Commit | Line | Data |
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0b1cf022 | 1 | /* opcode/i386.h -- Intel 80386 opcode macros |
4f1d9bd8 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
aa820537 | 3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 |
4f1d9bd8 | 4 | Free Software Foundation, Inc. |
252b5132 | 5 | |
543613e9 | 6 | This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. |
252b5132 | 7 | |
543613e9 NC |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
252b5132 | 12 | |
543613e9 NC |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
252b5132 | 17 | |
543613e9 NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
e172dbf8 | 20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
252b5132 | 21 | |
d0b47220 AM |
22 | /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived |
23 | ix86 Unix assemblers, generate floating point instructions with | |
24 | reversed source and destination registers in certain cases. | |
25 | Unfortunately, gcc and possibly many other programs use this | |
26 | reversed syntax, so we're stuck with it. | |
252b5132 | 27 | |
7f3f1ea2 AM |
28 | eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but |
29 | `fsub %st,%st(3)' results in st(3) = st - st(3), rather than | |
30 | the expected st(3) = st(3) - st | |
252b5132 RH |
31 | |
32 | This happens with all the non-commutative arithmetic floating point | |
33 | operations with two register operands, where the source register is | |
d796c0ad | 34 | %st, and destination register is %st(i). |
7f3f1ea2 AM |
35 | |
36 | The affected opcode map is dceX, dcfX, deeX, defX. */ | |
252b5132 | 37 | |
35669430 DE |
38 | #ifndef OPCODE_I386_H |
39 | #define OPCODE_I386_H | |
40 | ||
d0b47220 | 41 | #ifndef SYSV386_COMPAT |
252b5132 | 42 | /* Set non-zero for broken, compatible instructions. Set to zero for |
d0b47220 | 43 | non-broken opcodes at your peril. gcc generates SystemV/386 |
252b5132 | 44 | compatible instructions. */ |
d0b47220 AM |
45 | #define SYSV386_COMPAT 1 |
46 | #endif | |
47 | #ifndef OLDGCC_COMPAT | |
48 | /* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could | |
49 | generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands | |
50 | reversed. */ | |
51 | #define OLDGCC_COMPAT SYSV386_COMPAT | |
252b5132 | 52 | #endif |
252b5132 | 53 | |
252b5132 | 54 | #define MOV_AX_DISP32 0xa0 |
252b5132 | 55 | #define POP_SEG_SHORT 0x07 |
252b5132 | 56 | #define JUMP_PC_RELATIVE 0xeb |
543613e9 | 57 | #define INT_OPCODE 0xcd |
252b5132 | 58 | #define INT3_OPCODE 0xcc |
0b1cf022 L |
59 | /* The opcode for the fwait instruction, which disassembler treats as a |
60 | prefix when it can. */ | |
252b5132 | 61 | #define FWAIT_OPCODE 0x9b |
fedc618e DE |
62 | |
63 | /* Instruction prefixes. | |
64 | NOTE: For certain SSE* instructions, 0x66,0xf2,0xf3 are treated as | |
65 | part of the opcode. Other prefixes may still appear between them | |
66 | and the 0x0f part of the opcode. */ | |
252b5132 | 67 | #define ADDR_PREFIX_OPCODE 0x67 |
252b5132 | 68 | #define DATA_PREFIX_OPCODE 0x66 |
252b5132 | 69 | #define LOCK_PREFIX_OPCODE 0xf0 |
252b5132 | 70 | #define CS_PREFIX_OPCODE 0x2e |
252b5132 | 71 | #define DS_PREFIX_OPCODE 0x3e |
252b5132 | 72 | #define ES_PREFIX_OPCODE 0x26 |
252b5132 | 73 | #define FS_PREFIX_OPCODE 0x64 |
252b5132 | 74 | #define GS_PREFIX_OPCODE 0x65 |
252b5132 | 75 | #define SS_PREFIX_OPCODE 0x36 |
252b5132 RH |
76 | #define REPNE_PREFIX_OPCODE 0xf2 |
77 | #define REPE_PREFIX_OPCODE 0xf3 | |
050dfa73 | 78 | |
0b1cf022 L |
79 | #define TWO_BYTE_OPCODE_ESCAPE 0x0f |
80 | #define NOP_OPCODE (char) 0x90 | |
050dfa73 | 81 | |
0b1cf022 | 82 | /* register numbers */ |
35669430 DE |
83 | #define EAX_REG_NUM 0 |
84 | #define ECX_REG_NUM 1 | |
85 | #define EDX_REG_NUM 2 | |
86 | #define EBX_REG_NUM 3 | |
0b1cf022 | 87 | #define ESP_REG_NUM 4 |
35669430 DE |
88 | #define EBP_REG_NUM 5 |
89 | #define ESI_REG_NUM 6 | |
90 | #define EDI_REG_NUM 7 | |
050dfa73 | 91 | |
0b1cf022 L |
92 | /* modrm_byte.regmem for twobyte escape */ |
93 | #define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM | |
94 | /* index_base_byte.index for no index register addressing */ | |
95 | #define NO_INDEX_REGISTER ESP_REG_NUM | |
96 | /* index_base_byte.base for no base register addressing */ | |
97 | #define NO_BASE_REGISTER EBP_REG_NUM | |
98 | #define NO_BASE_REGISTER_16 6 | |
0f10071e | 99 | |
0b1cf022 L |
100 | /* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ |
101 | #define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ | |
102 | #define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) | |
252b5132 | 103 | |
35669430 DE |
104 | /* Extract fields from the mod/rm byte. */ |
105 | #define MODRM_MOD_FIELD(modrm) (((modrm) >> 6) & 3) | |
106 | #define MODRM_REG_FIELD(modrm) (((modrm) >> 3) & 7) | |
107 | #define MODRM_RM_FIELD(modrm) (((modrm) >> 0) & 7) | |
108 | ||
109 | /* Extract fields from the sib byte. */ | |
110 | #define SIB_SCALE_FIELD(sib) (((sib) >> 6) & 3) | |
111 | #define SIB_INDEX_FIELD(sib) (((sib) >> 3) & 7) | |
112 | #define SIB_BASE_FIELD(sib) (((sib) >> 0) & 7) | |
113 | ||
0b1cf022 L |
114 | /* x86-64 extension prefix. */ |
115 | #define REX_OPCODE 0x40 | |
252b5132 | 116 | |
35669430 DE |
117 | /* Non-zero if OPCODE is the rex prefix. */ |
118 | #define REX_PREFIX_P(opcode) (((opcode) & 0xf0) == REX_OPCODE) | |
119 | ||
0b1cf022 | 120 | /* Indicates 64 bit operand size. */ |
161a04f6 | 121 | #define REX_W 8 |
0b1cf022 | 122 | /* High extension to reg field of modrm byte. */ |
161a04f6 | 123 | #define REX_R 4 |
0b1cf022 | 124 | /* High extension to SIB index field. */ |
161a04f6 | 125 | #define REX_X 2 |
0b1cf022 | 126 | /* High extension to base field of modrm or SIB, or reg field of opcode. */ |
161a04f6 | 127 | #define REX_B 1 |
252b5132 | 128 | |
0b1cf022 | 129 | /* max operands per insn */ |
c0f3af97 | 130 | #define MAX_OPERANDS 5 |
252b5132 | 131 | |
0b1cf022 L |
132 | /* max immediates per insn (lcall, ljmp, insertq, extrq) */ |
133 | #define MAX_IMMEDIATE_OPERANDS 2 | |
5f47d35b | 134 | |
0b1cf022 L |
135 | /* max memory refs per insn (string ops) */ |
136 | #define MAX_MEMORY_OPERANDS 2 | |
252b5132 | 137 | |
0b1cf022 | 138 | /* max size of insn mnemonics. */ |
c0f3af97 | 139 | #define MAX_MNEM_SIZE 20 |
252b5132 | 140 | |
0b1cf022 L |
141 | /* max size of register name in insn mnemonics. */ |
142 | #define MAX_REG_NAME_SIZE 8 | |
35669430 DE |
143 | |
144 | #endif /* OPCODE_I386_H */ |