Commit | Line | Data |
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252b5132 | 1 | /* opcode/i386.h -- Intel 80386 opcode table |
4f1d9bd8 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
c3aa17e9 | 3 | 2000, 2001, 2002, 2003, 2004, 2005 |
4f1d9bd8 | 4 | Free Software Foundation, Inc. |
252b5132 | 5 | |
543613e9 | 6 | This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. |
252b5132 | 7 | |
543613e9 NC |
8 | This program is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
252b5132 | 12 | |
543613e9 NC |
13 | This program is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
252b5132 | 17 | |
543613e9 NC |
18 | You should have received a copy of the GNU General Public License |
19 | along with this program; if not, write to the Free Software | |
e172dbf8 | 20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
252b5132 | 21 | |
d0b47220 AM |
22 | /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived |
23 | ix86 Unix assemblers, generate floating point instructions with | |
24 | reversed source and destination registers in certain cases. | |
25 | Unfortunately, gcc and possibly many other programs use this | |
26 | reversed syntax, so we're stuck with it. | |
252b5132 | 27 | |
7f3f1ea2 AM |
28 | eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but |
29 | `fsub %st,%st(3)' results in st(3) = st - st(3), rather than | |
30 | the expected st(3) = st(3) - st | |
252b5132 RH |
31 | |
32 | This happens with all the non-commutative arithmetic floating point | |
33 | operations with two register operands, where the source register is | |
7f3f1ea2 AM |
34 | %st, and destination register is %st(i). See FloatDR below. |
35 | ||
36 | The affected opcode map is dceX, dcfX, deeX, defX. */ | |
252b5132 | 37 | |
d0b47220 | 38 | #ifndef SYSV386_COMPAT |
252b5132 | 39 | /* Set non-zero for broken, compatible instructions. Set to zero for |
d0b47220 | 40 | non-broken opcodes at your peril. gcc generates SystemV/386 |
252b5132 | 41 | compatible instructions. */ |
d0b47220 AM |
42 | #define SYSV386_COMPAT 1 |
43 | #endif | |
44 | #ifndef OLDGCC_COMPAT | |
45 | /* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could | |
46 | generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands | |
47 | reversed. */ | |
48 | #define OLDGCC_COMPAT SYSV386_COMPAT | |
252b5132 | 49 | #endif |
252b5132 | 50 | |
543613e9 NC |
51 | static const template i386_optab[] = |
52 | { | |
252b5132 RH |
53 | |
54 | #define X None | |
c0d8940f JH |
55 | #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) |
56 | #define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) | |
57 | #define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) | |
58 | #define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf|No_qSuf) | |
59 | #define q_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf) | |
60 | #define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_qSuf) | |
61 | #define bw_Suf (No_lSuf|No_sSuf|No_xSuf|No_qSuf) | |
62 | #define bl_Suf (No_wSuf|No_sSuf|No_xSuf|No_qSuf) | |
63 | #define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf) | |
64 | #define wlq_Suf (No_bSuf|No_sSuf|No_xSuf) | |
65 | #define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf) | |
85a33fe2 | 66 | #define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf) |
c0d8940f | 67 | #define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf) |
c0d8940f JH |
68 | #define bwl_Suf (No_sSuf|No_xSuf|No_qSuf) |
69 | #define bwlq_Suf (No_sSuf|No_xSuf) | |
9306ca4a JB |
70 | #define FP (NoSuf) |
71 | #define l_FP (l_Suf) | |
72 | #define q_FP (q_Suf|NoRex64) | |
73 | #define x_FP (x_Suf|FloatMF) | |
74 | #define sl_FP (sl_Suf|FloatMF) | |
d0b47220 | 75 | #if SYSV386_COMPAT |
7f3f1ea2 AM |
76 | /* Someone forgot that the FloatR bit reverses the operation when not |
77 | equal to the FloatD bit. ie. Changing only FloatD results in the | |
78 | destination being swapped *and* the direction being reversed. */ | |
252b5132 RH |
79 | #define FloatDR FloatD |
80 | #else | |
81 | #define FloatDR (FloatD|FloatR) | |
82 | #endif | |
83 | ||
d0b47220 | 84 | /* Move instructions. */ |
252b5132 | 85 | #define MOV_AX_DISP32 0xa0 |
b300c311 L |
86 | /* We put the 64bit displacement first and we only mark constants |
87 | larger than 32bit as Disp64. */ | |
88 | { "mov", 2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, | |
37edbb65 | 89 | { "mov", 2, 0xa0, X, CpuNo64,bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, |
c0d8940f JH |
90 | { "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, |
91 | /* In the 64bit mode the short form mov immediate is redefined to have | |
b300c311 | 92 | 64bit value. */ |
c0d8940f JH |
93 | { "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { EncImm, Reg8|Reg16|Reg32, 0 } }, |
94 | { "mov", 2, 0xc6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0 } }, | |
95 | { "mov", 2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, | |
e413e4e9 | 96 | /* The segment register moves accept WordReg so that a segment register |
252b5132 RH |
97 | can be copied to a 32 bit register, and vice versa, without using a |
98 | size prefix. When moving to a 32 bit register, the upper 16 bits | |
99 | are set to an implementation defined value (on the Pentium Pro, | |
100 | the implementation defined value is zero). */ | |
9306ca4a | 101 | { "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|InvMem, 0 } }, |
4cc91dba | 102 | { "mov", 2, 0x8c, X, 0, w_Suf|Modrm|IgnoreSize, { SReg2, WordMem, 0 } }, |
9306ca4a | 103 | { "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|InvMem, 0 } }, |
4cc91dba L |
104 | { "mov", 2, 0x8c, X, Cpu386, w_Suf|Modrm|IgnoreSize, { SReg3, WordMem, 0 } }, |
105 | { "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg, SReg2, 0 } }, | |
106 | { "mov", 2, 0x8e, X, 0, w_Suf|Modrm|IgnoreSize, { WordMem, SReg2, 0 } }, | |
107 | { "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg, SReg3, 0 } }, | |
108 | { "mov", 2, 0x8e, X, Cpu386, w_Suf|Modrm|IgnoreSize, { WordMem, SReg3, 0 } }, | |
c0d8940f JH |
109 | /* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit |
110 | mode they are 64bit.*/ | |
111 | { "mov", 2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|InvMem, 0} }, | |
112 | { "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} }, | |
113 | { "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} }, | |
114 | { "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} }, | |
37edbb65 | 115 | { "mov", 2, 0x0f24, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, |
c0d8940f JH |
116 | { "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, |
117 | { "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, | |
252b5132 | 118 | |
d0b47220 | 119 | /* Move with sign extend. */ |
252b5132 RH |
120 | /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid |
121 | conflict with the "movs" string move instruction. */ | |
e413e4e9 AM |
122 | {"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, |
123 | {"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, | |
c0d8940f JH |
124 | {"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem,Reg32, 0} }, |
125 | {"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, | |
126 | {"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} }, | |
127 | {"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, | |
9306ca4a | 128 | /* Intel Syntax next 3 insns */ |
e413e4e9 | 129 | {"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, |
9306ca4a | 130 | {"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} }, |
c0d8940f | 131 | {"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, |
252b5132 | 132 | |
bcb9eebe L |
133 | /* Move with zero extend. We can't remove "movzb" since existing |
134 | assembly codes may use it. */ | |
135 | {"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, | |
9306ca4a JB |
136 | /* "movzbl" & "movzbw" should not be unified into "movzb" for |
137 | consistency with the sign extending moves above. */ | |
138 | {"movzbl", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, | |
139 | {"movzbw", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, | |
e413e4e9 | 140 | {"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, |
9306ca4a | 141 | /* These instructions are not particulary useful, since the zero extend |
c0d8940f JH |
142 | 32->64 is implicit, but we can encode them. */ |
143 | {"movzbq", 2, 0x0fb6, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, | |
144 | {"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, | |
9306ca4a JB |
145 | /* Intel Syntax next 2 insns (the 64-bit variants are not particulary useful, |
146 | since the zero extend 32->64 is implicit, but we can encode them). */ | |
e413e4e9 | 147 | {"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, |
9306ca4a | 148 | {"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} }, |
252b5132 | 149 | |
d0b47220 | 150 | /* Push instructions. */ |
c0d8940f JH |
151 | {"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, |
152 | {"push", 1, 0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, | |
153 | {"push", 1, 0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, | |
154 | {"push", 1, 0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, | |
543613e9 | 155 | {"push", 1, 0x06, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, |
c0d8940f JH |
156 | {"push", 1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, |
157 | /* In 64bit mode, the operand size is implicitly 64bit. */ | |
543613e9 NC |
158 | {"push", 1, 0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } }, |
159 | {"push", 1, 0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } }, | |
160 | {"push", 1, 0x6a, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} }, | |
161 | {"push", 1, 0x68, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} }, | |
162 | {"push", 1, 0x0fa0, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, | |
c0d8940f | 163 | |
e2914f48 | 164 | {"pusha", 0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, |
252b5132 | 165 | |
d0b47220 | 166 | /* Pop instructions. */ |
c0d8940f JH |
167 | {"pop", 1, 0x58, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, |
168 | {"pop", 1, 0x8f, 0, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, | |
252b5132 | 169 | #define POP_SEG_SHORT 0x07 |
c0d8940f JH |
170 | {"pop", 1, 0x07, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, |
171 | {"pop", 1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, | |
172 | /* In 64bit mode, the operand size is implicitly 64bit. */ | |
543613e9 NC |
173 | {"pop", 1, 0x58, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } }, |
174 | {"pop", 1, 0x8f, 0, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } }, | |
85a33fe2 | 175 | {"pop", 1, 0x0fa1, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, |
c0d8940f JH |
176 | |
177 | {"popa", 0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, | |
252b5132 | 178 | |
d0b47220 | 179 | /* Exchange instructions. |
c0d8940f JH |
180 | xchg commutes: we allow both operand orders. |
181 | ||
46e883c5 | 182 | In the 64bit code, xchg rax, rax is reused for new nop instruction. */ |
543613e9 NC |
183 | {"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { WordReg, Acc, 0 } }, |
184 | {"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { Acc, WordReg, 0 } }, | |
185 | {"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Reg16|Reg64, Acc, 0 } }, | |
186 | {"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Acc, Reg16|Reg64, 0 } }, | |
c0d8940f JH |
187 | {"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, |
188 | {"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, | |
252b5132 | 189 | |
d0b47220 | 190 | /* In/out from ports. */ |
543613e9 | 191 | /* XXX should reject %rax */ |
85a33fe2 JH |
192 | {"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } }, |
193 | {"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, | |
194 | {"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, | |
195 | {"in", 1, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, | |
196 | {"out", 2, 0xe6, X, 0, bwl_Suf|W, { Acc, Imm8, 0 } }, | |
197 | {"out", 2, 0xee, X, 0, bwl_Suf|W, { Acc, InOutPortReg, 0 } }, | |
198 | {"out", 1, 0xe6, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, | |
199 | {"out", 1, 0xee, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, | |
252b5132 | 200 | |
d0b47220 | 201 | /* Load effective address. */ |
c0d8940f | 202 | {"lea", 2, 0x8d, X, 0, wlq_Suf|Modrm, { WordMem, WordReg, 0 } }, |
252b5132 | 203 | |
d0b47220 | 204 | /* Load segment registers from memory. */ |
543613e9 NC |
205 | {"lds", 2, 0xc5, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} }, |
206 | {"les", 2, 0xc4, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} }, | |
207 | {"lfs", 2, 0x0fb4, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, | |
208 | {"lgs", 2, 0x0fb5, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, | |
209 | {"lss", 2, 0x0fb2, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, | |
252b5132 | 210 | |
d0b47220 | 211 | /* Flags register instructions. */ |
e413e4e9 AM |
212 | {"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} }, |
213 | {"cld", 0, 0xfc, X, 0, NoSuf, { 0, 0, 0} }, | |
214 | {"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} }, | |
215 | {"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} }, | |
216 | {"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} }, | |
37edbb65 JB |
217 | {"lahf", 0, 0x9f, X, 0, NoSuf, { 0, 0, 0} }, |
218 | {"sahf", 0, 0x9e, X, 0, NoSuf, { 0, 0, 0} }, | |
543613e9 | 219 | {"pushf", 0, 0x9c, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, |
85a33fe2 | 220 | {"pushf", 0, 0x9c, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, |
543613e9 | 221 | {"popf", 0, 0x9d, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, |
85a33fe2 | 222 | {"popf", 0, 0x9d, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, |
e413e4e9 AM |
223 | {"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} }, |
224 | {"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} }, | |
225 | {"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} }, | |
252b5132 | 226 | |
d0b47220 | 227 | /* Arithmetic. */ |
c0d8940f JH |
228 | {"add", 2, 0x00, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, |
229 | {"add", 2, 0x83, 0, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
230 | {"add", 2, 0x04, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, | |
231 | {"add", 2, 0x80, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, | |
232 | ||
233 | {"inc", 1, 0x40, X, CpuNo64,wl_Suf|ShortForm, { WordReg, 0, 0} }, | |
234 | {"inc", 1, 0xfe, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
235 | ||
236 | {"sub", 2, 0x28, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, | |
237 | {"sub", 2, 0x83, 5, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
238 | {"sub", 2, 0x2c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, | |
239 | {"sub", 2, 0x80, 5, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, | |
240 | ||
241 | {"dec", 1, 0x48, X, CpuNo64, wl_Suf|ShortForm, { WordReg, 0, 0} }, | |
242 | {"dec", 1, 0xfe, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
243 | ||
244 | {"sbb", 2, 0x18, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, | |
245 | {"sbb", 2, 0x83, 3, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
246 | {"sbb", 2, 0x1c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, | |
247 | {"sbb", 2, 0x80, 3, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, | |
248 | ||
249 | {"cmp", 2, 0x38, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, | |
250 | {"cmp", 2, 0x83, 7, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
251 | {"cmp", 2, 0x3c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, | |
252 | {"cmp", 2, 0x80, 7, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, | |
253 | ||
c0d8940f | 254 | {"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} }, |
fda592e8 | 255 | {"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { AnyMem, Reg, 0} }, |
c0d8940f JH |
256 | {"test", 2, 0xa8, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, |
257 | {"test", 2, 0xf6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, | |
258 | ||
259 | {"and", 2, 0x20, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, | |
260 | {"and", 2, 0x83, 4, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
261 | {"and", 2, 0x24, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, | |
262 | {"and", 2, 0x80, 4, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, | |
263 | ||
264 | {"or", 2, 0x08, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, | |
265 | {"or", 2, 0x83, 1, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
266 | {"or", 2, 0x0c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, | |
267 | {"or", 2, 0x80, 1, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, | |
268 | ||
269 | {"xor", 2, 0x30, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, | |
270 | {"xor", 2, 0x83, 6, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
271 | {"xor", 2, 0x34, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, | |
272 | {"xor", 2, 0x80, 6, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, | |
e413e4e9 AM |
273 | |
274 | /* clr with 1 operand is really xor with 2 operands. */ | |
c0d8940f | 275 | {"clr", 1, 0x30, X, 0, bwlq_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, |
e413e4e9 | 276 | |
c0d8940f JH |
277 | {"adc", 2, 0x10, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, |
278 | {"adc", 2, 0x83, 2, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, | |
279 | {"adc", 2, 0x14, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, | |
280 | {"adc", 2, 0x80, 2, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, | |
e413e4e9 | 281 | |
c0d8940f JH |
282 | {"neg", 1, 0xf6, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, |
283 | {"not", 1, 0xf6, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
e413e4e9 | 284 | |
543613e9 NC |
285 | {"aaa", 0, 0x37, X, CpuNo64, NoSuf, { 0, 0, 0} }, |
286 | {"aas", 0, 0x3f, X, CpuNo64, NoSuf, { 0, 0, 0} }, | |
287 | {"daa", 0, 0x27, X, CpuNo64, NoSuf, { 0, 0, 0} }, | |
288 | {"das", 0, 0x2f, X, CpuNo64, NoSuf, { 0, 0, 0} }, | |
289 | {"aad", 0, 0xd50a, X, CpuNo64, NoSuf, { 0, 0, 0} }, | |
9a145ce6 | 290 | {"aad", 1, 0xd5, X, CpuNo64, NoSuf, { Imm8, 0, 0} }, |
543613e9 | 291 | {"aam", 0, 0xd40a, X, CpuNo64, NoSuf, { 0, 0, 0} }, |
9a145ce6 | 292 | {"aam", 1, 0xd4, X, CpuNo64, NoSuf, { Imm8, 0, 0} }, |
252b5132 | 293 | |
d0b47220 AM |
294 | /* Conversion insns. */ |
295 | /* Intel naming */ | |
e413e4e9 | 296 | {"cbw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, |
c0d8940f | 297 | {"cdqe", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, |
e413e4e9 AM |
298 | {"cwde", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, |
299 | {"cwd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, | |
300 | {"cdq", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, | |
c0d8940f | 301 | {"cqo", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, |
d0b47220 | 302 | /* AT&T naming */ |
e413e4e9 | 303 | {"cbtw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, |
c0d8940f | 304 | {"cltq", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, |
e413e4e9 AM |
305 | {"cwtl", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, |
306 | {"cwtd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, | |
307 | {"cltd", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, | |
c0d8940f | 308 | {"cqto", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, |
252b5132 RH |
309 | |
310 | /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are | |
311 | expanding 64-bit multiplies, and *cannot* be selected to accomplish | |
312 | 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) | |
313 | These multiplies can only be selected with single operand forms. */ | |
c0d8940f JH |
314 | {"mul", 1, 0xf6, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, |
315 | {"imul", 1, 0xf6, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
316 | {"imul", 2, 0x0faf, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
317 | {"imul", 3, 0x6b, X, Cpu186, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, | |
318 | {"imul", 3, 0x69, X, Cpu186, wlq_Suf|Modrm, { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} }, | |
252b5132 RH |
319 | /* imul with 2 operands mimics imul with 3 by putting the register in |
320 | both i.rm.reg & i.rm.regmem fields. regKludge enables this | |
321 | transformation. */ | |
c0d8940f JH |
322 | {"imul", 2, 0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} }, |
323 | {"imul", 2, 0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} }, | |
324 | ||
325 | {"div", 1, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
326 | {"div", 2, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, | |
327 | {"idiv", 1, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
328 | {"idiv", 2, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, | |
329 | ||
330 | {"rol", 2, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
331 | {"rol", 2, 0xc0, 0, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
332 | {"rol", 2, 0xd2, 0, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
333 | {"rol", 1, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
334 | ||
335 | {"ror", 2, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
336 | {"ror", 2, 0xc0, 1, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
337 | {"ror", 2, 0xd2, 1, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
338 | {"ror", 1, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
339 | ||
340 | {"rcl", 2, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
341 | {"rcl", 2, 0xc0, 2, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
342 | {"rcl", 2, 0xd2, 2, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
343 | {"rcl", 1, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
344 | ||
345 | {"rcr", 2, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
346 | {"rcr", 2, 0xc0, 3, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
347 | {"rcr", 2, 0xd2, 3, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
348 | {"rcr", 1, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
349 | ||
350 | {"sal", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
351 | {"sal", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
352 | {"sal", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
353 | {"sal", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
354 | ||
355 | {"shl", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
356 | {"shl", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
357 | {"shl", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
358 | {"shl", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
359 | ||
360 | {"shr", 2, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
361 | {"shr", 2, 0xc0, 5, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
362 | {"shr", 2, 0xd2, 5, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
363 | {"shr", 1, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
364 | ||
365 | {"sar", 2, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, | |
366 | {"sar", 2, 0xc0, 7, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, | |
367 | {"sar", 2, 0xd2, 7, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, | |
368 | {"sar", 1, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, | |
369 | ||
370 | {"shld", 3, 0x0fa4, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, | |
371 | {"shld", 3, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, | |
372 | {"shld", 2, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, | |
373 | ||
374 | {"shrd", 3, 0x0fac, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, | |
375 | {"shrd", 3, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, | |
376 | {"shrd", 2, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, | |
252b5132 | 377 | |
d0b47220 | 378 | /* Control transfer instructions. */ |
543613e9 NC |
379 | {"call", 1, 0xe8, X, CpuNo64, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, |
380 | {"call", 1, 0xe8, X, Cpu64, wq_Suf|JumpDword|DefaultSize|NoRex64, { Disp16|Disp32, 0, 0} }, | |
85a33fe2 | 381 | {"call", 1, 0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, |
543613e9 | 382 | {"call", 1, 0xff, 2, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem|LLongMem|JumpAbsolute, 0, 0} }, |
252b5132 | 383 | /* Intel Syntax */ |
543613e9 | 384 | {"call", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, |
3138f287 | 385 | /* Intel Syntax */ |
9306ca4a | 386 | {"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} }, |
543613e9 NC |
387 | {"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, {Imm16, Imm16|Imm32, 0} }, |
388 | {"lcall", 1, 0xff, 3, 0, wl_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} }, | |
252b5132 RH |
389 | |
390 | #define JUMP_PC_RELATIVE 0xeb | |
543613e9 | 391 | {"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp,0, 0} }, |
85a33fe2 | 392 | {"jmp", 1, 0xff, 4, CpuNo64, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, |
543613e9 NC |
393 | {"jmp", 1, 0xff, 4, Cpu64, wq_Suf|Modrm|NoRex64, { Reg16|Reg64|ShortMem|LLongMem|JumpAbsolute, 0, 0} }, |
394 | /* Intel Syntax. */ | |
c0d8940f | 395 | {"jmp", 2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, |
543613e9 | 396 | /* Intel Syntax. */ |
9306ca4a | 397 | {"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, |
543613e9 NC |
398 | {"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, |
399 | {"ljmp", 1, 0xff, 5, 0, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, | |
400 | ||
401 | {"ret", 0, 0xc3, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, | |
402 | {"ret", 1, 0xc2, X, CpuNo64,wl_Suf|DefaultSize, { Imm16, 0, 0} }, | |
403 | {"ret", 0, 0xc3, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, | |
404 | {"ret", 1, 0xc2, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} }, | |
c0d8940f JH |
405 | {"lret", 0, 0xcb, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, |
406 | {"lret", 1, 0xca, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} }, | |
543613e9 NC |
407 | {"enter", 2, 0xc8, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16, Imm8, 0} }, |
408 | {"enter", 2, 0xc8, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm16, Imm8, 0} }, | |
409 | {"leave", 0, 0xc9, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0} }, | |
410 | {"leave", 0, 0xc9, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { 0, 0, 0} }, | |
252b5132 | 411 | |
d0b47220 | 412 | /* Conditional jumps. */ |
e413e4e9 AM |
413 | {"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} }, |
414 | {"jno", 1, 0x71, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
415 | {"jb", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
416 | {"jc", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
417 | {"jnae", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
418 | {"jnb", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
419 | {"jnc", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
420 | {"jae", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
421 | {"je", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
422 | {"jz", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
423 | {"jne", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
424 | {"jnz", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
425 | {"jbe", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
426 | {"jna", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
427 | {"jnbe", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
428 | {"ja", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
429 | {"js", 1, 0x78, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
430 | {"jns", 1, 0x79, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
431 | {"jp", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
432 | {"jpe", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
433 | {"jnp", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
434 | {"jpo", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
435 | {"jl", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
436 | {"jnge", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
437 | {"jnl", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
438 | {"jge", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
439 | {"jle", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
440 | {"jng", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
441 | {"jnle", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
442 | {"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, | |
252b5132 RH |
443 | |
444 | /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ | |
85a33fe2 JH |
445 | {"jcxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} }, |
446 | {"jecxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, | |
447 | {"jecxz", 1, 0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, | |
448 | {"jrcxz", 1, 0xe3, X, Cpu64, NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} }, | |
252b5132 RH |
449 | |
450 | /* The loop instructions also use the address size prefix to select | |
451 | %cx rather than %ecx for the loop count, so the `w' form of these | |
452 | instructions emit an address size prefix rather than a data size | |
453 | prefix. */ | |
85a33fe2 JH |
454 | {"loop", 1, 0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, |
455 | {"loop", 1, 0xe2, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, | |
456 | {"loopz", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, | |
457 | {"loopz", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, | |
458 | {"loope", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, | |
459 | {"loope", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, | |
460 | {"loopnz", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, | |
461 | {"loopnz", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, | |
462 | {"loopne", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, | |
463 | {"loopne", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, | |
252b5132 | 464 | |
d0b47220 | 465 | /* Set byte on flag instructions. */ |
e413e4e9 AM |
466 | {"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, |
467 | {"setno", 1, 0x0f91, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
468 | {"setb", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
469 | {"setc", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
470 | {"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
471 | {"setnb", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
472 | {"setnc", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
473 | {"setae", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
474 | {"sete", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
475 | {"setz", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
476 | {"setne", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
477 | {"setnz", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
478 | {"setbe", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
479 | {"setna", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
480 | {"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
481 | {"seta", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
482 | {"sets", 1, 0x0f98, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
483 | {"setns", 1, 0x0f99, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
484 | {"setp", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
485 | {"setpe", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
486 | {"setnp", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
487 | {"setpo", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
488 | {"setl", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
489 | {"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
490 | {"setnl", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
491 | {"setge", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
492 | {"setle", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
493 | {"setng", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
494 | {"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
495 | {"setg", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, | |
252b5132 | 496 | |
d0b47220 | 497 | /* String manipulation. */ |
c0d8940f JH |
498 | {"cmps", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, |
499 | {"cmps", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, | |
500 | {"scmp", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, | |
501 | {"scmp", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, | |
85a33fe2 JH |
502 | {"ins", 0, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, |
503 | {"ins", 2, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} }, | |
504 | {"outs", 0, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, | |
505 | {"outs", 2, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { AnyMem, InOutPortReg, 0} }, | |
c0d8940f JH |
506 | {"lods", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, |
507 | {"lods", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, | |
508 | {"lods", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, | |
509 | {"slod", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, | |
510 | {"slod", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, | |
511 | {"slod", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, | |
512 | {"movs", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, | |
513 | {"movs", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, | |
514 | {"smov", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, | |
515 | {"smov", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, | |
516 | {"scas", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, | |
517 | {"scas", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, | |
518 | {"scas", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, | |
519 | {"ssca", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, | |
520 | {"ssca", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, | |
521 | {"ssca", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, | |
522 | {"stos", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, | |
523 | {"stos", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, | |
524 | {"stos", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, | |
525 | {"ssto", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, | |
526 | {"ssto", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, | |
527 | {"ssto", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, | |
e413e4e9 AM |
528 | {"xlat", 0, 0xd7, X, 0, b_Suf|IsString, { 0, 0, 0} }, |
529 | {"xlat", 1, 0xd7, X, 0, b_Suf|IsString, { AnyMem, 0, 0} }, | |
252b5132 | 530 | |
d0b47220 | 531 | /* Bit manipulation. */ |
c0d8940f JH |
532 | {"bsf", 2, 0x0fbc, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, |
533 | {"bsr", 2, 0x0fbd, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
534 | {"bt", 2, 0x0fa3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, | |
535 | {"bt", 2, 0x0fba, 4, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, | |
536 | {"btc", 2, 0x0fbb, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, | |
537 | {"btc", 2, 0x0fba, 7, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, | |
538 | {"btr", 2, 0x0fb3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, | |
539 | {"btr", 2, 0x0fba, 6, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, | |
540 | {"bts", 2, 0x0fab, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, | |
541 | {"bts", 2, 0x0fba, 5, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, | |
252b5132 | 542 | |
d0b47220 | 543 | /* Interrupts & op. sys insns. */ |
252b5132 | 544 | /* See gas/config/tc-i386.c for conversion of 'int $3' into the special |
d0b47220 | 545 | int 3 insn. */ |
543613e9 | 546 | #define INT_OPCODE 0xcd |
252b5132 | 547 | #define INT3_OPCODE 0xcc |
e413e4e9 AM |
548 | {"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} }, |
549 | {"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} }, | |
543613e9 | 550 | {"into", 0, 0xce, X, CpuNo64, NoSuf, { 0, 0, 0} }, |
c0d8940f | 551 | {"iret", 0, 0xcf, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, |
d0b47220 | 552 | /* i386sl, i486sl, later 486, and Pentium. */ |
e413e4e9 | 553 | {"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} }, |
252b5132 | 554 | |
543613e9 | 555 | {"bound", 2, 0x62, X, Cpu186|CpuNo64, wl_Suf|Modrm, { WordReg, WordMem, 0} }, |
252b5132 | 556 | |
e413e4e9 | 557 | {"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} }, |
15965411 L |
558 | |
559 | {"nop", 1, 0x0f1f, X, Cpu686, wl_Suf|Modrm, { WordMem, 0, 0} }, | |
560 | ||
561 | /* nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in | |
562 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ | |
e413e4e9 | 563 | {"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} }, |
252b5132 | 564 | |
d0b47220 | 565 | /* Protection control. */ |
543613e9 | 566 | {"arpl", 2, 0x63, X, Cpu286|CpuNo64, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, |
c0d8940f | 567 | {"lar", 2, 0x0f02, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, |
543613e9 NC |
568 | {"lgdt", 1, 0x0f01, 2, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, |
569 | {"lgdt", 1, 0x0f01, 2, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, | |
570 | {"lidt", 1, 0x0f01, 3, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, | |
571 | {"lidt", 1, 0x0f01, 3, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, | |
e413e4e9 AM |
572 | {"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, |
573 | {"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, | |
c0d8940f | 574 | {"lsl", 2, 0x0f03, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, |
e413e4e9 AM |
575 | {"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, |
576 | ||
543613e9 NC |
577 | {"sgdt", 1, 0x0f01, 0, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, |
578 | {"sgdt", 1, 0x0f01, 0, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, | |
579 | {"sidt", 1, 0x0f01, 1, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, | |
37edbb65 | 580 | {"sidt", 1, 0x0f01, 1, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, |
e5470cdc AM |
581 | {"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, |
582 | {"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, | |
583 | {"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, | |
584 | {"smsw", 1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, | |
585 | {"str", 1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, | |
586 | {"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, | |
e413e4e9 AM |
587 | |
588 | {"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, | |
589 | {"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, | |
252b5132 | 590 | |
d0b47220 | 591 | /* Floating point instructions. */ |
252b5132 RH |
592 | |
593 | /* load */ | |
e413e4e9 | 594 | {"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, |
9306ca4a JB |
595 | {"fld", 1, 0xd9, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, |
596 | {"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, | |
252b5132 | 597 | /* Intel Syntax */ |
e413e4e9 | 598 | {"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} }, |
9306ca4a JB |
599 | {"fild", 1, 0xdf, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, |
600 | {"fild", 1, 0xdf, 5, 0, q_FP|Modrm, { LLongMem, 0, 0} }, | |
e413e4e9 AM |
601 | {"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, |
602 | {"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, | |
9ae09ff9 | 603 | {"fbld", 1, 0xdf, 4, 0, x_Suf|Modrm, { LLongMem, 0, 0} }, |
252b5132 RH |
604 | |
605 | /* store (no pop) */ | |
e413e4e9 | 606 | {"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, |
9306ca4a JB |
607 | {"fst", 1, 0xd9, 2, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, |
608 | {"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, | |
609 | {"fist", 1, 0xdf, 2, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 RH |
610 | |
611 | /* store (with pop) */ | |
e413e4e9 | 612 | {"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, |
9306ca4a JB |
613 | {"fstp", 1, 0xd9, 3, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, |
614 | {"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, | |
252b5132 | 615 | /* Intel Syntax */ |
e413e4e9 | 616 | {"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} }, |
9306ca4a JB |
617 | {"fistp", 1, 0xdf, 3, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, |
618 | {"fistp", 1, 0xdf, 7, 0, q_FP|Modrm, { LLongMem, 0, 0} }, | |
e413e4e9 AM |
619 | {"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, |
620 | {"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, | |
9ae09ff9 | 621 | {"fbstp", 1, 0xdf, 6, 0, x_Suf|Modrm, { LLongMem, 0, 0} }, |
252b5132 RH |
622 | |
623 | /* exchange %st<n> with %st0 */ | |
e413e4e9 AM |
624 | {"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, |
625 | /* alias for fxch %st(1) */ | |
626 | {"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
627 | |
628 | /* comparison (without pop) */ | |
e413e4e9 AM |
629 | {"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, |
630 | /* alias for fcom %st(1) */ | |
631 | {"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} }, | |
9306ca4a JB |
632 | {"fcom", 1, 0xd8, 2, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, |
633 | {"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, | |
634 | {"ficom", 1, 0xde, 2, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 RH |
635 | |
636 | /* comparison (with pop) */ | |
e413e4e9 AM |
637 | {"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, |
638 | /* alias for fcomp %st(1) */ | |
639 | {"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} }, | |
9306ca4a JB |
640 | {"fcomp", 1, 0xd8, 3, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, |
641 | {"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, | |
642 | {"ficomp", 1, 0xde, 3, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, | |
e413e4e9 | 643 | {"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} }, |
252b5132 RH |
644 | |
645 | /* unordered comparison (with pop) */ | |
e413e4e9 AM |
646 | {"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, |
647 | /* alias for fucom %st(1) */ | |
648 | {"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} }, | |
649 | {"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, | |
650 | /* alias for fucomp %st(1) */ | |
651 | {"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} }, | |
652 | {"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} }, | |
252b5132 | 653 | |
e413e4e9 AM |
654 | {"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} }, |
655 | {"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
656 | |
657 | /* load constants into %st0 */ | |
e413e4e9 AM |
658 | {"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} }, |
659 | {"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} }, | |
660 | {"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} }, | |
661 | {"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} }, | |
662 | {"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} }, | |
663 | {"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} }, | |
664 | {"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} }, | |
252b5132 | 665 | |
543613e9 | 666 | /* Arithmetic. */ |
252b5132 RH |
667 | |
668 | /* add */ | |
e413e4e9 AM |
669 | {"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, |
670 | /* alias for fadd %st(i), %st */ | |
671 | {"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
d0b47220 | 672 | #if SYSV386_COMPAT |
e413e4e9 AM |
673 | /* alias for faddp */ |
674 | {"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} }, | |
252b5132 | 675 | #endif |
9306ca4a JB |
676 | {"fadd", 1, 0xd8, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, |
677 | {"fiadd", 1, 0xde, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 | 678 | |
e413e4e9 AM |
679 | {"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
680 | {"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
681 | /* alias for faddp %st, %st(1) */ | |
682 | {"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} }, | |
683 | {"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, | |
252b5132 RH |
684 | |
685 | /* subtract */ | |
e413e4e9 AM |
686 | {"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, |
687 | {"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
d0b47220 | 688 | #if SYSV386_COMPAT |
e413e4e9 AM |
689 | /* alias for fsubp */ |
690 | {"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} }, | |
252b5132 | 691 | #endif |
9306ca4a JB |
692 | {"fsub", 1, 0xd8, 4, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, |
693 | {"fisub", 1, 0xde, 4, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 | 694 | |
d0b47220 | 695 | #if SYSV386_COMPAT |
e413e4e9 AM |
696 | {"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
697 | {"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
698 | {"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, | |
d0b47220 | 699 | #if OLDGCC_COMPAT |
e413e4e9 | 700 | {"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, |
d0b47220 | 701 | #endif |
252b5132 | 702 | #else |
e413e4e9 AM |
703 | {"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
704 | {"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
705 | {"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
706 | #endif |
707 | ||
708 | /* subtract reverse */ | |
e413e4e9 AM |
709 | {"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, |
710 | {"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
d0b47220 | 711 | #if SYSV386_COMPAT |
e413e4e9 AM |
712 | /* alias for fsubrp */ |
713 | {"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} }, | |
252b5132 | 714 | #endif |
9306ca4a JB |
715 | {"fsubr", 1, 0xd8, 5, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, |
716 | {"fisubr", 1, 0xde, 5, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 | 717 | |
d0b47220 | 718 | #if SYSV386_COMPAT |
e413e4e9 AM |
719 | {"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
720 | {"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
721 | {"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, | |
d0b47220 | 722 | #if OLDGCC_COMPAT |
e413e4e9 | 723 | {"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, |
d0b47220 | 724 | #endif |
252b5132 | 725 | #else |
e413e4e9 AM |
726 | {"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
727 | {"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
728 | {"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
729 | #endif |
730 | ||
731 | /* multiply */ | |
e413e4e9 AM |
732 | {"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, |
733 | {"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
d0b47220 | 734 | #if SYSV386_COMPAT |
e413e4e9 AM |
735 | /* alias for fmulp */ |
736 | {"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} }, | |
252b5132 | 737 | #endif |
9306ca4a JB |
738 | {"fmul", 1, 0xd8, 1, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, |
739 | {"fimul", 1, 0xde, 1, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 | 740 | |
e413e4e9 AM |
741 | {"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
742 | {"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
743 | {"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} }, | |
744 | {"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, | |
252b5132 RH |
745 | |
746 | /* divide */ | |
e413e4e9 AM |
747 | {"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, |
748 | {"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
d0b47220 | 749 | #if SYSV386_COMPAT |
e413e4e9 AM |
750 | /* alias for fdivp */ |
751 | {"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} }, | |
252b5132 | 752 | #endif |
9306ca4a JB |
753 | {"fdiv", 1, 0xd8, 6, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, |
754 | {"fidiv", 1, 0xde, 6, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 | 755 | |
d0b47220 | 756 | #if SYSV386_COMPAT |
e413e4e9 AM |
757 | {"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
758 | {"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
759 | {"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, | |
d0b47220 | 760 | #if OLDGCC_COMPAT |
e413e4e9 | 761 | {"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, |
d0b47220 | 762 | #endif |
252b5132 | 763 | #else |
e413e4e9 AM |
764 | {"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
765 | {"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
766 | {"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
767 | #endif |
768 | ||
769 | /* divide reverse */ | |
e413e4e9 AM |
770 | {"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, |
771 | {"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
d0b47220 | 772 | #if SYSV386_COMPAT |
e413e4e9 AM |
773 | /* alias for fdivrp */ |
774 | {"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} }, | |
252b5132 | 775 | #endif |
9306ca4a JB |
776 | {"fdivr", 1, 0xd8, 7, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, |
777 | {"fidivr", 1, 0xde, 7, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, | |
252b5132 | 778 | |
d0b47220 | 779 | #if SYSV386_COMPAT |
e413e4e9 AM |
780 | {"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
781 | {"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
782 | {"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, | |
d0b47220 | 783 | #if OLDGCC_COMPAT |
e413e4e9 | 784 | {"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, |
d0b47220 | 785 | #endif |
252b5132 | 786 | #else |
e413e4e9 AM |
787 | {"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, |
788 | {"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
789 | {"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
790 | #endif |
791 | ||
e413e4e9 AM |
792 | {"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} }, |
793 | {"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} }, | |
794 | {"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} }, | |
795 | {"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} }, | |
796 | {"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} }, | |
797 | {"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} }, | |
798 | {"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} }, | |
799 | {"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} }, | |
800 | {"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} }, | |
801 | {"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} }, | |
802 | {"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} }, | |
803 | {"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} }, | |
804 | {"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} }, | |
805 | {"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} }, | |
806 | {"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} }, | |
807 | {"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} }, | |
808 | {"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} }, | |
809 | {"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} }, | |
252b5132 RH |
810 | |
811 | /* processor control */ | |
e413e4e9 AM |
812 | {"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} }, |
813 | {"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} }, | |
9ae09ff9 JB |
814 | {"fldcw", 1, 0xd9, 5, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, |
815 | {"fnstcw", 1, 0xd9, 7, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, | |
816 | {"fstcw", 1, 0xd9, 7, 0, w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} }, | |
9306ca4a JB |
817 | /* XXX should reject %al, %eax, and %rax */ |
818 | {"fnstsw", 1, 0xdfe0, X, 0, FP|IgnoreSize, { Acc, 0, 0} }, | |
9ae09ff9 | 819 | {"fnstsw", 1, 0xdd, 7, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, |
e413e4e9 | 820 | {"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} }, |
9306ca4a JB |
821 | /* XXX should reject %al, %eax, and %rax */ |
822 | {"fstsw", 1, 0xdfe0, X, 0, FP|FWait|IgnoreSize, { Acc, 0, 0} }, | |
9ae09ff9 | 823 | {"fstsw", 1, 0xdd, 7, 0, w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} }, |
e413e4e9 AM |
824 | {"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} }, |
825 | {"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} }, | |
826 | {"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} }, | |
d0b47220 | 827 | /* Short forms of fldenv, fstenv use data size prefix. */ |
9306ca4a JB |
828 | {"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, |
829 | {"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm|DefaultSize, { LLongMem, 0, 0} }, | |
830 | {"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, | |
831 | {"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, | |
832 | {"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm|DefaultSize, { LLongMem, 0, 0} }, | |
833 | {"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, | |
e413e4e9 AM |
834 | |
835 | {"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, | |
252b5132 | 836 | /* P6:free st(i), pop st */ |
e413e4e9 AM |
837 | {"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, |
838 | {"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} }, | |
252b5132 | 839 | #define FWAIT_OPCODE 0x9b |
e413e4e9 | 840 | {"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} }, |
252b5132 | 841 | |
d0b47220 AM |
842 | /* Opcode prefixes; we allow them as separate insns too. */ |
843 | ||
252b5132 | 844 | #define ADDR_PREFIX_OPCODE 0x67 |
543613e9 NC |
845 | {"addr16", 0, 0x67, X, Cpu386|CpuNo64, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, |
846 | {"addr32", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, | |
847 | {"aword", 0, 0x67, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, | |
848 | {"adword", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, | |
252b5132 | 849 | #define DATA_PREFIX_OPCODE 0x66 |
543613e9 NC |
850 | {"data16", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, |
851 | {"data32", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, | |
852 | {"word", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, | |
853 | {"dword", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, | |
252b5132 | 854 | #define LOCK_PREFIX_OPCODE 0xf0 |
e413e4e9 AM |
855 | {"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, |
856 | {"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, | |
252b5132 | 857 | #define CS_PREFIX_OPCODE 0x2e |
9a45f1c2 | 858 | {"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, |
252b5132 | 859 | #define DS_PREFIX_OPCODE 0x3e |
9a45f1c2 | 860 | {"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, |
252b5132 | 861 | #define ES_PREFIX_OPCODE 0x26 |
543613e9 | 862 | {"es", 0, 0x26, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} }, |
252b5132 | 863 | #define FS_PREFIX_OPCODE 0x64 |
e413e4e9 | 864 | {"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, |
252b5132 | 865 | #define GS_PREFIX_OPCODE 0x65 |
e413e4e9 | 866 | {"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, |
252b5132 | 867 | #define SS_PREFIX_OPCODE 0x36 |
543613e9 | 868 | {"ss", 0, 0x36, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} }, |
252b5132 RH |
869 | #define REPNE_PREFIX_OPCODE 0xf2 |
870 | #define REPE_PREFIX_OPCODE 0xf3 | |
e413e4e9 AM |
871 | {"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, |
872 | {"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, | |
873 | {"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, | |
874 | {"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, | |
875 | {"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, | |
e44823cf JB |
876 | {"ht", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, |
877 | {"hnt", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, | |
c0d8940f JH |
878 | {"rex", 0, 0x40, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, |
879 | {"rexz", 0, 0x41, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
880 | {"rexy", 0, 0x42, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
881 | {"rexyz", 0, 0x43, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
882 | {"rexx", 0, 0x44, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
883 | {"rexxz", 0, 0x45, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
884 | {"rexxy", 0, 0x46, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
885 | {"rexxyz", 0, 0x47, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
886 | {"rex64", 0, 0x48, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
887 | {"rex64z", 0, 0x49, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
888 | {"rex64y", 0, 0x4a, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
889 | {"rex64yz",0, 0x4b, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
890 | {"rex64x", 0, 0x4c, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
891 | {"rex64xz",0, 0x4d, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
892 | {"rex64xy",0, 0x4e, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
893 | {"rex64xyz",0, 0x4f, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, | |
252b5132 | 894 | |
d0b47220 | 895 | /* 486 extensions. */ |
252b5132 | 896 | |
c0d8940f JH |
897 | {"bswap", 1, 0x0fc8, X, Cpu486, lq_Suf|ShortForm, { Reg32|Reg64, 0, 0 } }, |
898 | {"xadd", 2, 0x0fc0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, | |
899 | {"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, | |
e413e4e9 AM |
900 | {"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} }, |
901 | {"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} }, | |
9306ca4a | 902 | {"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm|IgnoreSize, { AnyMem, 0, 0} }, |
252b5132 | 903 | |
d0b47220 | 904 | /* 586 and late 486 extensions. */ |
e413e4e9 | 905 | {"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} }, |
252b5132 | 906 | |
d0b47220 | 907 | /* Pentium extensions. */ |
e413e4e9 AM |
908 | {"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} }, |
909 | {"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} }, | |
910 | {"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} }, | |
9306ca4a | 911 | {"cmpxchg8b",1,0x0fc7, 1, Cpu586, q_Suf|Modrm, { LLongMem, 0, 0} }, |
252b5132 | 912 | |
558b0a60 | 913 | /* Pentium II/Pentium Pro extensions. */ |
4fd61dcb JJ |
914 | {"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} }, |
915 | {"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} }, | |
37edbb65 JB |
916 | {"fxsave", 1, 0x0fae, 0, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} }, |
917 | {"fxrstor", 1, 0x0fae, 1, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} }, | |
e413e4e9 AM |
918 | {"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} }, |
919 | /* official undefined instr. */ | |
920 | {"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, | |
921 | /* alias for ud2 */ | |
922 | {"ud2a", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, | |
923 | /* 2nd. official undefined instr. */ | |
924 | {"ud2b", 0, 0x0fb9, X, Cpu686, NoSuf, { 0, 0, 0} }, | |
925 | ||
c0d8940f JH |
926 | {"cmovo", 2, 0x0f40, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, |
927 | {"cmovno", 2, 0x0f41, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
928 | {"cmovb", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
929 | {"cmovc", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
930 | {"cmovnae", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
931 | {"cmovae", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
932 | {"cmovnc", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
933 | {"cmovnb", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
934 | {"cmove", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
935 | {"cmovz", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
936 | {"cmovne", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
937 | {"cmovnz", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
938 | {"cmovbe", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
939 | {"cmovna", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
940 | {"cmova", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
941 | {"cmovnbe", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
942 | {"cmovs", 2, 0x0f48, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
943 | {"cmovns", 2, 0x0f49, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
944 | {"cmovp", 2, 0x0f4a, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
945 | {"cmovnp", 2, 0x0f4b, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
946 | {"cmovl", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
947 | {"cmovnge", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
948 | {"cmovge", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
949 | {"cmovnl", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
950 | {"cmovle", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
951 | {"cmovng", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
952 | {"cmovg", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
953 | {"cmovnle", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, | |
e413e4e9 AM |
954 | |
955 | {"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
956 | {"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
957 | {"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
958 | {"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
959 | {"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
960 | {"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
961 | {"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
962 | {"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
963 | {"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
964 | {"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
965 | {"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
966 | {"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
967 | ||
968 | {"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
969 | {"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, | |
970 | {"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, | |
971 | {"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
972 | {"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, | |
973 | {"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, | |
974 | {"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
975 | {"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
976 | {"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, | |
977 | {"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, | |
978 | {"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
979 | {"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, | |
980 | {"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, | |
981 | {"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, | |
252b5132 | 982 | |
6f8c0c4c JH |
983 | /* Pentium4 extensions. */ |
984 | ||
9306ca4a JB |
985 | {"movnti", 2, 0x0fc3, X, CpuP4, wlq_Suf|Modrm, { WordReg, WordMem, 0 } }, |
986 | {"clflush", 1, 0x0fae, 7, CpuP4, NoSuf|Modrm|IgnoreSize, { ByteMem, 0, 0 } }, | |
987 | {"lfence", 0, 0x0fae, 0xe8, CpuP4, NoSuf|ImmExt, { 0, 0, 0 } }, | |
988 | {"mfence", 0, 0x0fae, 0xf0, CpuP4, NoSuf|ImmExt, { 0, 0, 0 } }, | |
989 | {"pause", 0, 0xf390, X, CpuP4, NoSuf, { 0, 0, 0 } }, | |
6f8c0c4c JH |
990 | |
991 | /* MMX/SSE2 instructions. */ | |
252b5132 | 992 | |
9306ca4a | 993 | {"emms", 0, 0x0f77, X, CpuMMX, NoSuf, { 0, 0, 0 } }, |
8b5328ac JB |
994 | /* These really shouldn't allow for Reg64 (movq is the right mnemonic for |
995 | copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's | |
996 | spec). AMD's spec, having been in existence for much longer, failed to | |
997 | recognize that and specified movd for 32- and 64-bit operations. */ | |
9306ca4a JB |
998 | {"movd", 2, 0x0f6e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegMMX, 0 } }, |
999 | {"movd", 2, 0x0f7e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64|LongMem, 0 } }, | |
8b5328ac JB |
1000 | {"movd", 2, 0x660f6e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegXMM, 0 } }, |
1001 | {"movd", 2, 0x660f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64|LongMem, 0 } }, | |
85a33fe2 JH |
1002 | /* In the 64bit mode the short form mov immediate is redefined to have |
1003 | 64bit displacement value. */ | |
8b5328ac JB |
1004 | {"movq", 2, 0x0f6f, X, CpuMMX, NoSuf|IgnoreSize|Modrm|NoRex64, { RegMMX|LLongMem, RegMMX, 0 } }, |
1005 | {"movq", 2, 0x0f7f, X, CpuMMX, NoSuf|IgnoreSize|Modrm|NoRex64, { RegMMX, RegMMX|LLongMem, 0 } }, | |
1006 | {"movq", 2, 0xf30f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm|NoRex64, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1007 | {"movq", 2, 0x660fd6,X,CpuSSE2,NoSuf|IgnoreSize|Modrm|NoRex64, { RegXMM, RegXMM|LLongMem, 0 } }, | |
1008 | {"movq", 2, 0x0f6e, X, Cpu64, NoSuf|IgnoreSize|Modrm, { Reg64|LLongMem, RegMMX, 0 } }, | |
1009 | {"movq", 2, 0x0f7e, X, Cpu64, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg64|LLongMem, 0 } }, | |
1010 | {"movq", 2, 0x660f6e,X,Cpu64, NoSuf|IgnoreSize|Modrm, { Reg64|LLongMem, RegXMM, 0 } }, | |
1011 | {"movq", 2, 0x660f7e,X,Cpu64, NoSuf|IgnoreSize|Modrm, { RegXMM, Reg64|LLongMem, 0 } }, | |
b300c311 L |
1012 | /* We put the 64bit displacement first and we only mark constants |
1013 | larger than 32bit as Disp64. */ | |
1014 | {"movq", 2, 0xa0, X, Cpu64, NoSuf|D|W|Size64, { Disp64, Acc, 0 } }, | |
c0d8940f JH |
1015 | {"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } }, |
1016 | {"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } }, | |
1017 | {"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } }, | |
4cc91dba L |
1018 | /* The segment register moves accept Reg64 so that a segment register |
1019 | can be copied to a 64 bit register, and vice versa. */ | |
1020 | {"movq", 2, 0x8c, X, Cpu64, NoSuf|Modrm|Size64, { SReg2|SReg3, Reg64|InvMem, 0 } }, | |
1021 | {"movq", 2, 0x8e, X, Cpu64, NoSuf|Modrm|Size64, { Reg64, SReg2|SReg3, 0 } }, | |
c0d8940f JH |
1022 | /* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit |
1023 | mode they are 64bit.*/ | |
1024 | {"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} }, | |
1025 | {"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} }, | |
9306ca4a JB |
1026 | /* Real MMX instructions. */ |
1027 | {"packssdw", 2, 0x0f6b, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1028 | {"packssdw", 2, 0x660f6b,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1029 | {"packsswb", 2, 0x0f63, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1030 | {"packsswb", 2, 0x660f63,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1031 | {"packuswb", 2, 0x0f67, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1032 | {"packuswb", 2, 0x660f67,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1033 | {"paddb", 2, 0x0ffc, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1034 | {"paddb", 2, 0x660ffc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1035 | {"paddw", 2, 0x0ffd, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1036 | {"paddw", 2, 0x660ffd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1037 | {"paddd", 2, 0x0ffe, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1038 | {"paddd", 2, 0x660ffe,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
5c6af06e | 1039 | {"paddq", 2, 0x0fd4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, |
9306ca4a JB |
1040 | {"paddq", 2, 0x660fd4,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
1041 | {"paddsb", 2, 0x0fec, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1042 | {"paddsb", 2, 0x660fec,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1043 | {"paddsw", 2, 0x0fed, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1044 | {"paddsw", 2, 0x660fed,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1045 | {"paddusb", 2, 0x0fdc, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1046 | {"paddusb", 2, 0x660fdc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1047 | {"paddusw", 2, 0x0fdd, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1048 | {"paddusw", 2, 0x660fdd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1049 | {"pand", 2, 0x0fdb, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1050 | {"pand", 2, 0x660fdb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1051 | {"pandn", 2, 0x0fdf, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1052 | {"pandn", 2, 0x660fdf,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1053 | {"pcmpeqb", 2, 0x0f74, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1054 | {"pcmpeqb", 2, 0x660f74,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1055 | {"pcmpeqw", 2, 0x0f75, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1056 | {"pcmpeqw", 2, 0x660f75,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1057 | {"pcmpeqd", 2, 0x0f76, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1058 | {"pcmpeqd", 2, 0x660f76,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1059 | {"pcmpgtb", 2, 0x0f64, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1060 | {"pcmpgtb", 2, 0x660f64,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1061 | {"pcmpgtw", 2, 0x0f65, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1062 | {"pcmpgtw", 2, 0x660f65,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1063 | {"pcmpgtd", 2, 0x0f66, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1064 | {"pcmpgtd", 2, 0x660f66,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1065 | {"pmaddwd", 2, 0x0ff5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1066 | {"pmaddwd", 2, 0x660ff5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1067 | {"pmulhw", 2, 0x0fe5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1068 | {"pmulhw", 2, 0x660fe5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1069 | {"pmullw", 2, 0x0fd5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1070 | {"pmullw", 2, 0x660fd5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1071 | {"por", 2, 0x0feb, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1072 | {"por", 2, 0x660feb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1073 | {"psllw", 2, 0x0ff1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1074 | {"psllw", 2, 0x660ff1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1075 | {"psllw", 2, 0x0f71, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, | |
1076 | {"psllw", 2, 0x660f71,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, | |
1077 | {"pslld", 2, 0x0ff2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1078 | {"pslld", 2, 0x660ff2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1079 | {"pslld", 2, 0x0f72, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, | |
1080 | {"pslld", 2, 0x660f72,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, | |
1081 | {"psllq", 2, 0x0ff3, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1082 | {"psllq", 2, 0x660ff3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1083 | {"psllq", 2, 0x0f73, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, | |
1084 | {"psllq", 2, 0x660f73,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, | |
1085 | {"psraw", 2, 0x0fe1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1086 | {"psraw", 2, 0x660fe1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1087 | {"psraw", 2, 0x0f71, 4, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, | |
1088 | {"psraw", 2, 0x660f71,4,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, | |
1089 | {"psrad", 2, 0x0fe2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1090 | {"psrad", 2, 0x660fe2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1091 | {"psrad", 2, 0x0f72, 4, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, | |
1092 | {"psrad", 2, 0x660f72,4,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, | |
1093 | {"psrlw", 2, 0x0fd1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1094 | {"psrlw", 2, 0x660fd1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1095 | {"psrlw", 2, 0x0f71, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, | |
1096 | {"psrlw", 2, 0x660f71,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, | |
1097 | {"psrld", 2, 0x0fd2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1098 | {"psrld", 2, 0x660fd2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1099 | {"psrld", 2, 0x0f72, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, | |
1100 | {"psrld", 2, 0x660f72,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, | |
1101 | {"psrlq", 2, 0x0fd3, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1102 | {"psrlq", 2, 0x660fd3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1103 | {"psrlq", 2, 0x0f73, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, | |
1104 | {"psrlq", 2, 0x660f73,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, | |
1105 | {"psubb", 2, 0x0ff8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1106 | {"psubb", 2, 0x660ff8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1107 | {"psubw", 2, 0x0ff9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1108 | {"psubw", 2, 0x660ff9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1109 | {"psubd", 2, 0x0ffa, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1110 | {"psubd", 2, 0x660ffa,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1111 | {"psubq", 2, 0x0ffb, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, | |
1112 | {"psubq", 2, 0x660ffb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1113 | {"psubsb", 2, 0x0fe8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1114 | {"psubsb", 2, 0x660fe8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1115 | {"psubsw", 2, 0x0fe9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1116 | {"psubsw", 2, 0x660fe9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1117 | {"psubusb", 2, 0x0fd8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1118 | {"psubusb", 2, 0x660fd8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1119 | {"psubusw", 2, 0x0fd9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1120 | {"psubusw", 2, 0x660fd9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1121 | {"punpckhbw",2, 0x0f68, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1122 | {"punpckhbw",2, 0x660f68,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1123 | {"punpckhwd",2, 0x0f69, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1124 | {"punpckhwd",2, 0x660f69,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1125 | {"punpckhdq",2, 0x0f6a, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1126 | {"punpckhdq",2, 0x660f6a,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1127 | {"punpcklbw",2, 0x0f60, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1128 | {"punpcklbw",2, 0x660f60,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1129 | {"punpcklwd",2, 0x0f61, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1130 | {"punpcklwd",2, 0x660f61,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1131 | {"punpckldq",2, 0x0f62, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1132 | {"punpckldq",2, 0x660f62,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1133 | {"pxor", 2, 0x0fef, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1134 | {"pxor", 2, 0x660fef,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
c608c12e | 1135 | |
d0b47220 | 1136 | /* PIII Katmai New Instructions / SIMD instructions. */ |
c608c12e | 1137 | |
9306ca4a JB |
1138 | {"addps", 2, 0x0f58, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
1139 | {"addss", 2, 0xf30f58, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1140 | {"andnps", 2, 0x0f55, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1141 | {"andps", 2, 0x0f54, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1142 | {"cmpeqps", 2, 0x0fc2, 0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1143 | {"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
1144 | {"cmpleps", 2, 0x0fc2, 2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1145 | {"cmpless", 2, 0xf30fc2, 2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
1146 | {"cmpltps", 2, 0x0fc2, 1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1147 | {"cmpltss", 2, 0xf30fc2, 1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
1148 | {"cmpneqps", 2, 0x0fc2, 4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1149 | {"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
1150 | {"cmpnleps", 2, 0x0fc2, 6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1151 | {"cmpnless", 2, 0xf30fc2, 6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
1152 | {"cmpnltps", 2, 0x0fc2, 5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1153 | {"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
1154 | {"cmpordps", 2, 0x0fc2, 7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1155 | {"cmpordss", 2, 0xf30fc2, 7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
1156 | {"cmpunordps",2, 0x0fc2, 3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1157 | {"cmpunordss",2, 0xf30fc2, 3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, | |
1158 | {"cmpps", 3, 0x0fc2, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, | |
1159 | {"cmpss", 3, 0xf30fc2, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, | |
1160 | {"comiss", 2, 0x0f2f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1161 | {"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, | |
1162 | {"cvtps2pi", 2, 0x0f2d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, | |
76f227a5 JH |
1163 | {"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, |
1164 | {"cvtss2si", 2, 0xf30f2d, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, | |
9306ca4a | 1165 | {"cvttps2pi", 2, 0x0f2c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, |
76f227a5 | 1166 | {"cvttss2si", 2, 0xf30f2c, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } }, |
9306ca4a JB |
1167 | {"divps", 2, 0x0f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
1168 | {"divss", 2, 0xf30f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1169 | {"ldmxcsr", 1, 0x0fae, 2, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } }, | |
c2f0420e | 1170 | {"maskmovq", 2, 0x0ff7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX, RegMMX, 0 } }, |
9306ca4a JB |
1171 | {"maxps", 2, 0x0f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
1172 | {"maxss", 2, 0xf30f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1173 | {"minps", 2, 0x0f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1174 | {"minss", 2, 0xf30f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1175 | {"movaps", 2, 0x0f28, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1176 | {"movaps", 2, 0x0f29, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, | |
c2f0420e | 1177 | {"movhlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM, 0 } }, |
9306ca4a JB |
1178 | {"movhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, |
1179 | {"movhps", 2, 0x0f17, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, | |
c2f0420e | 1180 | {"movlhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM, 0 } }, |
9306ca4a JB |
1181 | {"movlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, |
1182 | {"movlps", 2, 0x0f13, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, | |
c2f0420e | 1183 | {"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64, 0 } }, |
9306ca4a | 1184 | {"movntps", 2, 0x0f2b, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, |
5c6af06e | 1185 | {"movntq", 2, 0x0fe7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX, LLongMem, 0 } }, |
9306ca4a JB |
1186 | {"movntdq", 2, 0x660fe7, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, |
1187 | {"movss", 2, 0xf30f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1188 | {"movss", 2, 0xf30f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, | |
1189 | {"movups", 2, 0x0f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1190 | {"movups", 2, 0x0f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, | |
1191 | {"mulps", 2, 0x0f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1192 | {"mulss", 2, 0xf30f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1193 | {"orps", 2, 0x0f56, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
5c6af06e | 1194 | {"pavgb", 2, 0x0fe0, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, |
9306ca4a | 1195 | {"pavgb", 2, 0x660fe0, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
5c6af06e | 1196 | {"pavgw", 2, 0x0fe3, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, |
9306ca4a | 1197 | {"pavgw", 2, 0x660fe3, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
c2f0420e L |
1198 | {"pextrw", 3, 0x0fc5, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX, Reg32|Reg64 } }, |
1199 | {"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM, Reg32|Reg64 } }, | |
5c6af06e | 1200 | {"pinsrw", 3, 0x0fc4, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } }, |
9306ca4a | 1201 | {"pinsrw", 3, 0x660fc4, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } }, |
5c6af06e | 1202 | {"pmaxsw", 2, 0x0fee, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, |
9306ca4a | 1203 | {"pmaxsw", 2, 0x660fee, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
5c6af06e | 1204 | {"pmaxub", 2, 0x0fde, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, |
9306ca4a | 1205 | {"pmaxub", 2, 0x660fde, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
5c6af06e | 1206 | {"pminsw", 2, 0x0fea, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, |
9306ca4a | 1207 | {"pminsw", 2, 0x660fea, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
5c6af06e | 1208 | {"pminub", 2, 0x0fda, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, |
9306ca4a | 1209 | {"pminub", 2, 0x660fda, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
c2f0420e L |
1210 | {"pmovmskb", 2, 0x0fd7, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64, 0 } }, |
1211 | {"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64, 0 } }, | |
5c6af06e | 1212 | {"pmulhuw", 2, 0x0fe4, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, |
9306ca4a | 1213 | {"pmulhuw", 2, 0x660fe4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
5c6af06e JB |
1214 | {"prefetchnta", 1, 0x0f18, 0, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, |
1215 | {"prefetcht0", 1, 0x0f18, 1, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, | |
1216 | {"prefetcht1", 1, 0x0f18, 2, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, | |
1217 | {"prefetcht2", 1, 0x0f18, 3, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, | |
1218 | {"psadbw", 2, 0x0ff6, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, | |
9306ca4a | 1219 | {"psadbw", 2, 0x660ff6, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
5c6af06e | 1220 | {"pshufw", 3, 0x0f70, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, |
9306ca4a JB |
1221 | {"rcpps", 2, 0x0f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
1222 | {"rcpss", 2, 0xf30f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1223 | {"rsqrtps", 2, 0x0f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1224 | {"rsqrtss", 2, 0xf30f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
5c6af06e | 1225 | {"sfence", 0, 0x0fae, 0xf8, CpuMMX2,NoSuf|IgnoreSize|ImmExt, { 0, 0, 0 } }, |
9306ca4a JB |
1226 | {"shufps", 3, 0x0fc6, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, |
1227 | {"sqrtps", 2, 0x0f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1228 | {"sqrtss", 2, 0xf30f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1229 | {"stmxcsr", 1, 0x0fae, 3, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } }, | |
1230 | {"subps", 2, 0x0f5c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1231 | {"subss", 2, 0xf30f5c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1232 | {"ucomiss", 2, 0x0f2e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1233 | {"unpckhps", 2, 0x0f15, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1234 | {"unpcklps", 2, 0x0f14, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1235 | {"xorps", 2, 0x0f57, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
c608c12e | 1236 | |
6f8c0c4c JH |
1237 | /* SSE-2 instructions. */ |
1238 | ||
9306ca4a JB |
1239 | {"addpd", 2, 0x660f58, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
1240 | {"addsd", 2, 0xf20f58, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, | |
1241 | {"andnpd", 2, 0x660f55, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1242 | {"andpd", 2, 0x660f54, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, | |
1243 | {"cmpeqpd", 2, 0x660fc2, 0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, | |
1244 | {"cmpeqsd", 2, 0xf20fc2, 0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, | |
1245 | {"cmplepd", 2, 0x660fc2, 2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, | |
1246 | {"cmplesd", 2, 0xf20fc2, 2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, | |
1247 | {"cmpltpd", 2, 0x660fc2, 1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, | |
1248 | {"cmpltsd", 2, 0xf20fc2, 1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, | |
1249 | {"cmpneqpd", 2, 0x660fc2, 4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, | |
1250 | {"cmpneqsd", 2, 0xf20fc2, 4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, | |
1251 | {"cmpnlepd", 2, 0x660fc2, 6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, | |
1252 | {"cmpnlesd", 2, 0xf20fc2, 6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, | |
1253 | {"cmpnltpd", 2, 0x660fc2, 5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, | |
1254 | {"cmpnltsd", 2, 0xf20fc2, 5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, | |
1255 | {"cmpordpd", 2, 0x660fc2, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, | |
1256 | {"cmpordsd", 2, 0xf20fc2, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, | |
1257 | {"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, | |
1258 | {"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, | |
1259 | {"cmppd", 3, 0x660fc2, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, | |
cd47f4f1 AM |
1260 | /* Intel mode string compare. */ |
1261 | {"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, | |
1262 | {"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, | |
9306ca4a JB |
1263 | {"cmpsd", 3, 0xf20fc2, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LongMem, RegXMM } }, |
1264 | {"comisd", 2, 0x660f2f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, | |
1265 | {"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, | |
76f227a5 | 1266 | {"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, |
9306ca4a JB |
1267 | {"divpd", 2, 0x660f5e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
1268 | {"divsd", 2, 0xf20f5e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, | |
1269 | {"maxpd", 2, 0x660f5f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1270 | {"maxsd", 2, 0xf20f5f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, | |
1271 | {"minpd", 2, 0x660f5d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1272 | {"minsd", 2, 0xf20f5d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, | |
1273 | {"movapd", 2, 0x660f28, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1274 | {"movapd", 2, 0x660f29, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, | |
1275 | {"movhpd", 2, 0x660f16, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, | |
1276 | {"movhpd", 2, 0x660f17, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, | |
1277 | {"movlpd", 2, 0x660f12, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, | |
1278 | {"movlpd", 2, 0x660f13, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, | |
c2f0420e | 1279 | {"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64, 0 } }, |
9306ca4a | 1280 | {"movntpd", 2, 0x660f2b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, |
cd47f4f1 AM |
1281 | /* Intel mode string move. */ |
1282 | {"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, | |
1283 | {"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, | |
9306ca4a JB |
1284 | {"movsd", 2, 0xf20f10, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, |
1285 | {"movsd", 2, 0xf20f11, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LongMem, 0 } }, | |
1286 | {"movupd", 2, 0x660f10, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1287 | {"movupd", 2, 0x660f11, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, | |
1288 | {"mulpd", 2, 0x660f59, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1289 | {"mulsd", 2, 0xf20f59, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, | |
1290 | {"orpd", 2, 0x660f56, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1291 | {"shufpd", 3, 0x660fc6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, | |
1292 | {"sqrtpd", 2, 0x660f51, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1293 | {"sqrtsd", 2, 0xf20f51, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, | |
1294 | {"subpd", 2, 0x660f5c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1295 | {"subsd", 2, 0xf20f5c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, | |
1296 | {"ucomisd", 2, 0x660f2e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, | |
1297 | {"unpckhpd", 2, 0x660f15, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1298 | {"unpcklpd", 2, 0x660f14, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1299 | {"xorpd", 2, 0x660f57, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1300 | {"cvtdq2pd", 2, 0xf30fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1301 | {"cvtpd2dq", 2, 0xf20fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1302 | {"cvtdq2ps", 2, 0x0f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1303 | {"cvtpd2pi", 2, 0x660f2d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, | |
1304 | {"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1305 | {"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1306 | {"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
76f227a5 | 1307 | {"cvtsd2si", 2, 0xf20f2d, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } }, |
9306ca4a JB |
1308 | {"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
1309 | {"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1310 | {"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, | |
76f227a5 | 1311 | {"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, |
9306ca4a JB |
1312 | {"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
1313 | {"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
c2f0420e | 1314 | {"maskmovdqu",2, 0x660ff7, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM, 0 } }, |
9306ca4a JB |
1315 | {"movdqa", 2, 0x660f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, |
1316 | {"movdqa", 2, 0x660f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, | |
1317 | {"movdqu", 2, 0xf30f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1318 | {"movdqu", 2, 0xf30f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, | |
c2f0420e L |
1319 | {"movdq2q", 2, 0xf20fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegMMX, 0 } }, |
1320 | {"movq2dq", 2, 0xf30fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX, RegXMM, 0 } }, | |
9306ca4a JB |
1321 | {"pmuludq", 2, 0x0ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, |
1322 | {"pmuludq", 2, 0x660ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, | |
1323 | {"pshufd", 3, 0x660f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, | |
1324 | {"pshufhw", 3, 0xf30f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, | |
1325 | {"pshuflw", 3, 0xf20f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, | |
1326 | {"pslldq", 2, 0x660f73, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, | |
1327 | {"psrldq", 2, 0x660f73, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, | |
1328 | {"punpckhqdq",2, 0x660f6d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1329 | {"punpcklqdq",2, 0x660f6c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
6f8c0c4c | 1330 | |
b7d9ef37 L |
1331 | /* SSE-3 instructions. */ |
1332 | ||
1333 | {"addsubpd", 2, 0x660fd0, X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1334 | {"addsubps", 2, 0xf20fd0, X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1335 | {"cmpxchg16b",1, 0x0fc7, 1, CpuSSE3|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} }, | |
1336 | {"fisttp", 1, 0xdf, 1, CpuSSE3, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, | |
1337 | {"fisttp", 1, 0xdd, 1, CpuSSE3, q_FP|Modrm, { LLongMem, 0, 0} }, | |
1338 | {"fisttpll", 1, 0xdd, 1, CpuSSE3, FP|Modrm, { LLongMem, 0, 0} }, | |
1339 | {"haddpd", 2, 0x660f7c, X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1340 | {"haddps", 2, 0xf20f7c, X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1341 | {"hsubpd", 2, 0x660f7d, X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1342 | {"hsubps", 2, 0xf20f7d, X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1343 | {"lddqu", 2, 0xf20ff0, X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, | |
1344 | {"monitor", 0, 0x0f01, 0xc8, CpuSSE3, NoSuf|ImmExt, { 0, 0, 0} }, | |
cb712a9e L |
1345 | /* monitor is very special. CX and DX are always 64bits with zero upper |
1346 | 32bits in 64bit mode, and 32bits in 16bit and 32bit modes. The | |
1347 | address size override prefix can be used to overrride the AX size in | |
1348 | all modes. */ | |
1349 | /* Need to ensure only "monitor %eax/%ax,%ecx,%edx" is accepted. */ | |
b7d9ef37 | 1350 | {"monitor", 3, 0x0f01, 0xc8, CpuSSE3|CpuNo64, NoSuf|ImmExt, { Reg16|Reg32, Reg32, Reg32 } }, |
cb712a9e | 1351 | /* Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted. */ |
b7d9ef37 L |
1352 | {"monitor", 3, 0x0f01, 0xc8, CpuSSE3|Cpu64, NoSuf|ImmExt|NoRex64, { Reg32|Reg64, Reg64, Reg64 } }, |
1353 | {"movddup", 2, 0xf20f12, X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1354 | {"movshdup", 2, 0xf30f16, X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1355 | {"movsldup", 2, 0xf30f12, X, CpuSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1356 | {"mwait", 0, 0x0f01, 0xc9, CpuSSE3, NoSuf|ImmExt, { 0, 0, 0} }, | |
cb712a9e L |
1357 | /* mwait is very special. AX and CX are always 64bits with zero upper |
1358 | 32bits in 64bit mode, and 32bits in 16bit and 32bit modes. */ | |
ca164297 | 1359 | /* Need to ensure only "mwait %eax,%ecx" is accepted. */ |
b7d9ef37 | 1360 | {"mwait", 2, 0x0f01, 0xc9, CpuSSE3|CpuNo64, NoSuf|ImmExt, { Reg32, Reg32, 0} }, |
cb712a9e | 1361 | /* Need to ensure only "mwait %rax,%rcx" is accepted. */ |
b7d9ef37 | 1362 | {"mwait", 2, 0x0f01, 0xc9, CpuSSE3|Cpu64, NoSuf|ImmExt|NoRex64, { Reg64, Reg64, 0} }, |
ca164297 | 1363 | |
90700ea2 L |
1364 | /* VMX instructions. */ |
1365 | {"vmcall", 0, 0x0f01, 0xc1, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, | |
1366 | {"vmclear", 1, 0x660fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, | |
1367 | {"vmlaunch", 0, 0x0f01, 0xc2, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, | |
1368 | {"vmresume", 0, 0x0f01, 0xc3, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, | |
1369 | {"vmptrld", 1, 0x0fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, | |
1370 | {"vmptrst", 1, 0x0fc7, 7, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, | |
1371 | {"vmread", 2, 0x0f78, X, CpuVMX|CpuNo64, l_Suf|Modrm,{ Reg32, Reg32|LongMem, 0} }, | |
1372 | {"vmread", 2, 0x0f78, X, CpuVMX|Cpu64, q_Suf|Modrm|NoRex64,{ Reg64, Reg64|LLongMem, 0} }, | |
1373 | {"vmwrite", 2, 0x0f79, X, CpuVMX|CpuNo64, l_Suf|Modrm,{ Reg32|LongMem, Reg32, 0} }, | |
1374 | {"vmwrite", 2, 0x0f79, X, CpuVMX|Cpu64, q_Suf|Modrm|NoRex64,{ Reg64|LLongMem, Reg64, 0} }, | |
1375 | {"vmxoff", 0, 0x0f01, 0xc4, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, | |
1376 | {"vmxon", 1, 0xf30fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, | |
1377 | ||
ef05d495 L |
1378 | /* Supplemental Streaming SIMD extensions 3 Instructions. */ |
1379 | ||
1380 | {"phaddw", 2, 0x0f3801,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1381 | {"phaddw", 2, 0x660f3801,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1382 | {"phaddd", 2, 0x0f3802,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1383 | {"phaddd", 2, 0x660f3802,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1384 | {"phaddsw", 2, 0x0f3803,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1385 | {"phaddsw", 2, 0x660f3803,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1386 | {"phsubw", 2, 0x0f3805,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1387 | {"phsubw", 2, 0x660f3805,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1388 | {"phsubd", 2, 0x0f3806,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1389 | {"phsubd", 2, 0x660f3806,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1390 | {"phsubsw", 2, 0x0f3807,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1391 | {"phsubsw", 2, 0x660f3807,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1392 | {"pmaddubsw", 2, 0x0f3804,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1393 | {"pmaddubsw", 2, 0x660f3804,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1394 | {"pmulhrsw", 2, 0x0f380b,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1395 | {"pmulhrsw", 2, 0x660f380b,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1396 | {"pshufb", 2, 0x0f3800,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1397 | {"pshufb", 2, 0x660f3800,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1398 | {"psignb", 2, 0x0f3808,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1399 | {"psignb", 2, 0x660f3808,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1400 | {"psignw", 2, 0x0f3809,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1401 | {"psignw", 2, 0x660f3809,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1402 | {"psignd", 2, 0x0f380a,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1403 | {"psignd", 2, 0x660f380a,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1404 | {"palignr", 3, 0x0f3a0f,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LongMem, RegMMX } }, | |
1405 | {"palignr", 3, 0x660f3a0f,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, | |
1406 | {"pabsb", 2, 0x0f381c,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1407 | {"pabsb", 2, 0x660f381c,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1408 | {"pabsw", 2, 0x0f381d,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1409 | {"pabsw", 2, 0x660f381d,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
1410 | {"pabsd", 2, 0x0f381e,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, | |
1411 | {"pabsd", 2, 0x660f381e,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, | |
331d2d0d | 1412 | |
d0b47220 | 1413 | /* AMD 3DNow! instructions. */ |
c608c12e | 1414 | |
9306ca4a JB |
1415 | {"prefetch", 1, 0x0f0d, 0, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } }, |
1416 | {"prefetchw",1, 0x0f0d, 1, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } }, | |
1417 | {"femms", 0, 0x0f0e, X, Cpu3dnow, NoSuf, { 0, 0, 0 } }, | |
1418 | {"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1419 | {"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
5c6af06e | 1420 | {"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, |
9306ca4a JB |
1421 | {"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, |
1422 | {"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1423 | {"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1424 | {"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1425 | {"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1426 | {"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1427 | {"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1428 | {"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
5c6af06e JB |
1429 | {"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, |
1430 | {"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
9306ca4a JB |
1431 | {"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, |
1432 | {"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1433 | {"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1434 | {"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1435 | {"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1436 | {"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1437 | {"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
1438 | {"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, | |
5c6af06e | 1439 | {"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, |
9306ca4a | 1440 | {"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, |
5c6af06e | 1441 | {"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, |
e413e4e9 | 1442 | |
c0d8940f | 1443 | /* AMD extensions. */ |
296bc568 AM |
1444 | {"syscall", 0, 0x0f05, X, CpuK6, NoSuf, { 0, 0, 0} }, |
1445 | {"sysret", 0, 0x0f07, X, CpuK6, lq_Suf|DefaultSize, { 0, 0, 0} }, | |
1446 | {"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} }, | |
373ff435 | 1447 | {"rdtscp", 0, 0x0f01, 0xf9, CpuSledgehammer,NoSuf|ImmExt, { 0, 0, 0} }, |
c0d8940f | 1448 | |
30123838 JB |
1449 | /* AMD Pacifica additions. */ |
1450 | {"clgi", 0, 0x0f01, 0xdd, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, | |
1451 | {"invlpga", 0, 0x0f01, 0xdf, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, | |
1452 | /* Need to ensure only "invlpga ...,%ecx" is accepted. */ | |
1453 | {"invlpga", 2, 0x0f01, 0xdf, CpuSVME, NoSuf|ImmExt, { AnyMem, Reg32, 0 } }, | |
1454 | {"skinit", 0, 0x0f01, 0xde, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, | |
1455 | {"skinit", 1, 0x0f01, 0xde, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, | |
1456 | {"stgi", 0, 0x0f01, 0xdc, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, | |
1457 | {"vmload", 0, 0x0f01, 0xda, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, | |
1458 | {"vmload", 1, 0x0f01, 0xda, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, | |
1459 | {"vmmcall", 0, 0x0f01, 0xd9, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, | |
1460 | {"vmrun", 0, 0x0f01, 0xd8, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, | |
1461 | {"vmrun", 1, 0x0f01, 0xd8, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, | |
1462 | {"vmsave", 0, 0x0f01, 0xdb, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, | |
1463 | {"vmsave", 1, 0x0f01, 0xdb, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, | |
1464 | ||
050dfa73 MM |
1465 | |
1466 | /* SSE4a instructions */ | |
1467 | {"movntsd", 2, 0xf20f2b, X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { RegXMM, LongMem, 0 } }, | |
1468 | {"movntss", 2, 0xf30f2b, X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { RegXMM, WordMem, 0 } }, | |
1469 | {"extrq", 3, 0x660f78, 0, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { Imm8, Imm8, RegXMM } }, | |
1470 | {"extrq", 2, 0x660f79, X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM} }, | |
1471 | {"insertq", 2, 0xf20f79, X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM} }, | |
1472 | {"insertq", 4, 0xf20f78, X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { Imm8, Imm8, RegXMM, RegXMM} }, | |
1473 | ||
1474 | /* ABM instructions */ | |
7918206c | 1475 | {"popcnt", 2, 0xf30fb8, X, CpuABM, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, |
050dfa73 MM |
1476 | {"lzcnt", 2, 0xf30fbd, X, CpuABM, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, |
1477 | ||
1478 | ||
543613e9 | 1479 | /* VIA PadLock extensions. */ |
791fe849 MK |
1480 | {"xstore-rng",0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, |
1481 | {"xcrypt-ecb",0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, | |
1482 | {"xcrypt-cbc",0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, | |
1483 | {"xcrypt-ctr",0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, | |
1484 | {"xcrypt-cfb",0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, | |
1485 | {"xcrypt-ofb",0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, | |
1486 | {"montmul", 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, | |
1487 | {"xsha1", 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, | |
1488 | {"xsha256", 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, | |
1489 | /* Aliases without hyphens. */ | |
bc4bd9ab MK |
1490 | {"xstorerng", 0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, |
1491 | {"xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, | |
1492 | {"xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, | |
791fe849 | 1493 | {"xcryptctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, |
bc4bd9ab MK |
1494 | {"xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, |
1495 | {"xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, | |
791fe849 | 1496 | /* Alias for xstore-rng. */ |
bc4bd9ab | 1497 | {"xstore", 0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, |
0f10071e | 1498 | |
e413e4e9 AM |
1499 | /* sentinel */ |
1500 | {NULL, 0, 0, 0, 0, 0, { 0, 0, 0} } | |
252b5132 RH |
1501 | }; |
1502 | #undef X | |
252b5132 RH |
1503 | #undef NoSuf |
1504 | #undef b_Suf | |
1505 | #undef w_Suf | |
1506 | #undef l_Suf | |
c0d8940f | 1507 | #undef q_Suf |
eecb386c | 1508 | #undef x_Suf |
252b5132 RH |
1509 | #undef bw_Suf |
1510 | #undef bl_Suf | |
1511 | #undef wl_Suf | |
c0d8940f | 1512 | #undef wlq_Suf |
252b5132 RH |
1513 | #undef sl_Suf |
1514 | #undef bwl_Suf | |
c0d8940f | 1515 | #undef bwlq_Suf |
252b5132 RH |
1516 | #undef FP |
1517 | #undef l_FP | |
9306ca4a | 1518 | #undef q_FP |
eecb386c | 1519 | #undef x_FP |
252b5132 RH |
1520 | #undef sl_FP |
1521 | ||
543613e9 | 1522 | #define MAX_MNEM_SIZE 16 /* For parsing insn mnemonics from input. */ |
252b5132 | 1523 | |
d0b47220 | 1524 | /* 386 register table. */ |
252b5132 | 1525 | |
543613e9 NC |
1526 | static const reg_entry i386_regtab[] = |
1527 | { | |
1528 | /* Make %st first as we test for it. */ | |
3e73aa7c | 1529 | {"st", FloatReg|FloatAcc, 0, 0}, |
252b5132 | 1530 | /* 8 bit regs */ |
2e98d2de | 1531 | #define REGNAM_AL 1 /* Entry in i386_regtab. */ |
3e73aa7c JH |
1532 | {"al", Reg8|Acc, 0, 0}, |
1533 | {"cl", Reg8|ShiftCount, 0, 1}, | |
1534 | {"dl", Reg8, 0, 2}, | |
1535 | {"bl", Reg8, 0, 3}, | |
1536 | {"ah", Reg8, 0, 4}, | |
1537 | {"ch", Reg8, 0, 5}, | |
1538 | {"dh", Reg8, 0, 6}, | |
1539 | {"bh", Reg8, 0, 7}, | |
c0d8940f JH |
1540 | {"axl", Reg8|Acc, RegRex64, 0}, /* Must be in the "al + 8" slot. */ |
1541 | {"cxl", Reg8, RegRex64, 1}, | |
1542 | {"dxl", Reg8, RegRex64, 2}, | |
1543 | {"bxl", Reg8, RegRex64, 3}, | |
1544 | {"spl", Reg8, RegRex64, 4}, | |
1545 | {"bpl", Reg8, RegRex64, 5}, | |
1546 | {"sil", Reg8, RegRex64, 6}, | |
1547 | {"dil", Reg8, RegRex64, 7}, | |
1548 | {"r8b", Reg8, RegRex64|RegRex, 0}, | |
1549 | {"r9b", Reg8, RegRex64|RegRex, 1}, | |
1550 | {"r10b", Reg8, RegRex64|RegRex, 2}, | |
1551 | {"r11b", Reg8, RegRex64|RegRex, 3}, | |
1552 | {"r12b", Reg8, RegRex64|RegRex, 4}, | |
1553 | {"r13b", Reg8, RegRex64|RegRex, 5}, | |
1554 | {"r14b", Reg8, RegRex64|RegRex, 6}, | |
1555 | {"r15b", Reg8, RegRex64|RegRex, 7}, | |
252b5132 | 1556 | /* 16 bit regs */ |
2e98d2de | 1557 | #define REGNAM_AX 25 |
3e73aa7c JH |
1558 | {"ax", Reg16|Acc, 0, 0}, |
1559 | {"cx", Reg16, 0, 1}, | |
1560 | {"dx", Reg16|InOutPortReg, 0, 2}, | |
1561 | {"bx", Reg16|BaseIndex, 0, 3}, | |
1562 | {"sp", Reg16, 0, 4}, | |
1563 | {"bp", Reg16|BaseIndex, 0, 5}, | |
1564 | {"si", Reg16|BaseIndex, 0, 6}, | |
1565 | {"di", Reg16|BaseIndex, 0, 7}, | |
c0d8940f JH |
1566 | {"r8w", Reg16, RegRex, 0}, |
1567 | {"r9w", Reg16, RegRex, 1}, | |
1568 | {"r10w", Reg16, RegRex, 2}, | |
1569 | {"r11w", Reg16, RegRex, 3}, | |
1570 | {"r12w", Reg16, RegRex, 4}, | |
1571 | {"r13w", Reg16, RegRex, 5}, | |
1572 | {"r14w", Reg16, RegRex, 6}, | |
1573 | {"r15w", Reg16, RegRex, 7}, | |
252b5132 | 1574 | /* 32 bit regs */ |
2e98d2de | 1575 | #define REGNAM_EAX 41 |
543613e9 | 1576 | {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot. */ |
3e73aa7c JH |
1577 | {"ecx", Reg32|BaseIndex, 0, 1}, |
1578 | {"edx", Reg32|BaseIndex, 0, 2}, | |
1579 | {"ebx", Reg32|BaseIndex, 0, 3}, | |
1580 | {"esp", Reg32, 0, 4}, | |
1581 | {"ebp", Reg32|BaseIndex, 0, 5}, | |
1582 | {"esi", Reg32|BaseIndex, 0, 6}, | |
1583 | {"edi", Reg32|BaseIndex, 0, 7}, | |
c0d8940f JH |
1584 | {"r8d", Reg32|BaseIndex, RegRex, 0}, |
1585 | {"r9d", Reg32|BaseIndex, RegRex, 1}, | |
1586 | {"r10d", Reg32|BaseIndex, RegRex, 2}, | |
1587 | {"r11d", Reg32|BaseIndex, RegRex, 3}, | |
1588 | {"r12d", Reg32|BaseIndex, RegRex, 4}, | |
1589 | {"r13d", Reg32|BaseIndex, RegRex, 5}, | |
1590 | {"r14d", Reg32|BaseIndex, RegRex, 6}, | |
1591 | {"r15d", Reg32|BaseIndex, RegRex, 7}, | |
1592 | {"rax", Reg64|BaseIndex|Acc, 0, 0}, | |
1593 | {"rcx", Reg64|BaseIndex, 0, 1}, | |
1594 | {"rdx", Reg64|BaseIndex, 0, 2}, | |
1595 | {"rbx", Reg64|BaseIndex, 0, 3}, | |
1596 | {"rsp", Reg64, 0, 4}, | |
1597 | {"rbp", Reg64|BaseIndex, 0, 5}, | |
1598 | {"rsi", Reg64|BaseIndex, 0, 6}, | |
1599 | {"rdi", Reg64|BaseIndex, 0, 7}, | |
1600 | {"r8", Reg64|BaseIndex, RegRex, 0}, | |
1601 | {"r9", Reg64|BaseIndex, RegRex, 1}, | |
1602 | {"r10", Reg64|BaseIndex, RegRex, 2}, | |
1603 | {"r11", Reg64|BaseIndex, RegRex, 3}, | |
1604 | {"r12", Reg64|BaseIndex, RegRex, 4}, | |
1605 | {"r13", Reg64|BaseIndex, RegRex, 5}, | |
1606 | {"r14", Reg64|BaseIndex, RegRex, 6}, | |
1607 | {"r15", Reg64|BaseIndex, RegRex, 7}, | |
543613e9 | 1608 | /* Segment registers. */ |
3e73aa7c JH |
1609 | {"es", SReg2, 0, 0}, |
1610 | {"cs", SReg2, 0, 1}, | |
1611 | {"ss", SReg2, 0, 2}, | |
1612 | {"ds", SReg2, 0, 3}, | |
1613 | {"fs", SReg3, 0, 4}, | |
1614 | {"gs", SReg3, 0, 5}, | |
543613e9 | 1615 | /* Control registers. */ |
3e73aa7c JH |
1616 | {"cr0", Control, 0, 0}, |
1617 | {"cr1", Control, 0, 1}, | |
1618 | {"cr2", Control, 0, 2}, | |
1619 | {"cr3", Control, 0, 3}, | |
1620 | {"cr4", Control, 0, 4}, | |
1621 | {"cr5", Control, 0, 5}, | |
1622 | {"cr6", Control, 0, 6}, | |
1623 | {"cr7", Control, 0, 7}, | |
c0d8940f JH |
1624 | {"cr8", Control, RegRex, 0}, |
1625 | {"cr9", Control, RegRex, 1}, | |
1626 | {"cr10", Control, RegRex, 2}, | |
1627 | {"cr11", Control, RegRex, 3}, | |
1628 | {"cr12", Control, RegRex, 4}, | |
1629 | {"cr13", Control, RegRex, 5}, | |
1630 | {"cr14", Control, RegRex, 6}, | |
1631 | {"cr15", Control, RegRex, 7}, | |
543613e9 | 1632 | /* Debug registers. */ |
3e73aa7c JH |
1633 | {"db0", Debug, 0, 0}, |
1634 | {"db1", Debug, 0, 1}, | |
1635 | {"db2", Debug, 0, 2}, | |
1636 | {"db3", Debug, 0, 3}, | |
1637 | {"db4", Debug, 0, 4}, | |
1638 | {"db5", Debug, 0, 5}, | |
1639 | {"db6", Debug, 0, 6}, | |
1640 | {"db7", Debug, 0, 7}, | |
c0d8940f JH |
1641 | {"db8", Debug, RegRex, 0}, |
1642 | {"db9", Debug, RegRex, 1}, | |
1643 | {"db10", Debug, RegRex, 2}, | |
1644 | {"db11", Debug, RegRex, 3}, | |
1645 | {"db12", Debug, RegRex, 4}, | |
1646 | {"db13", Debug, RegRex, 5}, | |
1647 | {"db14", Debug, RegRex, 6}, | |
1648 | {"db15", Debug, RegRex, 7}, | |
3e73aa7c JH |
1649 | {"dr0", Debug, 0, 0}, |
1650 | {"dr1", Debug, 0, 1}, | |
1651 | {"dr2", Debug, 0, 2}, | |
1652 | {"dr3", Debug, 0, 3}, | |
1653 | {"dr4", Debug, 0, 4}, | |
1654 | {"dr5", Debug, 0, 5}, | |
1655 | {"dr6", Debug, 0, 6}, | |
1656 | {"dr7", Debug, 0, 7}, | |
c0d8940f JH |
1657 | {"dr8", Debug, RegRex, 0}, |
1658 | {"dr9", Debug, RegRex, 1}, | |
1659 | {"dr10", Debug, RegRex, 2}, | |
1660 | {"dr11", Debug, RegRex, 3}, | |
1661 | {"dr12", Debug, RegRex, 4}, | |
1662 | {"dr13", Debug, RegRex, 5}, | |
1663 | {"dr14", Debug, RegRex, 6}, | |
1664 | {"dr15", Debug, RegRex, 7}, | |
543613e9 | 1665 | /* Test registers. */ |
3e73aa7c JH |
1666 | {"tr0", Test, 0, 0}, |
1667 | {"tr1", Test, 0, 1}, | |
1668 | {"tr2", Test, 0, 2}, | |
1669 | {"tr3", Test, 0, 3}, | |
1670 | {"tr4", Test, 0, 4}, | |
1671 | {"tr5", Test, 0, 5}, | |
1672 | {"tr6", Test, 0, 6}, | |
1673 | {"tr7", Test, 0, 7}, | |
543613e9 | 1674 | /* MMX and simd registers. */ |
3e73aa7c JH |
1675 | {"mm0", RegMMX, 0, 0}, |
1676 | {"mm1", RegMMX, 0, 1}, | |
1677 | {"mm2", RegMMX, 0, 2}, | |
1678 | {"mm3", RegMMX, 0, 3}, | |
1679 | {"mm4", RegMMX, 0, 4}, | |
1680 | {"mm5", RegMMX, 0, 5}, | |
1681 | {"mm6", RegMMX, 0, 6}, | |
1682 | {"mm7", RegMMX, 0, 7}, | |
1683 | {"xmm0", RegXMM, 0, 0}, | |
1684 | {"xmm1", RegXMM, 0, 1}, | |
1685 | {"xmm2", RegXMM, 0, 2}, | |
1686 | {"xmm3", RegXMM, 0, 3}, | |
1687 | {"xmm4", RegXMM, 0, 4}, | |
1688 | {"xmm5", RegXMM, 0, 5}, | |
1689 | {"xmm6", RegXMM, 0, 6}, | |
c0d8940f JH |
1690 | {"xmm7", RegXMM, 0, 7}, |
1691 | {"xmm8", RegXMM, RegRex, 0}, | |
1692 | {"xmm9", RegXMM, RegRex, 1}, | |
1693 | {"xmm10", RegXMM, RegRex, 2}, | |
1694 | {"xmm11", RegXMM, RegRex, 3}, | |
1695 | {"xmm12", RegXMM, RegRex, 4}, | |
1696 | {"xmm13", RegXMM, RegRex, 5}, | |
1697 | {"xmm14", RegXMM, RegRex, 6}, | |
1698 | {"xmm15", RegXMM, RegRex, 7}, | |
543613e9 | 1699 | /* No type will make this register rejected for all purposes except |
c0d8940f JH |
1700 | for addressing. This saves creating one extra type for RIP. */ |
1701 | {"rip", BaseIndex, 0, 0} | |
252b5132 RH |
1702 | }; |
1703 | ||
543613e9 NC |
1704 | static const reg_entry i386_float_regtab[] = |
1705 | { | |
3e73aa7c JH |
1706 | {"st(0)", FloatReg|FloatAcc, 0, 0}, |
1707 | {"st(1)", FloatReg, 0, 1}, | |
1708 | {"st(2)", FloatReg, 0, 2}, | |
1709 | {"st(3)", FloatReg, 0, 3}, | |
1710 | {"st(4)", FloatReg, 0, 4}, | |
1711 | {"st(5)", FloatReg, 0, 5}, | |
1712 | {"st(6)", FloatReg, 0, 6}, | |
1713 | {"st(7)", FloatReg, 0, 7} | |
5f47d35b AM |
1714 | }; |
1715 | ||
543613e9 | 1716 | #define MAX_REG_NAME_SIZE 8 /* For parsing register names from input. */ |
252b5132 | 1717 | |
543613e9 | 1718 | /* Segment stuff. */ |
252b5132 RH |
1719 | static const seg_entry cs = { "cs", 0x2e }; |
1720 | static const seg_entry ds = { "ds", 0x3e }; | |
1721 | static const seg_entry ss = { "ss", 0x36 }; | |
1722 | static const seg_entry es = { "es", 0x26 }; | |
1723 | static const seg_entry fs = { "fs", 0x64 }; | |
1724 | static const seg_entry gs = { "gs", 0x65 }; | |
1725 |