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05166a28 | 1 | /* mips.h. Mips opcode list for GDB, the GNU debugger. |
b410ea2b | 2 | Copyright 1993, 94, 95, 96, 1997 Free Software Foundation, Inc. |
05166a28 ILT |
3 | Contributed by Ralph Campbell and OSF |
4 | Commented and modified by Ian Lance Taylor, Cygnus Support | |
5 | ||
6 | This file is part of GDB, GAS, and the GNU binutils. | |
7 | ||
8 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
9 | them and/or modify them under the terms of the GNU General Public | |
10 | License as published by the Free Software Foundation; either version | |
11 | 1, or (at your option) any later version. | |
12 | ||
13 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
14 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
15 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
16 | the GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this file; see the file COPYING. If not, write to the Free | |
b5eab453 | 20 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
05166a28 | 21 | |
2fedd0a1 DP |
22 | #ifndef _MIPS_H_ |
23 | #define _MIPS_H_ | |
24 | ||
05166a28 ILT |
25 | /* These are bit masks and shift counts to use to access the various |
26 | fields of an instruction. To retrieve the X field of an | |
27 | instruction, use the expression | |
28 | (i >> OP_SH_X) & OP_MASK_X | |
29 | To set the same field (to j), use | |
30 | i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) | |
31 | ||
32 | Make sure you use fields that are appropriate for the instruction, | |
33 | of course. | |
34 | ||
35 | The 'i' format uses OP, RS, RT and IMMEDIATE. | |
36 | ||
37 | The 'j' format uses OP and TARGET. | |
38 | ||
39 | The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. | |
40 | ||
41 | The 'b' format uses OP, RS, RT and DELTA. | |
42 | ||
43 | The floating point 'i' format uses OP, RS, RT and IMMEDIATE. | |
44 | ||
45 | The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. | |
46 | ||
47 | A breakpoint instruction uses OP, CODE and SPEC (10 bits of the | |
48 | breakpoint instruction are not defined; Kane says the breakpoint | |
49 | code field in BREAK is 20 bits; yet MIPS assemblers and debuggers | |
d3b42ce1 GRK |
50 | only use ten bits). An optional two-operand form of break/sdbbp |
51 | allows the lower ten bits to be set too. | |
05166a28 ILT |
52 | |
53 | The syscall instruction uses SYSCALL. | |
54 | ||
55 | The general coprocessor instructions use COPZ. */ | |
56 | ||
57 | #define OP_MASK_OP 0x3f | |
58 | #define OP_SH_OP 26 | |
59 | #define OP_MASK_RS 0x1f | |
60 | #define OP_SH_RS 21 | |
b5eab453 KR |
61 | #define OP_MASK_FR 0x1f |
62 | #define OP_SH_FR 21 | |
05166a28 ILT |
63 | #define OP_MASK_FMT 0x1f |
64 | #define OP_SH_FMT 21 | |
b5eab453 KR |
65 | #define OP_MASK_BCC 0x7 |
66 | #define OP_SH_BCC 18 | |
05166a28 ILT |
67 | #define OP_MASK_CODE 0x3ff |
68 | #define OP_SH_CODE 16 | |
d3b42ce1 GRK |
69 | #define OP_MASK_CODE2 0x3ff |
70 | #define OP_SH_CODE2 6 | |
05166a28 ILT |
71 | #define OP_MASK_RT 0x1f |
72 | #define OP_SH_RT 16 | |
73 | #define OP_MASK_FT 0x1f | |
74 | #define OP_SH_FT 16 | |
57ec4ed5 ILT |
75 | #define OP_MASK_CACHE 0x1f |
76 | #define OP_SH_CACHE 16 | |
05166a28 ILT |
77 | #define OP_MASK_RD 0x1f |
78 | #define OP_SH_RD 11 | |
79 | #define OP_MASK_FS 0x1f | |
80 | #define OP_SH_FS 11 | |
b5eab453 KR |
81 | #define OP_MASK_PREFX 0x1f |
82 | #define OP_SH_PREFX 11 | |
83 | #define OP_MASK_CCC 0x7 | |
84 | #define OP_SH_CCC 8 | |
05166a28 ILT |
85 | #define OP_MASK_SYSCALL 0xfffff |
86 | #define OP_SH_SYSCALL 6 | |
87 | #define OP_MASK_SHAMT 0x1f | |
88 | #define OP_SH_SHAMT 6 | |
89 | #define OP_MASK_FD 0x1f | |
90 | #define OP_SH_FD 6 | |
91 | #define OP_MASK_TARGET 0x3ffffff | |
92 | #define OP_SH_TARGET 0 | |
93 | #define OP_MASK_COPZ 0x1ffffff | |
94 | #define OP_SH_COPZ 0 | |
95 | #define OP_MASK_IMMEDIATE 0xffff | |
96 | #define OP_SH_IMMEDIATE 0 | |
97 | #define OP_MASK_DELTA 0xffff | |
98 | #define OP_SH_DELTA 0 | |
99 | #define OP_MASK_FUNCT 0x3f | |
100 | #define OP_SH_FUNCT 0 | |
101 | #define OP_MASK_SPEC 0x3f | |
102 | #define OP_SH_SPEC 0 | |
2fedd0a1 DP |
103 | #define OP_SH_LOCC 8 /* FP condition code */ |
104 | #define OP_SH_HICC 18 /* FP condition code */ | |
105 | #define OP_MASK_CC 0x7 | |
106 | #define OP_SH_COP1NORM 25 /* Normal COP1 encoding */ | |
107 | #define OP_MASK_COP1NORM 0x1 /* a single bit */ | |
108 | #define OP_SH_COP1SPEC 21 /* COP1 encodings */ | |
109 | #define OP_MASK_COP1SPEC 0xf | |
110 | #define OP_MASK_COP1SCLR 0x4 | |
111 | #define OP_MASK_COP1CMP 0x3 | |
112 | #define OP_SH_COP1CMP 4 | |
113 | #define OP_SH_FORMAT 21 /* FP short format field */ | |
114 | #define OP_MASK_FORMAT 0x7 | |
115 | #define OP_SH_TRUE 16 | |
116 | #define OP_MASK_TRUE 0x1 | |
117 | #define OP_SH_GE 17 | |
118 | #define OP_MASK_GE 0x01 | |
119 | #define OP_SH_UNSIGNED 16 | |
120 | #define OP_MASK_UNSIGNED 0x1 | |
121 | #define OP_SH_HINT 16 | |
122 | #define OP_MASK_HINT 0x1f | |
123 | #define OP_SH_MMI 0 /* Multimedia (parallel) op */ | |
124 | #define OP_MASK_MMI 0x3f | |
125 | #define OP_SH_MMISUB 6 | |
b410ea2b | 126 | #define OP_MASK_MMISUB 0x1f |
b410ea2b KR |
127 | #define OP_MASK_PERFREG 0x1f /* Performance monitoring */ |
128 | #define OP_SH_PERFREG 1 | |
d3b42ce1 | 129 | /* start-sanitize-cygnus */ |
b410ea2b KR |
130 | #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, |
131 | but 0x8-0xf don't select bytes. */ | |
132 | #define OP_SH_VECBYTE 22 | |
133 | #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ | |
134 | #define OP_SH_VECALIGN 21 | |
d3b42ce1 GRK |
135 | /* end-sanitize-cygnus */ |
136 | /* start-sanitize-r5900 */ | |
137 | #define OP_SH_VADDI 6 | |
138 | #define OP_MASK_VADDI 0x1f | |
139 | #define OP_SH_VUTREG 16 | |
140 | #define OP_MASK_VUTREG 0x1f | |
141 | #define OP_SH_VUSREG 11 | |
142 | #define OP_MASK_VUSREG 0x1f | |
143 | #define OP_SH_VUDREG 6 | |
144 | #define OP_MASK_VUDREG 0x1f | |
145 | #define OP_SH_VUFSF 21 | |
146 | #define OP_MASK_VUFSF 0x3 | |
147 | #define OP_SH_VUFTF 23 | |
148 | #define OP_MASK_VUFTF 0x3 | |
149 | #define OP_SH_VUDEST 21 | |
150 | #define OP_MASK_VUDEST 0xf | |
151 | #define OP_SH_VUCALLMS 6 | |
152 | #define OP_MASK_VUCALLMS 0x7fff | |
153 | /* end-sanitize-r5900 */ | |
05166a28 ILT |
154 | |
155 | /* This structure holds information for a particular instruction. */ | |
156 | ||
157 | struct mips_opcode | |
158 | { | |
159 | /* The name of the instruction. */ | |
160 | const char *name; | |
161 | /* A string describing the arguments for this instruction. */ | |
162 | const char *args; | |
163 | /* The basic opcode for the instruction. When assembling, this | |
164 | opcode is modified by the arguments to produce the actual opcode | |
d3b42ce1 | 165 | that is used. If pinfo is INSN_MACRO, then this is 0. */ |
05166a28 ILT |
166 | unsigned long match; |
167 | /* If pinfo is not INSN_MACRO, then this is a bit mask for the | |
168 | relevant portions of the opcode when disassembling. If the | |
169 | actual opcode anded with the match field equals the opcode field, | |
170 | then we have found the correct instruction. If pinfo is | |
171 | INSN_MACRO, then this field is the macro identifier. */ | |
172 | unsigned long mask; | |
173 | /* For a macro, this is INSN_MACRO. Otherwise, it is a collection | |
174 | of bits describing the instruction, notably any relevant hazard | |
175 | information. */ | |
176 | unsigned long pinfo; | |
b410ea2b | 177 | /* A collection of bits describing the instruction sets of which this |
d3b42ce1 | 178 | instruction or macro is a member. */ |
b410ea2b | 179 | unsigned long membership; |
05166a28 ILT |
180 | }; |
181 | ||
182 | /* These are the characters which may appears in the args field of an | |
183 | instruction. They appear in the order in which the fields appear | |
184 | when the instruction is used. Commas and parentheses in the args | |
185 | string are ignored when assembling, and written into the output | |
186 | when disassembling. | |
187 | ||
188 | Each of these characters corresponds to a mask field defined above. | |
189 | ||
190 | "<" 5 bit shift amount (OP_*_SHAMT) | |
57ec4ed5 | 191 | ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) |
05166a28 ILT |
192 | "a" 26 bit target address (OP_*_TARGET) |
193 | "b" 5 bit base register (OP_*_RS) | |
194 | "c" 10 bit breakpoint code (OP_*_CODE) | |
195 | "d" 5 bit destination register specifier (OP_*_RD) | |
b5eab453 | 196 | "h" 5 bit prefx hint (OP_*_PREFX) |
05166a28 ILT |
197 | "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) |
198 | "j" 16 bit signed immediate (OP_*_DELTA) | |
57ec4ed5 | 199 | "k" 5 bit cache opcode in target register position (OP_*_CACHE) |
d3b42ce1 | 200 | start-sanitize-cygnus |
b410ea2b | 201 | also vr5400 vector ops immediate operand |
d3b42ce1 | 202 | end-sanitize-cygnus |
05166a28 ILT |
203 | "o" 16 bit signed offset (OP_*_DELTA) |
204 | "p" 16 bit PC relative branch target address (OP_*_DELTA) | |
d3b42ce1 | 205 | "q" 10 bit extra breakpoint code (OP_*_CODE2) |
05166a28 ILT |
206 | "r" 5 bit same register used as both source and target (OP_*_RS) |
207 | "s" 5 bit source register specifier (OP_*_RS) | |
208 | "t" 5 bit target register (OP_*_RT) | |
209 | "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) | |
210 | "v" 5 bit same register used as both source and destination (OP_*_RS) | |
211 | "w" 5 bit same register used as both target and destination (OP_*_RT) | |
212 | "C" 25 bit coprocessor function code (OP_*_COPZ) | |
213 | "B" 20 bit syscall function code (OP_*_SYSCALL) | |
0834f518 | 214 | "x" accept and ignore register name |
57ec4ed5 | 215 | "z" must be zero register |
05166a28 ILT |
216 | |
217 | Floating point instructions: | |
218 | "D" 5 bit destination register (OP_*_FD) | |
b5eab453 KR |
219 | "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) |
220 | "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) | |
05166a28 ILT |
221 | "S" 5 bit fs source 1 register (OP_*_FS) |
222 | "T" 5 bit ft source 2 register (OP_*_FT) | |
b5eab453 | 223 | "R" 5 bit fr source 3 register (OP_*_FR) |
05166a28 ILT |
224 | "V" 5 bit same register used as floating source and destination (OP_*_FS) |
225 | "W" 5 bit same register used as floating target and destination (OP_*_FT) | |
226 | ||
227 | Coprocessor instructions: | |
228 | "E" 5 bit target register (OP_*_RT) | |
229 | "G" 5 bit destination register (OP_*_RD) | |
b410ea2b | 230 | "P" 5 bit performance-monitor register (OP_*_PERFREG) |
d3b42ce1 | 231 | start-sanitize-cygnus |
b410ea2b KR |
232 | "e" 5 bit vector register byte specifier (OP_*_VECBYTE) |
233 | "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) | |
234 | see also "k" above | |
d3b42ce1 | 235 | end-sanitize-cygnus |
6ad9ba64 | 236 | start-sanitize-r5900 |
467caa5a | 237 | "0" vu0 immediate for viaddi |
6ad9ba64 DE |
238 | "1" vu0 fp reg position 1 |
239 | "2" vu0 fp reg position 2 | |
240 | "3" vu0 fp reg position 3 | |
241 | "4" vu0 int reg position 1 | |
242 | "5" vu0 int reg position 2 | |
243 | "6" vu0 int reg position 3 | |
244 | "7" vu0 fp reg with ftf modifier | |
245 | "8" vu0 fp reg with fsf modifier | |
246 | "9" vi27 for vcallmsr | |
247 | "#" optional suffix that must match if present | |
248 | "K" dest operant completer, must match previous dest if present | |
249 | "&" dest instruction completer | |
250 | ";" dest instruction completer, must by xyz | |
251 | "J" vu0 I register | |
252 | "Q" vu0 Q register | |
253 | "X" vu0 R register | |
254 | "U" vu0 ACC register | |
467caa5a | 255 | "O" Immediate operand for vcallms instruction. |
6ad9ba64 | 256 | end-sanitize-r5900 |
05166a28 ILT |
257 | |
258 | Macro instructions: | |
78641221 | 259 | "A" General 32 bit expression |
05166a28 | 260 | "I" 32 bit immediate |
78641221 ILT |
261 | "F" 64 bit floating point constant in .rdata |
262 | "L" 64 bit floating point constant in .lit8 | |
263 | "f" 32 bit floating point constant | |
264 | "l" 32 bit floating point constant in .lit4 | |
b410ea2b | 265 | |
336ffb47 KR |
266 | Other: |
267 | "()" parens surrounding optional value | |
268 | "," separates operands | |
d3b42ce1 | 269 | start-sanitize-cygnus |
336ffb47 | 270 | "[]" brackets around index for vector-op scalar operand specifier (vr5400) |
d3b42ce1 | 271 | end-sanitize-cygnus |
6ad9ba64 DE |
272 | start-sanitize-r5900 |
273 | "+-" auto inc/dec decorators | |
274 | end-sanitize-r5900 | |
336ffb47 | 275 | |
b410ea2b | 276 | Characters used so far, for quick reference when adding more: |
d3b42ce1 | 277 | start-sanitize-cygnus |
336ffb47 | 278 | "Pe%[]" plus... |
d3b42ce1 | 279 | end-sanitize-cygnus |
6ad9ba64 DE |
280 | start-sanitize-r5900 |
281 | "0123456789+-#&;KJWXUO" | |
282 | end-sanitize-r5900 | |
336ffb47 | 283 | "<>()," |
b410ea2b | 284 | "ABCDEFGILMNSTRVW" |
d3b42ce1 | 285 | "abcdfhijklopqrstuvwxz" |
05166a28 ILT |
286 | */ |
287 | ||
288 | /* These are the bits which may be set in the pinfo field of an | |
289 | instructions, if it is not equal to INSN_MACRO. */ | |
290 | ||
291 | /* Modifies the general purpose register in OP_*_RD. */ | |
292 | #define INSN_WRITE_GPR_D 0x00000001 | |
05166a28 | 293 | /* Modifies the general purpose register in OP_*_RT. */ |
0834f518 | 294 | #define INSN_WRITE_GPR_T 0x00000002 |
05166a28 | 295 | /* Modifies general purpose register 31. */ |
0834f518 | 296 | #define INSN_WRITE_GPR_31 0x00000004 |
763e8ded | 297 | /* Modifies the floating point register in OP_*_FD. */ |
0834f518 ILT |
298 | #define INSN_WRITE_FPR_D 0x00000008 |
299 | /* Modifies the floating point register in OP_*_FS. */ | |
300 | #define INSN_WRITE_FPR_S 0x00000010 | |
763e8ded | 301 | /* Modifies the floating point register in OP_*_FT. */ |
0834f518 | 302 | #define INSN_WRITE_FPR_T 0x00000020 |
05166a28 | 303 | /* Reads the general purpose register in OP_*_RS. */ |
0834f518 | 304 | #define INSN_READ_GPR_S 0x00000040 |
05166a28 | 305 | /* Reads the general purpose register in OP_*_RT. */ |
0834f518 | 306 | #define INSN_READ_GPR_T 0x00000080 |
763e8ded | 307 | /* Reads the floating point register in OP_*_FS. */ |
0834f518 | 308 | #define INSN_READ_FPR_S 0x00000100 |
763e8ded | 309 | /* Reads the floating point register in OP_*_FT. */ |
0834f518 | 310 | #define INSN_READ_FPR_T 0x00000200 |
b5eab453 KR |
311 | /* Reads the floating point register in OP_*_FR. */ |
312 | #define INSN_READ_FPR_R 0x00000400 | |
763e8ded | 313 | /* Modifies coprocessor condition code. */ |
b5eab453 | 314 | #define INSN_WRITE_COND_CODE 0x00000800 |
763e8ded | 315 | /* Reads coprocessor condition code. */ |
b5eab453 | 316 | #define INSN_READ_COND_CODE 0x00001000 |
05166a28 | 317 | /* TLB operation. */ |
b5eab453 | 318 | #define INSN_TLB 0x00002000 |
763e8ded | 319 | /* Reads coprocessor register other than floating point register. */ |
0834f518 ILT |
320 | #define INSN_COP 0x00004000 |
321 | /* Instruction loads value from memory, requiring delay. */ | |
322 | #define INSN_LOAD_MEMORY_DELAY 0x00008000 | |
323 | /* Instruction loads value from coprocessor, requiring delay. */ | |
324 | #define INSN_LOAD_COPROC_DELAY 0x00010000 | |
05166a28 | 325 | /* Instruction has unconditional branch delay slot. */ |
0834f518 | 326 | #define INSN_UNCOND_BRANCH_DELAY 0x00020000 |
05166a28 | 327 | /* Instruction has conditional branch delay slot. */ |
0834f518 ILT |
328 | #define INSN_COND_BRANCH_DELAY 0x00040000 |
329 | /* Conditional branch likely: if branch not taken, insn nullified. */ | |
330 | #define INSN_COND_BRANCH_LIKELY 0x00080000 | |
331 | /* Moves to coprocessor register, requiring delay. */ | |
332 | #define INSN_COPROC_MOVE_DELAY 0x00100000 | |
333 | /* Loads coprocessor register from memory, requiring delay. */ | |
334 | #define INSN_COPROC_MEMORY_DELAY 0x00200000 | |
05166a28 | 335 | /* Reads the HI register. */ |
0834f518 | 336 | #define INSN_READ_HI 0x00400000 |
05166a28 | 337 | /* Reads the LO register. */ |
0834f518 | 338 | #define INSN_READ_LO 0x00800000 |
05166a28 | 339 | /* Modifies the HI register. */ |
0834f518 | 340 | #define INSN_WRITE_HI 0x01000000 |
05166a28 | 341 | /* Modifies the LO register. */ |
0834f518 | 342 | #define INSN_WRITE_LO 0x02000000 |
57ec4ed5 | 343 | /* Takes a trap (easier to keep out of delay slot). */ |
0834f518 | 344 | #define INSN_TRAP 0x04000000 |
882d9d1a ILT |
345 | /* Instruction stores value into memory. */ |
346 | #define INSN_STORE_MEMORY 0x08000000 | |
b410ea2b KR |
347 | /* Instruction uses single precision floating point. */ |
348 | #define FP_S 0x10000000 | |
349 | /* Instruction uses double precision floating point. */ | |
350 | #define FP_D 0x20000000 | |
d3b42ce1 GRK |
351 | /* Instruction is part of the tx39's integer multiply family. */ |
352 | #define INSN_MULT 0x40000000 | |
467caa5a DE |
353 | /* Instruction synchronize shared memory. */ |
354 | #define INSN_SYNC 0x80000000 | |
b410ea2b KR |
355 | |
356 | /* Instruction is actually a macro. It should be ignored by the | |
357 | disassembler, and requires special treatment by the assembler. */ | |
358 | #define INSN_MACRO 0xffffffff | |
359 | ||
360 | ||
361 | ||
362 | ||
363 | ||
882d9d1a | 364 | /* MIPS ISA field--CPU level at which insn is supported. */ |
b410ea2b KR |
365 | #define INSN_ISA 0x0000000F |
366 | /* An instruction which is not part of any basic MIPS ISA. | |
367 | (ie it is a chip specific instruction) */ | |
368 | #define INSN_NO_ISA 0x00000000 | |
369 | /* MIPS ISA 1 instruction. */ | |
370 | #define INSN_ISA1 0x00000001 | |
0834f518 | 371 | /* MIPS ISA 2 instruction (R6000 or R4000). */ |
b410ea2b | 372 | #define INSN_ISA2 0x00000002 |
0834f518 | 373 | /* MIPS ISA 3 instruction (R4000). */ |
b410ea2b | 374 | #define INSN_ISA3 0x00000003 |
49f24512 | 375 | /* MIPS ISA 4 instruction (R8000). */ |
b410ea2b KR |
376 | #define INSN_ISA4 0x00000004 |
377 | ||
378 | /* Chip specific instructions. These are bitmasks. */ | |
379 | /* MIPS R4650 instruction. */ | |
380 | #define INSN_4650 0x00000010 | |
b5eab453 | 381 | /* LSI R4010 instruction. */ |
b410ea2b | 382 | #define INSN_4010 0x00000020 |
2fedd0a1 | 383 | /* NEC VR4100 instruction. */ |
b410ea2b KR |
384 | #define INSN_4100 0x00000040 |
385 | /* Toshiba R3900 instruction. */ | |
386 | #define INSN_3900 0x00000080 | |
d3b42ce1 GRK |
387 | /* start-sanitize-vr4320 */ |
388 | /* NEC VR4320 instruction. */ | |
389 | #define INSN_4320 0x00002000 | |
390 | /* end-sanitize-vr4320 */ | |
391 | /* start-sanitize-cygnus */ | |
b410ea2b KR |
392 | /* NEC VR5400 instruction. */ |
393 | #define INSN_5400 0x00001000 | |
d3b42ce1 | 394 | /* end-sanitize-cygnus */ |
2fedd0a1 DP |
395 | /* start-sanitize-r5900 */ |
396 | /* Toshiba R5900 instruction */ | |
b410ea2b | 397 | #define INSN_5900 0x00000100 |
2fedd0a1 | 398 | /* end-sanitize-r5900 */ |
c7227bdc GRK |
399 | /* start-sanitize-tx49 */ |
400 | #define INSN_4900 0x00000200 | |
401 | /* end-sanitize-tx49 */ | |
402 | ||
05166a28 | 403 | |
05166a28 ILT |
404 | /* This is a list of macro expanded instructions. |
405 | * | |
406 | * _I appended means immediate | |
407 | * _A appended means address | |
408 | * _AB appended means address with base register | |
78641221 ILT |
409 | * _D appended means 64 bit floating point constant |
410 | * _S appended means 32 bit floating point constant | |
05166a28 ILT |
411 | */ |
412 | enum { | |
413 | M_ABS, | |
05166a28 ILT |
414 | M_ADD_I, |
415 | M_ADDU_I, | |
416 | M_AND_I, | |
2fedd0a1 | 417 | M_BEQ, |
05166a28 | 418 | M_BEQ_I, |
0834f518 | 419 | M_BEQL_I, |
05166a28 | 420 | M_BGE, |
0834f518 | 421 | M_BGEL, |
05166a28 | 422 | M_BGE_I, |
0834f518 | 423 | M_BGEL_I, |
05166a28 | 424 | M_BGEU, |
0834f518 | 425 | M_BGEUL, |
05166a28 | 426 | M_BGEU_I, |
0834f518 | 427 | M_BGEUL_I, |
05166a28 | 428 | M_BGT, |
0834f518 | 429 | M_BGTL, |
05166a28 | 430 | M_BGT_I, |
0834f518 | 431 | M_BGTL_I, |
05166a28 | 432 | M_BGTU, |
0834f518 | 433 | M_BGTUL, |
05166a28 | 434 | M_BGTU_I, |
0834f518 | 435 | M_BGTUL_I, |
05166a28 | 436 | M_BLE, |
0834f518 | 437 | M_BLEL, |
05166a28 | 438 | M_BLE_I, |
0834f518 | 439 | M_BLEL_I, |
05166a28 | 440 | M_BLEU, |
0834f518 | 441 | M_BLEUL, |
05166a28 | 442 | M_BLEU_I, |
0834f518 | 443 | M_BLEUL_I, |
05166a28 | 444 | M_BLT, |
0834f518 | 445 | M_BLTL, |
05166a28 | 446 | M_BLT_I, |
0834f518 | 447 | M_BLTL_I, |
05166a28 | 448 | M_BLTU, |
0834f518 | 449 | M_BLTUL, |
05166a28 | 450 | M_BLTU_I, |
0834f518 | 451 | M_BLTUL_I, |
2fedd0a1 | 452 | M_BNE, |
05166a28 | 453 | M_BNE_I, |
0834f518 | 454 | M_BNEL_I, |
57ec4ed5 | 455 | M_DABS, |
0834f518 ILT |
456 | M_DADD_I, |
457 | M_DADDU_I, | |
458 | M_DDIV_3, | |
459 | M_DDIV_3I, | |
460 | M_DDIVU_3, | |
461 | M_DDIVU_3I, | |
05166a28 ILT |
462 | M_DIV_3, |
463 | M_DIV_3I, | |
464 | M_DIVU_3, | |
465 | M_DIVU_3I, | |
49f24512 ILT |
466 | M_DLA_AB, |
467 | M_DLI, | |
0834f518 ILT |
468 | M_DMUL, |
469 | M_DMUL_I, | |
470 | M_DMULO, | |
471 | M_DMULO_I, | |
472 | M_DMULOU, | |
473 | M_DMULOU_I, | |
474 | M_DREM_3, | |
475 | M_DREM_3I, | |
476 | M_DREMU_3, | |
477 | M_DREMU_3I, | |
478 | M_DSUB_I, | |
479 | M_DSUBU_I, | |
2fedd0a1 | 480 | M_DSUBU_I_2, |
57ec4ed5 ILT |
481 | M_J_A, |
482 | M_JAL_1, | |
483 | M_JAL_2, | |
484 | M_JAL_A, | |
05166a28 ILT |
485 | M_L_DOB, |
486 | M_L_DAB, | |
05166a28 ILT |
487 | M_LA_AB, |
488 | M_LB_A, | |
489 | M_LB_AB, | |
490 | M_LBU_A, | |
491 | M_LBU_AB, | |
492 | M_LD_A, | |
493 | M_LD_OB, | |
494 | M_LD_AB, | |
0834f518 ILT |
495 | M_LDC1_AB, |
496 | M_LDC2_AB, | |
497 | M_LDC3_AB, | |
498 | M_LDL_AB, | |
499 | M_LDR_AB, | |
05166a28 ILT |
500 | M_LH_A, |
501 | M_LH_AB, | |
502 | M_LHU_A, | |
503 | M_LHU_AB, | |
504 | M_LI, | |
505 | M_LI_D, | |
506 | M_LI_DD, | |
78641221 ILT |
507 | M_LI_S, |
508 | M_LI_SS, | |
0834f518 ILT |
509 | M_LL_AB, |
510 | M_LLD_AB, | |
05166a28 ILT |
511 | M_LS_A, |
512 | M_LW_A, | |
513 | M_LW_AB, | |
514 | M_LWC0_A, | |
515 | M_LWC0_AB, | |
516 | M_LWC1_A, | |
517 | M_LWC1_AB, | |
518 | M_LWC2_A, | |
519 | M_LWC2_AB, | |
520 | M_LWC3_A, | |
521 | M_LWC3_AB, | |
522 | M_LWL_A, | |
523 | M_LWL_AB, | |
524 | M_LWR_A, | |
525 | M_LWR_AB, | |
0834f518 | 526 | M_LWU_AB, |
05166a28 ILT |
527 | M_MUL, |
528 | M_MUL_I, | |
529 | M_MULO, | |
530 | M_MULO_I, | |
531 | M_MULOU, | |
532 | M_MULOU_I, | |
533 | M_NOR_I, | |
534 | M_OR_I, | |
535 | M_REM_3, | |
536 | M_REM_3I, | |
537 | M_REMU_3, | |
538 | M_REMU_3I, | |
539 | M_ROL, | |
540 | M_ROL_I, | |
541 | M_ROR, | |
542 | M_ROR_I, | |
543 | M_S_DA, | |
544 | M_S_DOB, | |
545 | M_S_DAB, | |
546 | M_S_S, | |
0834f518 ILT |
547 | M_SC_AB, |
548 | M_SCD_AB, | |
05166a28 ILT |
549 | M_SD_A, |
550 | M_SD_OB, | |
551 | M_SD_AB, | |
0834f518 ILT |
552 | M_SDC1_AB, |
553 | M_SDC2_AB, | |
554 | M_SDC3_AB, | |
555 | M_SDL_AB, | |
556 | M_SDR_AB, | |
05166a28 ILT |
557 | M_SEQ, |
558 | M_SEQ_I, | |
559 | M_SGE, | |
560 | M_SGE_I, | |
561 | M_SGEU, | |
562 | M_SGEU_I, | |
563 | M_SGT, | |
564 | M_SGT_I, | |
565 | M_SGTU, | |
566 | M_SGTU_I, | |
567 | M_SLE, | |
568 | M_SLE_I, | |
569 | M_SLEU, | |
570 | M_SLEU_I, | |
571 | M_SLT_I, | |
572 | M_SLTU_I, | |
573 | M_SNE, | |
574 | M_SNE_I, | |
575 | M_SB_A, | |
576 | M_SB_AB, | |
577 | M_SH_A, | |
578 | M_SH_AB, | |
579 | M_SW_A, | |
580 | M_SW_AB, | |
581 | M_SWC0_A, | |
582 | M_SWC0_AB, | |
583 | M_SWC1_A, | |
584 | M_SWC1_AB, | |
585 | M_SWC2_A, | |
586 | M_SWC2_AB, | |
587 | M_SWC3_A, | |
588 | M_SWC3_AB, | |
589 | M_SWL_A, | |
590 | M_SWL_AB, | |
591 | M_SWR_A, | |
592 | M_SWR_AB, | |
593 | M_SUB_I, | |
594 | M_SUBU_I, | |
2fedd0a1 | 595 | M_SUBU_I_2, |
0834f518 ILT |
596 | M_TEQ_I, |
597 | M_TGE_I, | |
598 | M_TGEU_I, | |
599 | M_TLT_I, | |
600 | M_TLTU_I, | |
601 | M_TNE_I, | |
05166a28 ILT |
602 | M_TRUNCWD, |
603 | M_TRUNCWS, | |
882d9d1a ILT |
604 | M_ULD, |
605 | M_ULD_A, | |
05166a28 ILT |
606 | M_ULH, |
607 | M_ULH_A, | |
608 | M_ULHU, | |
609 | M_ULHU_A, | |
610 | M_ULW, | |
611 | M_ULW_A, | |
612 | M_USH, | |
613 | M_USH_A, | |
614 | M_USW, | |
615 | M_USW_A, | |
882d9d1a ILT |
616 | M_USD, |
617 | M_USD_A, | |
2fedd0a1 DP |
618 | M_XOR_I, |
619 | M_COP0, | |
620 | M_COP1, | |
621 | M_COP2, | |
622 | M_COP3, | |
623 | M_NUM_MACROS | |
05166a28 ILT |
624 | }; |
625 | ||
2fedd0a1 | 626 | |
05166a28 ILT |
627 | /* The order of overloaded instructions matters. Label arguments and |
628 | register arguments look the same. Instructions that can have either | |
629 | for arguments must apear in the correct order in this table for the | |
630 | assembler to pick the right one. In other words, entries with | |
631 | immediate operands must apear after the same instruction with | |
632 | registers. | |
633 | ||
634 | Many instructions are short hand for other instructions (i.e., The | |
635 | jal <register> instruction is short for jalr <register>). */ | |
636 | ||
2fedd0a1 DP |
637 | extern const struct mips_opcode mips_builtin_opcodes[]; |
638 | extern const int bfd_mips_num_builtin_opcodes; | |
639 | extern struct mips_opcode *mips_opcodes; | |
640 | extern int bfd_mips_num_opcodes; | |
78641221 | 641 | #define NUMOPCODES bfd_mips_num_opcodes |
2fedd0a1 DP |
642 | |
643 | \f | |
644 | /* The rest of this file adds definitions for the mips16 TinyRISC | |
645 | processor. */ | |
646 | ||
647 | /* These are the bitmasks and shift counts used for the different | |
648 | fields in the instruction formats. Other than OP, no masks are | |
649 | provided for the fixed portions of an instruction, since they are | |
650 | not needed. | |
651 | ||
652 | The I format uses IMM11. | |
653 | ||
654 | The RI format uses RX and IMM8. | |
655 | ||
656 | The RR format uses RX, and RY. | |
657 | ||
658 | The RRI format uses RX, RY, and IMM5. | |
659 | ||
660 | The RRR format uses RX, RY, and RZ. | |
661 | ||
662 | The RRI_A format uses RX, RY, and IMM4. | |
663 | ||
664 | The SHIFT format uses RX, RY, and SHAMT. | |
665 | ||
666 | The I8 format uses IMM8. | |
667 | ||
668 | The I8_MOVR32 format uses RY and REGR32. | |
669 | ||
670 | The IR_MOV32R format uses REG32R and MOV32Z. | |
671 | ||
672 | The I64 format uses IMM8. | |
673 | ||
674 | The RI64 format uses RY and IMM5. | |
675 | */ | |
676 | ||
677 | #define MIPS16OP_MASK_OP 0x1f | |
678 | #define MIPS16OP_SH_OP 11 | |
679 | #define MIPS16OP_MASK_IMM11 0x7ff | |
680 | #define MIPS16OP_SH_IMM11 0 | |
681 | #define MIPS16OP_MASK_RX 0x7 | |
682 | #define MIPS16OP_SH_RX 8 | |
683 | #define MIPS16OP_MASK_IMM8 0xff | |
684 | #define MIPS16OP_SH_IMM8 0 | |
685 | #define MIPS16OP_MASK_RY 0x7 | |
686 | #define MIPS16OP_SH_RY 5 | |
687 | #define MIPS16OP_MASK_IMM5 0x1f | |
688 | #define MIPS16OP_SH_IMM5 0 | |
689 | #define MIPS16OP_MASK_RZ 0x7 | |
690 | #define MIPS16OP_SH_RZ 2 | |
691 | #define MIPS16OP_MASK_IMM4 0xf | |
692 | #define MIPS16OP_SH_IMM4 0 | |
693 | #define MIPS16OP_MASK_REGR32 0x1f | |
694 | #define MIPS16OP_SH_REGR32 0 | |
695 | #define MIPS16OP_MASK_REG32R 0x1f | |
696 | #define MIPS16OP_SH_REG32R 3 | |
697 | #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) | |
698 | #define MIPS16OP_MASK_MOVE32Z 0x7 | |
699 | #define MIPS16OP_SH_MOVE32Z 0 | |
700 | #define MIPS16OP_MASK_IMM6 0x3f | |
701 | #define MIPS16OP_SH_IMM6 5 | |
702 | ||
703 | /* These are the characters which may appears in the args field of an | |
704 | instruction. They appear in the order in which the fields appear | |
705 | when the instruction is used. Commas and parentheses in the args | |
706 | string are ignored when assembling, and written into the output | |
707 | when disassembling. | |
708 | ||
709 | "y" 3 bit register (MIPS16OP_*_RY) | |
710 | "x" 3 bit register (MIPS16OP_*_RX) | |
711 | "z" 3 bit register (MIPS16OP_*_RZ) | |
712 | "Z" 3 bit register (MIPS16OP_*_MOVE32Z) | |
713 | "v" 3 bit same register as source and destination (MIPS16OP_*_RX) | |
714 | "w" 3 bit same register as source and destination (MIPS16OP_*_RY) | |
715 | "0" zero register ($0) | |
716 | "S" stack pointer ($sp or $29) | |
717 | "P" program counter | |
718 | "R" return address register ($ra or $31) | |
719 | "X" 5 bit MIPS register (MIPS16OP_*_REGR32) | |
720 | "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) | |
721 | "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) | |
722 | "a" 26 bit jump address | |
723 | "e" 11 bit extension value | |
724 | "l" register list for entry instruction | |
725 | "L" register list for exit instruction | |
726 | ||
727 | The remaining codes may be extended. Except as otherwise noted, | |
728 | the full extended operand is a 16 bit signed value. | |
729 | "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) | |
730 | ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) | |
731 | "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) | |
732 | "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) | |
733 | "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) | |
734 | "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) | |
735 | "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) | |
736 | "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) | |
737 | "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) | |
738 | "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) | |
739 | "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) | |
740 | "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) | |
741 | "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) | |
742 | "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) | |
743 | "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) | |
744 | "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) | |
745 | "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) | |
746 | "q" 11 bit branch address (MIPS16OP_*_IMM11) | |
747 | "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) | |
748 | "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) | |
749 | "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) | |
750 | */ | |
751 | ||
752 | /* For the mips16, we use the same opcode table format and a few of | |
753 | the same flags. However, most of the flags are different. */ | |
754 | ||
755 | /* Modifies the register in MIPS16OP_*_RX. */ | |
756 | #define MIPS16_INSN_WRITE_X 0x00000001 | |
757 | /* Modifies the register in MIPS16OP_*_RY. */ | |
758 | #define MIPS16_INSN_WRITE_Y 0x00000002 | |
759 | /* Modifies the register in MIPS16OP_*_RZ. */ | |
760 | #define MIPS16_INSN_WRITE_Z 0x00000004 | |
761 | /* Modifies the T ($24) register. */ | |
762 | #define MIPS16_INSN_WRITE_T 0x00000008 | |
763 | /* Modifies the SP ($29) register. */ | |
764 | #define MIPS16_INSN_WRITE_SP 0x00000010 | |
765 | /* Modifies the RA ($31) register. */ | |
766 | #define MIPS16_INSN_WRITE_31 0x00000020 | |
767 | /* Modifies the general purpose register in MIPS16OP_*_REG32R. */ | |
768 | #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 | |
769 | /* Reads the register in MIPS16OP_*_RX. */ | |
770 | #define MIPS16_INSN_READ_X 0x00000080 | |
771 | /* Reads the register in MIPS16OP_*_RY. */ | |
772 | #define MIPS16_INSN_READ_Y 0x00000100 | |
773 | /* Reads the register in MIPS16OP_*_MOVE32Z. */ | |
774 | #define MIPS16_INSN_READ_Z 0x00000200 | |
775 | /* Reads the T ($24) register. */ | |
776 | #define MIPS16_INSN_READ_T 0x00000400 | |
777 | /* Reads the SP ($29) register. */ | |
778 | #define MIPS16_INSN_READ_SP 0x00000800 | |
779 | /* Reads the RA ($31) register. */ | |
780 | #define MIPS16_INSN_READ_31 0x00001000 | |
781 | /* Reads the program counter. */ | |
782 | #define MIPS16_INSN_READ_PC 0x00002000 | |
783 | /* Reads the general purpose register in MIPS16OP_*_REGR32. */ | |
784 | #define MIPS16_INSN_READ_GPR_X 0x00004000 | |
785 | ||
786 | /* The following flags have the same value for the mips16 opcode | |
787 | table: | |
788 | INSN_UNCOND_BRANCH_DELAY | |
789 | INSN_COND_BRANCH_DELAY | |
790 | INSN_COND_BRANCH_LIKELY (never used) | |
791 | INSN_READ_HI | |
792 | INSN_READ_LO | |
793 | INSN_WRITE_HI | |
794 | INSN_WRITE_LO | |
795 | INSN_TRAP | |
796 | INSN_ISA3 | |
797 | */ | |
798 | ||
799 | extern const struct mips_opcode mips16_opcodes[]; | |
800 | extern const int bfd_mips16_num_opcodes; | |
801 | ||
802 | #endif /* _MIPS_H_ */ |