Commit | Line | Data |
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252b5132 | 1 | /* mips.h. Mips opcode list for GDB, the GNU debugger. |
c3aa17e9 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
c67a084a | 3 | 2003, 2004, 2005, 2008, 2009, 2010 |
4f1d9bd8 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by Ralph Campbell and OSF |
6 | Commented and modified by Ian Lance Taylor, Cygnus Support | |
7 | ||
8 | This file is part of GDB, GAS, and the GNU binutils. | |
9 | ||
10 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
11 | them and/or modify them under the terms of the GNU General Public | |
12 | License as published by the Free Software Foundation; either version | |
13 | 1, or (at your option) any later version. | |
14 | ||
15 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
16 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
17 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
18 | the GNU General Public License for more details. | |
19 | ||
20 | You should have received a copy of the GNU General Public License | |
21 | along with this file; see the file COPYING. If not, write to the Free | |
e172dbf8 | 22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
252b5132 RH |
23 | |
24 | #ifndef _MIPS_H_ | |
25 | #define _MIPS_H_ | |
26 | ||
27 | /* These are bit masks and shift counts to use to access the various | |
28 | fields of an instruction. To retrieve the X field of an | |
29 | instruction, use the expression | |
30 | (i >> OP_SH_X) & OP_MASK_X | |
31 | To set the same field (to j), use | |
32 | i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) | |
33 | ||
34 | Make sure you use fields that are appropriate for the instruction, | |
8eaec934 | 35 | of course. |
252b5132 | 36 | |
8eaec934 | 37 | The 'i' format uses OP, RS, RT and IMMEDIATE. |
252b5132 RH |
38 | |
39 | The 'j' format uses OP and TARGET. | |
40 | ||
41 | The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. | |
42 | ||
43 | The 'b' format uses OP, RS, RT and DELTA. | |
44 | ||
45 | The floating point 'i' format uses OP, RS, RT and IMMEDIATE. | |
46 | ||
47 | The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. | |
48 | ||
49 | A breakpoint instruction uses OP, CODE and SPEC (10 bits of the | |
50 | breakpoint instruction are not defined; Kane says the breakpoint | |
51 | code field in BREAK is 20 bits; yet MIPS assemblers and debuggers | |
52 | only use ten bits). An optional two-operand form of break/sdbbp | |
4372b673 NC |
53 | allows the lower ten bits to be set too, and MIPS32 and later |
54 | architectures allow 20 bits to be set with a signal operand | |
55 | (using CODE20). | |
252b5132 | 56 | |
4372b673 | 57 | The syscall instruction uses CODE20. |
252b5132 RH |
58 | |
59 | The general coprocessor instructions use COPZ. */ | |
60 | ||
61 | #define OP_MASK_OP 0x3f | |
62 | #define OP_SH_OP 26 | |
63 | #define OP_MASK_RS 0x1f | |
64 | #define OP_SH_RS 21 | |
65 | #define OP_MASK_FR 0x1f | |
66 | #define OP_SH_FR 21 | |
67 | #define OP_MASK_FMT 0x1f | |
68 | #define OP_SH_FMT 21 | |
69 | #define OP_MASK_BCC 0x7 | |
70 | #define OP_SH_BCC 18 | |
71 | #define OP_MASK_CODE 0x3ff | |
72 | #define OP_SH_CODE 16 | |
73 | #define OP_MASK_CODE2 0x3ff | |
74 | #define OP_SH_CODE2 6 | |
75 | #define OP_MASK_RT 0x1f | |
76 | #define OP_SH_RT 16 | |
77 | #define OP_MASK_FT 0x1f | |
78 | #define OP_SH_FT 16 | |
79 | #define OP_MASK_CACHE 0x1f | |
80 | #define OP_SH_CACHE 16 | |
81 | #define OP_MASK_RD 0x1f | |
82 | #define OP_SH_RD 11 | |
83 | #define OP_MASK_FS 0x1f | |
84 | #define OP_SH_FS 11 | |
85 | #define OP_MASK_PREFX 0x1f | |
86 | #define OP_SH_PREFX 11 | |
87 | #define OP_MASK_CCC 0x7 | |
88 | #define OP_SH_CCC 8 | |
4372b673 NC |
89 | #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ |
90 | #define OP_SH_CODE20 6 | |
252b5132 RH |
91 | #define OP_MASK_SHAMT 0x1f |
92 | #define OP_SH_SHAMT 6 | |
93 | #define OP_MASK_FD 0x1f | |
94 | #define OP_SH_FD 6 | |
95 | #define OP_MASK_TARGET 0x3ffffff | |
96 | #define OP_SH_TARGET 0 | |
97 | #define OP_MASK_COPZ 0x1ffffff | |
98 | #define OP_SH_COPZ 0 | |
99 | #define OP_MASK_IMMEDIATE 0xffff | |
100 | #define OP_SH_IMMEDIATE 0 | |
101 | #define OP_MASK_DELTA 0xffff | |
102 | #define OP_SH_DELTA 0 | |
103 | #define OP_MASK_FUNCT 0x3f | |
104 | #define OP_SH_FUNCT 0 | |
105 | #define OP_MASK_SPEC 0x3f | |
106 | #define OP_SH_SPEC 0 | |
4372b673 NC |
107 | #define OP_SH_LOCC 8 /* FP condition code. */ |
108 | #define OP_SH_HICC 18 /* FP condition code. */ | |
252b5132 | 109 | #define OP_MASK_CC 0x7 |
4372b673 NC |
110 | #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ |
111 | #define OP_MASK_COP1NORM 0x1 /* a single bit. */ | |
112 | #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ | |
252b5132 RH |
113 | #define OP_MASK_COP1SPEC 0xf |
114 | #define OP_MASK_COP1SCLR 0x4 | |
115 | #define OP_MASK_COP1CMP 0x3 | |
116 | #define OP_SH_COP1CMP 4 | |
4372b673 | 117 | #define OP_SH_FORMAT 21 /* FP short format field. */ |
252b5132 RH |
118 | #define OP_MASK_FORMAT 0x7 |
119 | #define OP_SH_TRUE 16 | |
120 | #define OP_MASK_TRUE 0x1 | |
121 | #define OP_SH_GE 17 | |
122 | #define OP_MASK_GE 0x01 | |
123 | #define OP_SH_UNSIGNED 16 | |
124 | #define OP_MASK_UNSIGNED 0x1 | |
125 | #define OP_SH_HINT 16 | |
126 | #define OP_MASK_HINT 0x1f | |
4372b673 | 127 | #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ |
8eaec934 | 128 | #define OP_MASK_MMI 0x3f |
252b5132 RH |
129 | #define OP_SH_MMISUB 6 |
130 | #define OP_MASK_MMISUB 0x1f | |
4372b673 | 131 | #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ |
252b5132 | 132 | #define OP_SH_PERFREG 1 |
4372b673 NC |
133 | #define OP_SH_SEL 0 /* Coprocessor select field. */ |
134 | #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ | |
135 | #define OP_SH_CODE19 6 /* 19 bit wait code. */ | |
136 | #define OP_MASK_CODE19 0x7ffff | |
deec1734 CD |
137 | #define OP_SH_ALN 21 |
138 | #define OP_MASK_ALN 0x7 | |
139 | #define OP_SH_VSEL 21 | |
140 | #define OP_MASK_VSEL 0x1f | |
9752cf1b RS |
141 | #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, |
142 | but 0x8-0xf don't select bytes. */ | |
143 | #define OP_SH_VECBYTE 22 | |
144 | #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ | |
145 | #define OP_SH_VECALIGN 21 | |
af7ee8bf CD |
146 | #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ |
147 | #define OP_SH_INSMSB 11 | |
148 | #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ | |
149 | #define OP_SH_EXTMSBD 11 | |
deec1734 | 150 | |
93c34b9b CF |
151 | /* MIPS DSP ASE */ |
152 | #define OP_SH_DSPACC 11 | |
153 | #define OP_MASK_DSPACC 0x3 | |
154 | #define OP_SH_DSPACC_S 21 | |
155 | #define OP_MASK_DSPACC_S 0x3 | |
156 | #define OP_SH_DSPSFT 20 | |
157 | #define OP_MASK_DSPSFT 0x3f | |
158 | #define OP_SH_DSPSFT_7 19 | |
159 | #define OP_MASK_DSPSFT_7 0x7f | |
160 | #define OP_SH_SA3 21 | |
161 | #define OP_MASK_SA3 0x7 | |
162 | #define OP_SH_SA4 21 | |
163 | #define OP_MASK_SA4 0xf | |
164 | #define OP_SH_IMM8 16 | |
165 | #define OP_MASK_IMM8 0xff | |
166 | #define OP_SH_IMM10 16 | |
167 | #define OP_MASK_IMM10 0x3ff | |
168 | #define OP_SH_WRDSP 11 | |
169 | #define OP_MASK_WRDSP 0x3f | |
170 | #define OP_SH_RDDSP 16 | |
171 | #define OP_MASK_RDDSP 0x3f | |
8b082fb1 TS |
172 | #define OP_SH_BP 11 |
173 | #define OP_MASK_BP 0x3 | |
93c34b9b | 174 | |
089b39de CF |
175 | /* MIPS MT ASE */ |
176 | #define OP_SH_MT_U 5 | |
177 | #define OP_MASK_MT_U 0x1 | |
178 | #define OP_SH_MT_H 4 | |
179 | #define OP_MASK_MT_H 0x1 | |
180 | #define OP_SH_MTACC_T 18 | |
181 | #define OP_MASK_MTACC_T 0x3 | |
182 | #define OP_SH_MTACC_D 13 | |
183 | #define OP_MASK_MTACC_D 0x3 | |
184 | ||
640c0ccd CD |
185 | #define OP_OP_COP0 0x10 |
186 | #define OP_OP_COP1 0x11 | |
187 | #define OP_OP_COP2 0x12 | |
188 | #define OP_OP_COP3 0x13 | |
189 | #define OP_OP_LWC1 0x31 | |
190 | #define OP_OP_LWC2 0x32 | |
191 | #define OP_OP_LWC3 0x33 /* a.k.a. pref */ | |
192 | #define OP_OP_LDC1 0x35 | |
193 | #define OP_OP_LDC2 0x36 | |
194 | #define OP_OP_LDC3 0x37 /* a.k.a. ld */ | |
195 | #define OP_OP_SWC1 0x39 | |
196 | #define OP_OP_SWC2 0x3a | |
197 | #define OP_OP_SWC3 0x3b | |
198 | #define OP_OP_SDC1 0x3d | |
199 | #define OP_OP_SDC2 0x3e | |
200 | #define OP_OP_SDC3 0x3f /* a.k.a. sd */ | |
201 | ||
deec1734 CD |
202 | /* Values in the 'VSEL' field. */ |
203 | #define MDMX_FMTSEL_IMM_QH 0x1d | |
204 | #define MDMX_FMTSEL_IMM_OB 0x1e | |
205 | #define MDMX_FMTSEL_VEC_QH 0x15 | |
206 | #define MDMX_FMTSEL_VEC_OB 0x16 | |
4372b673 | 207 | |
9bcd4f99 TS |
208 | /* UDI */ |
209 | #define OP_SH_UDI1 6 | |
210 | #define OP_MASK_UDI1 0x1f | |
211 | #define OP_SH_UDI2 6 | |
212 | #define OP_MASK_UDI2 0x3ff | |
213 | #define OP_SH_UDI3 6 | |
214 | #define OP_MASK_UDI3 0x7fff | |
215 | #define OP_SH_UDI4 6 | |
216 | #define OP_MASK_UDI4 0xfffff | |
217 | ||
bb35fb24 NC |
218 | /* Octeon */ |
219 | #define OP_SH_BBITIND 16 | |
220 | #define OP_MASK_BBITIND 0x1f | |
221 | #define OP_SH_CINSPOS 6 | |
222 | #define OP_MASK_CINSPOS 0x1f | |
223 | #define OP_SH_CINSLM1 11 | |
224 | #define OP_MASK_CINSLM1 0x1f | |
dd3cbb7e NC |
225 | #define OP_SH_SEQI 6 |
226 | #define OP_MASK_SEQI 0x3ff | |
bb35fb24 | 227 | |
252b5132 RH |
228 | /* This structure holds information for a particular instruction. */ |
229 | ||
230 | struct mips_opcode | |
231 | { | |
232 | /* The name of the instruction. */ | |
233 | const char *name; | |
234 | /* A string describing the arguments for this instruction. */ | |
235 | const char *args; | |
236 | /* The basic opcode for the instruction. When assembling, this | |
237 | opcode is modified by the arguments to produce the actual opcode | |
238 | that is used. If pinfo is INSN_MACRO, then this is 0. */ | |
239 | unsigned long match; | |
240 | /* If pinfo is not INSN_MACRO, then this is a bit mask for the | |
241 | relevant portions of the opcode when disassembling. If the | |
242 | actual opcode anded with the match field equals the opcode field, | |
243 | then we have found the correct instruction. If pinfo is | |
244 | INSN_MACRO, then this field is the macro identifier. */ | |
245 | unsigned long mask; | |
246 | /* For a macro, this is INSN_MACRO. Otherwise, it is a collection | |
247 | of bits describing the instruction, notably any relevant hazard | |
248 | information. */ | |
249 | unsigned long pinfo; | |
dc9a9f39 FF |
250 | /* A collection of additional bits describing the instruction. */ |
251 | unsigned long pinfo2; | |
252b5132 RH |
252 | /* A collection of bits describing the instruction sets of which this |
253 | instruction or macro is a member. */ | |
254 | unsigned long membership; | |
255 | }; | |
256 | ||
27abff54 | 257 | /* These are the characters which may appear in the args field of an |
252b5132 RH |
258 | instruction. They appear in the order in which the fields appear |
259 | when the instruction is used. Commas and parentheses in the args | |
260 | string are ignored when assembling, and written into the output | |
261 | when disassembling. | |
262 | ||
263 | Each of these characters corresponds to a mask field defined above. | |
264 | ||
de9a3e51 | 265 | "1" 5 bit sync type (OP_*_SHAMT) |
252b5132 RH |
266 | "<" 5 bit shift amount (OP_*_SHAMT) |
267 | ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) | |
268 | "a" 26 bit target address (OP_*_TARGET) | |
269 | "b" 5 bit base register (OP_*_RS) | |
270 | "c" 10 bit breakpoint code (OP_*_CODE) | |
271 | "d" 5 bit destination register specifier (OP_*_RD) | |
272 | "h" 5 bit prefx hint (OP_*_PREFX) | |
273 | "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) | |
274 | "j" 16 bit signed immediate (OP_*_DELTA) | |
275 | "k" 5 bit cache opcode in target register position (OP_*_CACHE) | |
9752cf1b | 276 | Also used for immediate operands in vr5400 vector insns. |
252b5132 RH |
277 | "o" 16 bit signed offset (OP_*_DELTA) |
278 | "p" 16 bit PC relative branch target address (OP_*_DELTA) | |
279 | "q" 10 bit extra breakpoint code (OP_*_CODE2) | |
280 | "r" 5 bit same register used as both source and target (OP_*_RS) | |
281 | "s" 5 bit source register specifier (OP_*_RS) | |
282 | "t" 5 bit target register (OP_*_RT) | |
283 | "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) | |
284 | "v" 5 bit same register used as both source and destination (OP_*_RS) | |
285 | "w" 5 bit same register used as both target and destination (OP_*_RT) | |
4372b673 NC |
286 | "U" 5 bit same destination register in both OP_*_RD and OP_*_RT |
287 | (used by clo and clz) | |
252b5132 | 288 | "C" 25 bit coprocessor function code (OP_*_COPZ) |
4372b673 NC |
289 | "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) |
290 | "J" 19 bit wait function code (OP_*_CODE19) | |
252b5132 RH |
291 | "x" accept and ignore register name |
292 | "z" must be zero register | |
af7ee8bf | 293 | "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) |
ef0ee844 TS |
294 | "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes |
295 | LSB (OP_*_SHAMT). | |
071742cf | 296 | Enforces: 0 <= pos < 32. |
ef0ee844 | 297 | "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). |
5f74bc13 | 298 | Requires that "+A" or "+E" occur first to set position. |
071742cf | 299 | Enforces: 0 < (pos+size) <= 32. |
ef0ee844 | 300 | "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). |
5f74bc13 | 301 | Requires that "+A" or "+E" occur first to set position. |
071742cf | 302 | Enforces: 0 < (pos+size) <= 32. |
5f74bc13 CD |
303 | (Also used by "dext" w/ different limits, but limits for |
304 | that are checked by the M_DEXT macro.) | |
ef0ee844 | 305 | "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). |
5f74bc13 | 306 | Enforces: 32 <= pos < 64. |
ef0ee844 | 307 | "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). |
5f74bc13 CD |
308 | Requires that "+A" or "+E" occur first to set position. |
309 | Enforces: 32 < (pos+size) <= 64. | |
310 | "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). | |
311 | Requires that "+A" or "+E" occur first to set position. | |
312 | Enforces: 32 < (pos+size) <= 64. | |
313 | "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). | |
314 | Requires that "+A" or "+E" occur first to set position. | |
315 | Enforces: 32 < (pos+size) <= 64. | |
252b5132 RH |
316 | |
317 | Floating point instructions: | |
318 | "D" 5 bit destination register (OP_*_FD) | |
319 | "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) | |
320 | "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) | |
321 | "S" 5 bit fs source 1 register (OP_*_FS) | |
322 | "T" 5 bit ft source 2 register (OP_*_FT) | |
323 | "R" 5 bit fr source 3 register (OP_*_FR) | |
324 | "V" 5 bit same register used as floating source and destination (OP_*_FS) | |
325 | "W" 5 bit same register used as floating target and destination (OP_*_FT) | |
326 | ||
327 | Coprocessor instructions: | |
328 | "E" 5 bit target register (OP_*_RT) | |
329 | "G" 5 bit destination register (OP_*_RD) | |
8ff529d8 | 330 | "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) |
252b5132 | 331 | "P" 5 bit performance-monitor register (OP_*_PERFREG) |
9752cf1b RS |
332 | "e" 5 bit vector register byte specifier (OP_*_VECBYTE) |
333 | "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) | |
334 | see also "k" above | |
bbcc0807 CD |
335 | "+D" Combined destination register ("G") and sel ("H") for CP0 ops, |
336 | for pretty-printing in disassembly only. | |
252b5132 RH |
337 | |
338 | Macro instructions: | |
339 | "A" General 32 bit expression | |
5f74bc13 CD |
340 | "I" 32 bit immediate (value placed in imm_expr). |
341 | "+I" 32 bit immediate (value placed in imm2_expr). | |
252b5132 RH |
342 | "F" 64 bit floating point constant in .rdata |
343 | "L" 64 bit floating point constant in .lit8 | |
344 | "f" 32 bit floating point constant | |
345 | "l" 32 bit floating point constant in .lit4 | |
346 | ||
deec1734 CD |
347 | MDMX instruction operands (note that while these use the FP register |
348 | fields, they accept both $fN and $vN names for the registers): | |
349 | "O" MDMX alignment offset (OP_*_ALN) | |
350 | "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) | |
351 | "X" MDMX destination register (OP_*_FD) | |
352 | "Y" MDMX source register (OP_*_FS) | |
353 | "Z" MDMX source register (OP_*_FT) | |
354 | ||
93c34b9b | 355 | DSP ASE usage: |
8b082fb1 | 356 | "2" 2 bit unsigned immediate for byte align (OP_*_BP) |
93c34b9b CF |
357 | "3" 3 bit unsigned immediate (OP_*_SA3) |
358 | "4" 4 bit unsigned immediate (OP_*_SA4) | |
359 | "5" 8 bit unsigned immediate (OP_*_IMM8) | |
360 | "6" 5 bit unsigned immediate (OP_*_RS) | |
361 | "7" 2 bit dsp accumulator register (OP_*_DSPACC) | |
362 | "8" 6 bit unsigned immediate (OP_*_WRDSP) | |
363 | "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) | |
364 | "0" 6 bit signed immediate (OP_*_DSPSFT) | |
365 | ":" 7 bit signed immediate (OP_*_DSPSFT_7) | |
366 | "'" 6 bit unsigned immediate (OP_*_RDDSP) | |
367 | "@" 10 bit signed immediate (OP_*_IMM10) | |
368 | ||
089b39de | 369 | MT ASE usage: |
a9e24354 TS |
370 | "!" 1 bit usermode flag (OP_*_MT_U) |
371 | "$" 1 bit load high flag (OP_*_MT_H) | |
089b39de CF |
372 | "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) |
373 | "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) | |
374 | "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) | |
375 | "+t" 5 bit coprocessor 0 destination register (OP_*_RT) | |
376 | "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only | |
377 | ||
9bcd4f99 TS |
378 | UDI immediates: |
379 | "+1" UDI immediate bits 6-10 | |
380 | "+2" UDI immediate bits 6-15 | |
381 | "+3" UDI immediate bits 6-20 | |
382 | "+4" UDI immediate bits 6-25 | |
383 | ||
bb35fb24 NC |
384 | Octeon: |
385 | "+x" Bit index field of bbit. Enforces: 0 <= index < 32. | |
386 | "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64, | |
387 | otherwise skips to next candidate. | |
388 | "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32. | |
389 | "+P" Position field of cins/exts aliasing cins32/exts32. Matches if | |
390 | 32 <= pos < 64, otherwise skips to next candidate. | |
dd3cbb7e | 391 | "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512. |
bb35fb24 NC |
392 | "+s" Length-minus-one field of cins/exts. Enforces: 0 <= lenm1 < 32. |
393 | "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing | |
394 | cint32/exts32. Enforces non-negative value and that | |
395 | pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous | |
396 | position field is "+p" or "+P". | |
397 | ||
252b5132 RH |
398 | Other: |
399 | "()" parens surrounding optional value | |
400 | "," separates operands | |
9752cf1b | 401 | "[]" brackets around index for vector-op scalar operand specifier (vr5400) |
af7ee8bf | 402 | "+" Start of extension sequence. |
252b5132 RH |
403 | |
404 | Characters used so far, for quick reference when adding more: | |
de9a3e51 | 405 | "1234567890" |
089b39de | 406 | "%[]<>(),+:'@!$*&" |
af7ee8bf | 407 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" |
089b39de | 408 | "abcdefghijklopqrstuvwxz" |
af7ee8bf CD |
409 | |
410 | Extension character sequences used so far ("+" followed by the | |
411 | following), for quick reference when adding more: | |
9bcd4f99 | 412 | "1234" |
dd3cbb7e | 413 | "ABCDEFGHIPQSTX" |
bb35fb24 | 414 | "pstx" |
252b5132 RH |
415 | */ |
416 | ||
417 | /* These are the bits which may be set in the pinfo field of an | |
418 | instructions, if it is not equal to INSN_MACRO. */ | |
419 | ||
420 | /* Modifies the general purpose register in OP_*_RD. */ | |
421 | #define INSN_WRITE_GPR_D 0x00000001 | |
422 | /* Modifies the general purpose register in OP_*_RT. */ | |
423 | #define INSN_WRITE_GPR_T 0x00000002 | |
424 | /* Modifies general purpose register 31. */ | |
425 | #define INSN_WRITE_GPR_31 0x00000004 | |
426 | /* Modifies the floating point register in OP_*_FD. */ | |
427 | #define INSN_WRITE_FPR_D 0x00000008 | |
428 | /* Modifies the floating point register in OP_*_FS. */ | |
429 | #define INSN_WRITE_FPR_S 0x00000010 | |
430 | /* Modifies the floating point register in OP_*_FT. */ | |
431 | #define INSN_WRITE_FPR_T 0x00000020 | |
432 | /* Reads the general purpose register in OP_*_RS. */ | |
433 | #define INSN_READ_GPR_S 0x00000040 | |
434 | /* Reads the general purpose register in OP_*_RT. */ | |
435 | #define INSN_READ_GPR_T 0x00000080 | |
436 | /* Reads the floating point register in OP_*_FS. */ | |
437 | #define INSN_READ_FPR_S 0x00000100 | |
438 | /* Reads the floating point register in OP_*_FT. */ | |
439 | #define INSN_READ_FPR_T 0x00000200 | |
440 | /* Reads the floating point register in OP_*_FR. */ | |
441 | #define INSN_READ_FPR_R 0x00000400 | |
442 | /* Modifies coprocessor condition code. */ | |
443 | #define INSN_WRITE_COND_CODE 0x00000800 | |
444 | /* Reads coprocessor condition code. */ | |
445 | #define INSN_READ_COND_CODE 0x00001000 | |
446 | /* TLB operation. */ | |
447 | #define INSN_TLB 0x00002000 | |
448 | /* Reads coprocessor register other than floating point register. */ | |
449 | #define INSN_COP 0x00004000 | |
450 | /* Instruction loads value from memory, requiring delay. */ | |
451 | #define INSN_LOAD_MEMORY_DELAY 0x00008000 | |
452 | /* Instruction loads value from coprocessor, requiring delay. */ | |
453 | #define INSN_LOAD_COPROC_DELAY 0x00010000 | |
454 | /* Instruction has unconditional branch delay slot. */ | |
455 | #define INSN_UNCOND_BRANCH_DELAY 0x00020000 | |
456 | /* Instruction has conditional branch delay slot. */ | |
457 | #define INSN_COND_BRANCH_DELAY 0x00040000 | |
458 | /* Conditional branch likely: if branch not taken, insn nullified. */ | |
459 | #define INSN_COND_BRANCH_LIKELY 0x00080000 | |
460 | /* Moves to coprocessor register, requiring delay. */ | |
461 | #define INSN_COPROC_MOVE_DELAY 0x00100000 | |
462 | /* Loads coprocessor register from memory, requiring delay. */ | |
463 | #define INSN_COPROC_MEMORY_DELAY 0x00200000 | |
464 | /* Reads the HI register. */ | |
465 | #define INSN_READ_HI 0x00400000 | |
466 | /* Reads the LO register. */ | |
467 | #define INSN_READ_LO 0x00800000 | |
468 | /* Modifies the HI register. */ | |
469 | #define INSN_WRITE_HI 0x01000000 | |
470 | /* Modifies the LO register. */ | |
471 | #define INSN_WRITE_LO 0x02000000 | |
472 | /* Takes a trap (easier to keep out of delay slot). */ | |
473 | #define INSN_TRAP 0x04000000 | |
474 | /* Instruction stores value into memory. */ | |
475 | #define INSN_STORE_MEMORY 0x08000000 | |
476 | /* Instruction uses single precision floating point. */ | |
477 | #define FP_S 0x10000000 | |
478 | /* Instruction uses double precision floating point. */ | |
479 | #define FP_D 0x20000000 | |
480 | /* Instruction is part of the tx39's integer multiply family. */ | |
481 | #define INSN_MULT 0x40000000 | |
482 | /* Instruction synchronize shared memory. */ | |
483 | #define INSN_SYNC 0x80000000 | |
d0799671 AN |
484 | /* Instruction is actually a macro. It should be ignored by the |
485 | disassembler, and requires special treatment by the assembler. */ | |
486 | #define INSN_MACRO 0xffffffff | |
dc9a9f39 FF |
487 | |
488 | /* These are the bits which may be set in the pinfo2 field of an | |
489 | instruction. */ | |
490 | ||
491 | /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ | |
239cb185 | 492 | #define INSN2_ALIAS 0x00000001 |
dc9a9f39 | 493 | /* Instruction reads MDMX accumulator. */ |
239cb185 | 494 | #define INSN2_READ_MDMX_ACC 0x00000002 |
dc9a9f39 | 495 | /* Instruction writes MDMX accumulator. */ |
239cb185 | 496 | #define INSN2_WRITE_MDMX_ACC 0x00000004 |
d0799671 AN |
497 | /* Macro uses single-precision floating-point instructions. This should |
498 | only be set for macros. For instructions, FP_S in pinfo carries the | |
499 | same information. */ | |
500 | #define INSN2_M_FP_S 0x00000008 | |
501 | /* Macro uses double-precision floating-point instructions. This should | |
502 | only be set for macros. For instructions, FP_D in pinfo carries the | |
503 | same information. */ | |
504 | #define INSN2_M_FP_D 0x00000010 | |
252b5132 | 505 | |
e7af610e | 506 | /* Masks used to mark instructions to indicate which MIPS ISA level |
56950294 MS |
507 | they were introduced in. INSN_ISA_MASK masks an enumeration that |
508 | specifies the base ISA level(s). The remainder of a 32-bit | |
509 | word constructed using these macros is a bitmask of the remaining | |
510 | INSN_* values below. */ | |
511 | ||
512 | #define INSN_ISA_MASK 0x0000000ful | |
513 | ||
514 | /* We cannot start at zero due to ISA_UNKNOWN below. */ | |
515 | #define INSN_ISA1 1 | |
516 | #define INSN_ISA2 2 | |
517 | #define INSN_ISA3 3 | |
518 | #define INSN_ISA4 4 | |
519 | #define INSN_ISA5 5 | |
520 | #define INSN_ISA32 6 | |
521 | #define INSN_ISA32R2 7 | |
522 | #define INSN_ISA64 8 | |
523 | #define INSN_ISA64R2 9 | |
524 | /* Below this point the INSN_* values correspond to combinations of ISAs. | |
525 | They are only for use in the opcodes table to indicate membership of | |
526 | a combination of ISAs that cannot be expressed using the usual inclusion | |
527 | ordering on the above INSN_* values. */ | |
528 | #define INSN_ISA3_32 10 | |
529 | #define INSN_ISA3_32R2 11 | |
530 | #define INSN_ISA4_32 12 | |
531 | #define INSN_ISA4_32R2 13 | |
532 | #define INSN_ISA5_32R2 14 | |
533 | ||
534 | /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through | |
535 | INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2, | |
536 | this table describes whether at least one of the ISAs described by X | |
537 | is/are implemented by ISA Y. (Think of Y as the ISA level supported by | |
538 | a particular core and X as the ISA level(s) at which a certain instruction | |
539 | is defined.) The ISA(s) described by X is/are implemented by Y iff | |
540 | (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1 | |
541 | is non-zero. */ | |
542 | static const unsigned int mips_isa_table[] = | |
543 | { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; | |
252b5132 | 544 | |
e6429699 | 545 | /* Masks used for Chip specific instructions. */ |
52b6b6b9 | 546 | #define INSN_CHIP_MASK 0xc3ff0820 |
e6429699 AN |
547 | |
548 | /* Cavium Networks Octeon instructions. */ | |
549 | #define INSN_OCTEON 0x00000800 | |
550 | ||
1f25f5d3 | 551 | /* Masks used for MIPS-defined ASEs. */ |
8b082fb1 | 552 | #define INSN_ASE_MASK 0x3c00f000 |
1f25f5d3 | 553 | |
93c34b9b CF |
554 | /* DSP ASE */ |
555 | #define INSN_DSP 0x00001000 | |
65263ce3 | 556 | #define INSN_DSP64 0x00002000 |
aec421e0 | 557 | /* MIPS 16 ASE */ |
65263ce3 | 558 | #define INSN_MIPS16 0x00004000 |
1f25f5d3 | 559 | /* MIPS-3D ASE */ |
65263ce3 | 560 | #define INSN_MIPS3D 0x00008000 |
1f25f5d3 | 561 | |
252b5132 | 562 | /* MIPS R4650 instruction. */ |
e7af610e | 563 | #define INSN_4650 0x00010000 |
252b5132 | 564 | /* LSI R4010 instruction. */ |
e7af610e NC |
565 | #define INSN_4010 0x00020000 |
566 | /* NEC VR4100 instruction. */ | |
bf40d919 | 567 | #define INSN_4100 0x00040000 |
252b5132 | 568 | /* Toshiba R3900 instruction. */ |
bf40d919 | 569 | #define INSN_3900 0x00080000 |
99c14723 TS |
570 | /* MIPS R10000 instruction. */ |
571 | #define INSN_10000 0x00100000 | |
2228315b CD |
572 | /* Broadcom SB-1 instruction. */ |
573 | #define INSN_SB1 0x00200000 | |
9752cf1b RS |
574 | /* NEC VR4111/VR4181 instruction. */ |
575 | #define INSN_4111 0x00400000 | |
576 | /* NEC VR4120 instruction. */ | |
577 | #define INSN_4120 0x00800000 | |
578 | /* NEC VR5400 instruction. */ | |
579 | #define INSN_5400 0x01000000 | |
580 | /* NEC VR5500 instruction. */ | |
581 | #define INSN_5500 0x02000000 | |
39a7806d | 582 | |
65263ce3 TS |
583 | /* MDMX ASE */ |
584 | #define INSN_MDMX 0x04000000 | |
089b39de | 585 | /* MT ASE */ |
65263ce3 | 586 | #define INSN_MT 0x08000000 |
8b082fb1 | 587 | /* SmartMIPS ASE */ |
65263ce3 | 588 | #define INSN_SMARTMIPS 0x10000000 |
8b082fb1 TS |
589 | /* DSP R2 ASE */ |
590 | #define INSN_DSPR2 0x20000000 | |
350cc38d MS |
591 | /* ST Microelectronics Loongson 2E. */ |
592 | #define INSN_LOONGSON_2E 0x40000000 | |
593 | /* ST Microelectronics Loongson 2F. */ | |
594 | #define INSN_LOONGSON_2F 0x80000000 | |
52b6b6b9 JM |
595 | /* RMI Xlr instruction */ |
596 | #define INSN_XLR 0x00000020 | |
39a7806d | 597 | |
e7af610e NC |
598 | /* MIPS ISA defines, use instead of hardcoding ISA level. */ |
599 | ||
600 | #define ISA_UNKNOWN 0 /* Gas internal use. */ | |
56950294 MS |
601 | #define ISA_MIPS1 INSN_ISA1 |
602 | #define ISA_MIPS2 INSN_ISA2 | |
603 | #define ISA_MIPS3 INSN_ISA3 | |
604 | #define ISA_MIPS4 INSN_ISA4 | |
605 | #define ISA_MIPS5 INSN_ISA5 | |
af7ee8bf | 606 | |
56950294 MS |
607 | #define ISA_MIPS32 INSN_ISA32 |
608 | #define ISA_MIPS64 INSN_ISA64 | |
367c01af | 609 | |
56950294 MS |
610 | #define ISA_MIPS32R2 INSN_ISA32R2 |
611 | #define ISA_MIPS64R2 INSN_ISA64R2 | |
5f74bc13 | 612 | |
af7ee8bf | 613 | |
156c2f8b NC |
614 | /* CPU defines, use instead of hardcoding processor number. Keep this |
615 | in sync with bfd/archures.c in order for machine selection to work. */ | |
e7af610e | 616 | #define CPU_UNKNOWN 0 /* Gas internal use. */ |
156c2f8b NC |
617 | #define CPU_R3000 3000 |
618 | #define CPU_R3900 3900 | |
619 | #define CPU_R4000 4000 | |
620 | #define CPU_R4010 4010 | |
621 | #define CPU_VR4100 4100 | |
622 | #define CPU_R4111 4111 | |
9752cf1b | 623 | #define CPU_VR4120 4120 |
156c2f8b NC |
624 | #define CPU_R4300 4300 |
625 | #define CPU_R4400 4400 | |
626 | #define CPU_R4600 4600 | |
627 | #define CPU_R4650 4650 | |
628 | #define CPU_R5000 5000 | |
9752cf1b RS |
629 | #define CPU_VR5400 5400 |
630 | #define CPU_VR5500 5500 | |
156c2f8b | 631 | #define CPU_R6000 6000 |
5a7ea749 | 632 | #define CPU_RM7000 7000 |
156c2f8b | 633 | #define CPU_R8000 8000 |
98e7aba8 | 634 | #define CPU_RM9000 9000 |
156c2f8b | 635 | #define CPU_R10000 10000 |
d1cf510e | 636 | #define CPU_R12000 12000 |
3aa3176b TS |
637 | #define CPU_R14000 14000 |
638 | #define CPU_R16000 16000 | |
156c2f8b NC |
639 | #define CPU_MIPS16 16 |
640 | #define CPU_MIPS32 32 | |
af7ee8bf | 641 | #define CPU_MIPS32R2 33 |
84ea6cf2 NC |
642 | #define CPU_MIPS5 5 |
643 | #define CPU_MIPS64 64 | |
5f74bc13 | 644 | #define CPU_MIPS64R2 65 |
c6c98b38 | 645 | #define CPU_SB1 12310201 /* octal 'SB', 01. */ |
350cc38d MS |
646 | #define CPU_LOONGSON_2E 3001 |
647 | #define CPU_LOONGSON_2F 3002 | |
e6429699 | 648 | #define CPU_OCTEON 6501 |
52b6b6b9 | 649 | #define CPU_XLR 887682 /* decimal 'XLR' */ |
156c2f8b | 650 | |
1f25f5d3 CD |
651 | /* Test for membership in an ISA including chip specific ISAs. INSN |
652 | is pointer to an element of the opcode table; ISA is the specified | |
653 | ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to | |
654 | test, or zero if no CPU specific ISA test is desired. */ | |
a58ec95a RS |
655 | |
656 | #define OPCODE_IS_MEMBER(insn, isa, cpu) \ | |
56950294 MS |
657 | (((isa & INSN_ISA_MASK) != 0 \ |
658 | && ((insn)->membership & INSN_ISA_MASK) != 0 \ | |
659 | && ((mips_isa_table [(isa & INSN_ISA_MASK) - 1] >> \ | |
660 | (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) \ | |
661 | || ((isa & ~INSN_ISA_MASK) \ | |
662 | & ((insn)->membership & ~INSN_ISA_MASK)) != 0 \ | |
156c2f8b | 663 | || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ |
5a7ea749 | 664 | || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ |
98e7aba8 | 665 | || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ |
156c2f8b | 666 | || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ |
9752cf1b | 667 | || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ |
99c14723 | 668 | || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ |
3aa3176b TS |
669 | || ((cpu == CPU_R10000 || cpu == CPU_R12000 || cpu == CPU_R14000 \ |
670 | || cpu == CPU_R16000) \ | |
2228315b | 671 | && ((insn)->membership & INSN_10000) != 0) \ |
5d84d93f | 672 | || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ |
9752cf1b RS |
673 | || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \ |
674 | || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \ | |
675 | || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \ | |
676 | || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \ | |
350cc38d MS |
677 | || (cpu == CPU_LOONGSON_2E \ |
678 | && ((insn)->membership & INSN_LOONGSON_2E) != 0) \ | |
679 | || (cpu == CPU_LOONGSON_2F \ | |
680 | && ((insn)->membership & INSN_LOONGSON_2F) != 0) \ | |
e6429699 AN |
681 | || (cpu == CPU_OCTEON \ |
682 | && ((insn)->membership & INSN_OCTEON) != 0) \ | |
52b6b6b9 | 683 | || (cpu == CPU_XLR && ((insn)->membership & INSN_XLR) != 0) \ |
e4432525 | 684 | || 0) /* Please keep this term for easier source merging. */ |
252b5132 RH |
685 | |
686 | /* This is a list of macro expanded instructions. | |
8eaec934 | 687 | |
e7af610e NC |
688 | _I appended means immediate |
689 | _A appended means address | |
690 | _AB appended means address with base register | |
691 | _D appended means 64 bit floating point constant | |
692 | _S appended means 32 bit floating point constant. */ | |
693 | ||
694 | enum | |
695 | { | |
696 | M_ABS, | |
697 | M_ADD_I, | |
698 | M_ADDU_I, | |
699 | M_AND_I, | |
8b082fb1 | 700 | M_BALIGN, |
e7af610e NC |
701 | M_BEQ, |
702 | M_BEQ_I, | |
703 | M_BEQL_I, | |
704 | M_BGE, | |
705 | M_BGEL, | |
706 | M_BGE_I, | |
707 | M_BGEL_I, | |
708 | M_BGEU, | |
709 | M_BGEUL, | |
710 | M_BGEU_I, | |
711 | M_BGEUL_I, | |
712 | M_BGT, | |
713 | M_BGTL, | |
714 | M_BGT_I, | |
715 | M_BGTL_I, | |
716 | M_BGTU, | |
717 | M_BGTUL, | |
718 | M_BGTU_I, | |
719 | M_BGTUL_I, | |
720 | M_BLE, | |
721 | M_BLEL, | |
722 | M_BLE_I, | |
723 | M_BLEL_I, | |
724 | M_BLEU, | |
725 | M_BLEUL, | |
726 | M_BLEU_I, | |
727 | M_BLEUL_I, | |
728 | M_BLT, | |
729 | M_BLTL, | |
730 | M_BLT_I, | |
731 | M_BLTL_I, | |
732 | M_BLTU, | |
733 | M_BLTUL, | |
734 | M_BLTU_I, | |
735 | M_BLTUL_I, | |
736 | M_BNE, | |
737 | M_BNE_I, | |
738 | M_BNEL_I, | |
d43b4baf | 739 | M_CACHE_AB, |
e7af610e NC |
740 | M_DABS, |
741 | M_DADD_I, | |
742 | M_DADDU_I, | |
743 | M_DDIV_3, | |
744 | M_DDIV_3I, | |
745 | M_DDIVU_3, | |
746 | M_DDIVU_3I, | |
5f74bc13 CD |
747 | M_DEXT, |
748 | M_DINS, | |
e7af610e NC |
749 | M_DIV_3, |
750 | M_DIV_3I, | |
751 | M_DIVU_3, | |
752 | M_DIVU_3I, | |
753 | M_DLA_AB, | |
1abe91b1 | 754 | M_DLCA_AB, |
e7af610e NC |
755 | M_DLI, |
756 | M_DMUL, | |
8eaec934 | 757 | M_DMUL_I, |
e7af610e | 758 | M_DMULO, |
8eaec934 | 759 | M_DMULO_I, |
e7af610e | 760 | M_DMULOU, |
8eaec934 | 761 | M_DMULOU_I, |
e7af610e NC |
762 | M_DREM_3, |
763 | M_DREM_3I, | |
764 | M_DREMU_3, | |
765 | M_DREMU_3I, | |
766 | M_DSUB_I, | |
767 | M_DSUBU_I, | |
768 | M_DSUBU_I_2, | |
769 | M_J_A, | |
770 | M_JAL_1, | |
771 | M_JAL_2, | |
772 | M_JAL_A, | |
773 | M_L_DOB, | |
774 | M_L_DAB, | |
775 | M_LA_AB, | |
776 | M_LB_A, | |
777 | M_LB_AB, | |
778 | M_LBU_A, | |
779 | M_LBU_AB, | |
1abe91b1 | 780 | M_LCA_AB, |
e7af610e NC |
781 | M_LD_A, |
782 | M_LD_OB, | |
783 | M_LD_AB, | |
784 | M_LDC1_AB, | |
785 | M_LDC2_AB, | |
786 | M_LDC3_AB, | |
787 | M_LDL_AB, | |
788 | M_LDR_AB, | |
789 | M_LH_A, | |
790 | M_LH_AB, | |
791 | M_LHU_A, | |
792 | M_LHU_AB, | |
793 | M_LI, | |
794 | M_LI_D, | |
795 | M_LI_DD, | |
796 | M_LI_S, | |
797 | M_LI_SS, | |
798 | M_LL_AB, | |
799 | M_LLD_AB, | |
800 | M_LS_A, | |
801 | M_LW_A, | |
802 | M_LW_AB, | |
803 | M_LWC0_A, | |
804 | M_LWC0_AB, | |
805 | M_LWC1_A, | |
806 | M_LWC1_AB, | |
807 | M_LWC2_A, | |
808 | M_LWC2_AB, | |
809 | M_LWC3_A, | |
810 | M_LWC3_AB, | |
811 | M_LWL_A, | |
812 | M_LWL_AB, | |
813 | M_LWR_A, | |
814 | M_LWR_AB, | |
815 | M_LWU_AB, | |
52b6b6b9 JM |
816 | M_MSGSND, |
817 | M_MSGLD, | |
818 | M_MSGLD_T, | |
819 | M_MSGWAIT, | |
820 | M_MSGWAIT_T, | |
a58ec95a | 821 | M_MOVE, |
e7af610e | 822 | M_MUL, |
8eaec934 | 823 | M_MUL_I, |
e7af610e | 824 | M_MULO, |
8eaec934 | 825 | M_MULO_I, |
e7af610e | 826 | M_MULOU, |
8eaec934 | 827 | M_MULOU_I, |
e7af610e NC |
828 | M_NOR_I, |
829 | M_OR_I, | |
830 | M_REM_3, | |
831 | M_REM_3I, | |
832 | M_REMU_3, | |
833 | M_REMU_3I, | |
771c7ce4 | 834 | M_DROL, |
e7af610e | 835 | M_ROL, |
771c7ce4 | 836 | M_DROL_I, |
e7af610e | 837 | M_ROL_I, |
771c7ce4 | 838 | M_DROR, |
e7af610e | 839 | M_ROR, |
771c7ce4 | 840 | M_DROR_I, |
e7af610e NC |
841 | M_ROR_I, |
842 | M_S_DA, | |
843 | M_S_DOB, | |
844 | M_S_DAB, | |
845 | M_S_S, | |
846 | M_SC_AB, | |
847 | M_SCD_AB, | |
848 | M_SD_A, | |
849 | M_SD_OB, | |
850 | M_SD_AB, | |
851 | M_SDC1_AB, | |
852 | M_SDC2_AB, | |
853 | M_SDC3_AB, | |
854 | M_SDL_AB, | |
855 | M_SDR_AB, | |
856 | M_SEQ, | |
857 | M_SEQ_I, | |
858 | M_SGE, | |
859 | M_SGE_I, | |
860 | M_SGEU, | |
861 | M_SGEU_I, | |
862 | M_SGT, | |
863 | M_SGT_I, | |
864 | M_SGTU, | |
865 | M_SGTU_I, | |
866 | M_SLE, | |
867 | M_SLE_I, | |
868 | M_SLEU, | |
869 | M_SLEU_I, | |
870 | M_SLT_I, | |
871 | M_SLTU_I, | |
872 | M_SNE, | |
873 | M_SNE_I, | |
874 | M_SB_A, | |
875 | M_SB_AB, | |
876 | M_SH_A, | |
877 | M_SH_AB, | |
878 | M_SW_A, | |
879 | M_SW_AB, | |
880 | M_SWC0_A, | |
881 | M_SWC0_AB, | |
882 | M_SWC1_A, | |
883 | M_SWC1_AB, | |
884 | M_SWC2_A, | |
885 | M_SWC2_AB, | |
886 | M_SWC3_A, | |
887 | M_SWC3_AB, | |
888 | M_SWL_A, | |
889 | M_SWL_AB, | |
890 | M_SWR_A, | |
891 | M_SWR_AB, | |
892 | M_SUB_I, | |
893 | M_SUBU_I, | |
894 | M_SUBU_I_2, | |
895 | M_TEQ_I, | |
896 | M_TGE_I, | |
897 | M_TGEU_I, | |
898 | M_TLT_I, | |
899 | M_TLTU_I, | |
900 | M_TNE_I, | |
901 | M_TRUNCWD, | |
902 | M_TRUNCWS, | |
903 | M_ULD, | |
904 | M_ULD_A, | |
905 | M_ULH, | |
906 | M_ULH_A, | |
907 | M_ULHU, | |
908 | M_ULHU_A, | |
909 | M_ULW, | |
910 | M_ULW_A, | |
911 | M_USH, | |
912 | M_USH_A, | |
913 | M_USW, | |
914 | M_USW_A, | |
915 | M_USD, | |
916 | M_USD_A, | |
917 | M_XOR_I, | |
918 | M_COP0, | |
919 | M_COP1, | |
920 | M_COP2, | |
921 | M_COP3, | |
922 | M_NUM_MACROS | |
252b5132 RH |
923 | }; |
924 | ||
925 | ||
926 | /* The order of overloaded instructions matters. Label arguments and | |
927 | register arguments look the same. Instructions that can have either | |
928 | for arguments must apear in the correct order in this table for the | |
929 | assembler to pick the right one. In other words, entries with | |
930 | immediate operands must apear after the same instruction with | |
931 | registers. | |
932 | ||
933 | Many instructions are short hand for other instructions (i.e., The | |
934 | jal <register> instruction is short for jalr <register>). */ | |
935 | ||
936 | extern const struct mips_opcode mips_builtin_opcodes[]; | |
937 | extern const int bfd_mips_num_builtin_opcodes; | |
938 | extern struct mips_opcode *mips_opcodes; | |
939 | extern int bfd_mips_num_opcodes; | |
940 | #define NUMOPCODES bfd_mips_num_opcodes | |
941 | ||
942 | \f | |
943 | /* The rest of this file adds definitions for the mips16 TinyRISC | |
944 | processor. */ | |
945 | ||
946 | /* These are the bitmasks and shift counts used for the different | |
947 | fields in the instruction formats. Other than OP, no masks are | |
948 | provided for the fixed portions of an instruction, since they are | |
949 | not needed. | |
950 | ||
951 | The I format uses IMM11. | |
952 | ||
953 | The RI format uses RX and IMM8. | |
954 | ||
955 | The RR format uses RX, and RY. | |
956 | ||
957 | The RRI format uses RX, RY, and IMM5. | |
958 | ||
959 | The RRR format uses RX, RY, and RZ. | |
960 | ||
961 | The RRI_A format uses RX, RY, and IMM4. | |
962 | ||
963 | The SHIFT format uses RX, RY, and SHAMT. | |
964 | ||
965 | The I8 format uses IMM8. | |
966 | ||
967 | The I8_MOVR32 format uses RY and REGR32. | |
968 | ||
969 | The IR_MOV32R format uses REG32R and MOV32Z. | |
970 | ||
971 | The I64 format uses IMM8. | |
972 | ||
973 | The RI64 format uses RY and IMM5. | |
974 | */ | |
975 | ||
976 | #define MIPS16OP_MASK_OP 0x1f | |
977 | #define MIPS16OP_SH_OP 11 | |
978 | #define MIPS16OP_MASK_IMM11 0x7ff | |
979 | #define MIPS16OP_SH_IMM11 0 | |
980 | #define MIPS16OP_MASK_RX 0x7 | |
981 | #define MIPS16OP_SH_RX 8 | |
982 | #define MIPS16OP_MASK_IMM8 0xff | |
983 | #define MIPS16OP_SH_IMM8 0 | |
984 | #define MIPS16OP_MASK_RY 0x7 | |
985 | #define MIPS16OP_SH_RY 5 | |
986 | #define MIPS16OP_MASK_IMM5 0x1f | |
987 | #define MIPS16OP_SH_IMM5 0 | |
988 | #define MIPS16OP_MASK_RZ 0x7 | |
989 | #define MIPS16OP_SH_RZ 2 | |
990 | #define MIPS16OP_MASK_IMM4 0xf | |
991 | #define MIPS16OP_SH_IMM4 0 | |
992 | #define MIPS16OP_MASK_REGR32 0x1f | |
993 | #define MIPS16OP_SH_REGR32 0 | |
994 | #define MIPS16OP_MASK_REG32R 0x1f | |
995 | #define MIPS16OP_SH_REG32R 3 | |
996 | #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) | |
997 | #define MIPS16OP_MASK_MOVE32Z 0x7 | |
998 | #define MIPS16OP_SH_MOVE32Z 0 | |
999 | #define MIPS16OP_MASK_IMM6 0x3f | |
1000 | #define MIPS16OP_SH_IMM6 5 | |
1001 | ||
bb35fb24 NC |
1002 | /* These are the characters which may appears in the args field of a MIPS16 |
1003 | instruction. They appear in the order in which the fields appear when the | |
1004 | instruction is used. Commas and parentheses in the args string are ignored | |
1005 | when assembling, and written into the output when disassembling. | |
252b5132 RH |
1006 | |
1007 | "y" 3 bit register (MIPS16OP_*_RY) | |
1008 | "x" 3 bit register (MIPS16OP_*_RX) | |
1009 | "z" 3 bit register (MIPS16OP_*_RZ) | |
1010 | "Z" 3 bit register (MIPS16OP_*_MOVE32Z) | |
1011 | "v" 3 bit same register as source and destination (MIPS16OP_*_RX) | |
1012 | "w" 3 bit same register as source and destination (MIPS16OP_*_RY) | |
1013 | "0" zero register ($0) | |
1014 | "S" stack pointer ($sp or $29) | |
1015 | "P" program counter | |
1016 | "R" return address register ($ra or $31) | |
1017 | "X" 5 bit MIPS register (MIPS16OP_*_REGR32) | |
1018 | "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) | |
1019 | "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) | |
1020 | "a" 26 bit jump address | |
1021 | "e" 11 bit extension value | |
1022 | "l" register list for entry instruction | |
1023 | "L" register list for exit instruction | |
1024 | ||
1025 | The remaining codes may be extended. Except as otherwise noted, | |
1026 | the full extended operand is a 16 bit signed value. | |
1027 | "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) | |
1028 | ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) | |
1029 | "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) | |
1030 | "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) | |
1031 | "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) | |
1032 | "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) | |
1033 | "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) | |
1034 | "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) | |
1035 | "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) | |
1036 | "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) | |
1037 | "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) | |
1038 | "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) | |
1039 | "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) | |
1040 | "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) | |
1041 | "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) | |
1042 | "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) | |
1043 | "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) | |
1044 | "q" 11 bit branch address (MIPS16OP_*_IMM11) | |
1045 | "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) | |
1046 | "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) | |
1047 | "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) | |
0499d65b TS |
1048 | "m" 7 bit register list for save instruction (18 bit extended) |
1049 | "M" 7 bit register list for restore instruction (18 bit extended) | |
1050 | */ | |
1051 | ||
1052 | /* Save/restore encoding for the args field when all 4 registers are | |
1053 | either saved as arguments or saved/restored as statics. */ | |
1054 | #define MIPS16_ALL_ARGS 0xe | |
1055 | #define MIPS16_ALL_STATICS 0xb | |
252b5132 RH |
1056 | |
1057 | /* For the mips16, we use the same opcode table format and a few of | |
1058 | the same flags. However, most of the flags are different. */ | |
1059 | ||
1060 | /* Modifies the register in MIPS16OP_*_RX. */ | |
1061 | #define MIPS16_INSN_WRITE_X 0x00000001 | |
1062 | /* Modifies the register in MIPS16OP_*_RY. */ | |
1063 | #define MIPS16_INSN_WRITE_Y 0x00000002 | |
1064 | /* Modifies the register in MIPS16OP_*_RZ. */ | |
1065 | #define MIPS16_INSN_WRITE_Z 0x00000004 | |
1066 | /* Modifies the T ($24) register. */ | |
1067 | #define MIPS16_INSN_WRITE_T 0x00000008 | |
1068 | /* Modifies the SP ($29) register. */ | |
1069 | #define MIPS16_INSN_WRITE_SP 0x00000010 | |
1070 | /* Modifies the RA ($31) register. */ | |
1071 | #define MIPS16_INSN_WRITE_31 0x00000020 | |
1072 | /* Modifies the general purpose register in MIPS16OP_*_REG32R. */ | |
1073 | #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 | |
1074 | /* Reads the register in MIPS16OP_*_RX. */ | |
1075 | #define MIPS16_INSN_READ_X 0x00000080 | |
1076 | /* Reads the register in MIPS16OP_*_RY. */ | |
1077 | #define MIPS16_INSN_READ_Y 0x00000100 | |
1078 | /* Reads the register in MIPS16OP_*_MOVE32Z. */ | |
1079 | #define MIPS16_INSN_READ_Z 0x00000200 | |
1080 | /* Reads the T ($24) register. */ | |
1081 | #define MIPS16_INSN_READ_T 0x00000400 | |
1082 | /* Reads the SP ($29) register. */ | |
1083 | #define MIPS16_INSN_READ_SP 0x00000800 | |
1084 | /* Reads the RA ($31) register. */ | |
1085 | #define MIPS16_INSN_READ_31 0x00001000 | |
1086 | /* Reads the program counter. */ | |
1087 | #define MIPS16_INSN_READ_PC 0x00002000 | |
1088 | /* Reads the general purpose register in MIPS16OP_*_REGR32. */ | |
1089 | #define MIPS16_INSN_READ_GPR_X 0x00004000 | |
1090 | /* Is a branch insn. */ | |
1091 | #define MIPS16_INSN_BRANCH 0x00010000 | |
1092 | ||
1093 | /* The following flags have the same value for the mips16 opcode | |
1094 | table: | |
1095 | INSN_UNCOND_BRANCH_DELAY | |
1096 | INSN_COND_BRANCH_DELAY | |
1097 | INSN_COND_BRANCH_LIKELY (never used) | |
1098 | INSN_READ_HI | |
1099 | INSN_READ_LO | |
1100 | INSN_WRITE_HI | |
1101 | INSN_WRITE_LO | |
1102 | INSN_TRAP | |
1103 | INSN_ISA3 | |
1104 | */ | |
1105 | ||
1106 | extern const struct mips_opcode mips16_opcodes[]; | |
1107 | extern const int bfd_mips16_num_opcodes; | |
1108 | ||
c67a084a NC |
1109 | /* A NOP insn impemented as "or at,at,zero". |
1110 | Used to implement -mfix-loongson2f. */ | |
1111 | #define LOONGSON2F_NOP_INSN 0x00200825 | |
1112 | ||
252b5132 | 1113 | #endif /* _MIPS_H_ */ |