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Fix register name printed in warning message.
[deliverable/binutils-gdb.git] / include / opcode / mips.h
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252b5132 1/* mips.h. Mips opcode list for GDB, the GNU debugger.
4f1d9bd8
NC		 2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
252b5132
RH		 4 Contributed by Ralph Campbell and OSF
5 Commented and modified by Ian Lance Taylor, Cygnus Support
6
7This file is part of GDB, GAS, and the GNU binutils.
8
9GDB, GAS, and the GNU binutils are free software; you can redistribute
10them and/or modify them under the terms of the GNU General Public
11License as published by the Free Software Foundation; either version
121, or (at your option) any later version.
13
14GDB, GAS, and the GNU binutils are distributed in the hope that they
15will be useful, but WITHOUT ANY WARRANTY; without even the implied
16warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
17the GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License
20along with this file; see the file COPYING. If not, write to the Free
21Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22
23#ifndef _MIPS_H_
24#define _MIPS_H_
25
26/* These are bit masks and shift counts to use to access the various
27 fields of an instruction. To retrieve the X field of an
28 instruction, use the expression
29 (i >> OP_SH_X) & OP_MASK_X
30 To set the same field (to j), use
31 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
32
33 Make sure you use fields that are appropriate for the instruction,
8eaec934 34 of course.
252b5132 35
8eaec934 36 The 'i' format uses OP, RS, RT and IMMEDIATE.
252b5132
RH		 37
38 The 'j' format uses OP and TARGET.
39
40 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
41
42 The 'b' format uses OP, RS, RT and DELTA.
43
44 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
45
46 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
47
48 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
49 breakpoint instruction are not defined; Kane says the breakpoint
50 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
51 only use ten bits). An optional two-operand form of break/sdbbp
4372b673
NC		 52 allows the lower ten bits to be set too, and MIPS32 and later
53 architectures allow 20 bits to be set with a signal operand
54 (using CODE20).
252b5132 55
4372b673 56 The syscall instruction uses CODE20.
252b5132
RH		 57
58 The general coprocessor instructions use COPZ. */
59
60#define OP_MASK_OP 0x3f
61#define OP_SH_OP 26
62#define OP_MASK_RS 0x1f
63#define OP_SH_RS 21
64#define OP_MASK_FR 0x1f
65#define OP_SH_FR 21
66#define OP_MASK_FMT 0x1f
67#define OP_SH_FMT 21
68#define OP_MASK_BCC 0x7
69#define OP_SH_BCC 18
70#define OP_MASK_CODE 0x3ff
71#define OP_SH_CODE 16
72#define OP_MASK_CODE2 0x3ff
73#define OP_SH_CODE2 6
74#define OP_MASK_RT 0x1f
75#define OP_SH_RT 16
76#define OP_MASK_FT 0x1f
77#define OP_SH_FT 16
78#define OP_MASK_CACHE 0x1f
79#define OP_SH_CACHE 16
80#define OP_MASK_RD 0x1f
81#define OP_SH_RD 11
82#define OP_MASK_FS 0x1f
83#define OP_SH_FS 11
84#define OP_MASK_PREFX 0x1f
85#define OP_SH_PREFX 11
86#define OP_MASK_CCC 0x7
87#define OP_SH_CCC 8
4372b673
NC		 88#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
89#define OP_SH_CODE20 6
252b5132
RH		 90#define OP_MASK_SHAMT 0x1f
91#define OP_SH_SHAMT 6
92#define OP_MASK_FD 0x1f
93#define OP_SH_FD 6
94#define OP_MASK_TARGET 0x3ffffff
95#define OP_SH_TARGET 0
96#define OP_MASK_COPZ 0x1ffffff
97#define OP_SH_COPZ 0
98#define OP_MASK_IMMEDIATE 0xffff
99#define OP_SH_IMMEDIATE 0
100#define OP_MASK_DELTA 0xffff
101#define OP_SH_DELTA 0
102#define OP_MASK_FUNCT 0x3f
103#define OP_SH_FUNCT 0
104#define OP_MASK_SPEC 0x3f
105#define OP_SH_SPEC 0
4372b673
NC		 106#define OP_SH_LOCC 8 /* FP condition code. */
107#define OP_SH_HICC 18 /* FP condition code. */
252b5132 108#define OP_MASK_CC 0x7
4372b673
NC		 109#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
110#define OP_MASK_COP1NORM 0x1 /* a single bit. */
111#define OP_SH_COP1SPEC 21 /* COP1 encodings. */
252b5132
RH		 112#define OP_MASK_COP1SPEC 0xf
113#define OP_MASK_COP1SCLR 0x4
114#define OP_MASK_COP1CMP 0x3
115#define OP_SH_COP1CMP 4
4372b673 116#define OP_SH_FORMAT 21 /* FP short format field. */
252b5132
RH		 117#define OP_MASK_FORMAT 0x7
118#define OP_SH_TRUE 16
119#define OP_MASK_TRUE 0x1
120#define OP_SH_GE 17
121#define OP_MASK_GE 0x01
122#define OP_SH_UNSIGNED 16
123#define OP_MASK_UNSIGNED 0x1
124#define OP_SH_HINT 16
125#define OP_MASK_HINT 0x1f
4372b673 126#define OP_SH_MMI 0 /* Multimedia (parallel) op. */
8eaec934 127#define OP_MASK_MMI 0x3f
252b5132
RH		 128#define OP_SH_MMISUB 6
129#define OP_MASK_MMISUB 0x1f
4372b673 130#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
252b5132 131#define OP_SH_PERFREG 1
4372b673
NC		 132#define OP_SH_SEL 0 /* Coprocessor select field. */
133#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
134#define OP_SH_CODE19 6 /* 19 bit wait code. */
135#define OP_MASK_CODE19 0x7ffff
136
252b5132
RH		 137/* This structure holds information for a particular instruction. */
138
139struct mips_opcode
140{
141 /* The name of the instruction. */
142 const char *name;
143 /* A string describing the arguments for this instruction. */
144 const char *args;
145 /* The basic opcode for the instruction. When assembling, this
146 opcode is modified by the arguments to produce the actual opcode
147 that is used. If pinfo is INSN_MACRO, then this is 0. */
148 unsigned long match;
149 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
150 relevant portions of the opcode when disassembling. If the
151 actual opcode anded with the match field equals the opcode field,
152 then we have found the correct instruction. If pinfo is
153 INSN_MACRO, then this field is the macro identifier. */
154 unsigned long mask;
155 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
156 of bits describing the instruction, notably any relevant hazard
157 information. */
158 unsigned long pinfo;
159 /* A collection of bits describing the instruction sets of which this
160 instruction or macro is a member. */
161 unsigned long membership;
162};
163
164/* These are the characters which may appears in the args field of an
165 instruction. They appear in the order in which the fields appear
166 when the instruction is used. Commas and parentheses in the args
167 string are ignored when assembling, and written into the output
168 when disassembling.
169
170 Each of these characters corresponds to a mask field defined above.
171
172 "<" 5 bit shift amount (OP_*_SHAMT)
173 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
174 "a" 26 bit target address (OP_*_TARGET)
175 "b" 5 bit base register (OP_*_RS)
176 "c" 10 bit breakpoint code (OP_*_CODE)
177 "d" 5 bit destination register specifier (OP_*_RD)
178 "h" 5 bit prefx hint (OP_*_PREFX)
179 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
180 "j" 16 bit signed immediate (OP_*_DELTA)
181 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
182 "o" 16 bit signed offset (OP_*_DELTA)
183 "p" 16 bit PC relative branch target address (OP_*_DELTA)
184 "q" 10 bit extra breakpoint code (OP_*_CODE2)
185 "r" 5 bit same register used as both source and target (OP_*_RS)
186 "s" 5 bit source register specifier (OP_*_RS)
187 "t" 5 bit target register (OP_*_RT)
188 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
189 "v" 5 bit same register used as both source and destination (OP_*_RS)
190 "w" 5 bit same register used as both target and destination (OP_*_RT)
4372b673
NC		 191 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
192 (used by clo and clz)
252b5132 193 "C" 25 bit coprocessor function code (OP_*_COPZ)
4372b673
NC		 194 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
195 "J" 19 bit wait function code (OP_*_CODE19)
252b5132
RH		 196 "x" accept and ignore register name
197 "z" must be zero register
198
199 Floating point instructions:
200 "D" 5 bit destination register (OP_*_FD)
201 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
202 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
203 "S" 5 bit fs source 1 register (OP_*_FS)
204 "T" 5 bit ft source 2 register (OP_*_FT)
205 "R" 5 bit fr source 3 register (OP_*_FR)
206 "V" 5 bit same register used as floating source and destination (OP_*_FS)
207 "W" 5 bit same register used as floating target and destination (OP_*_FT)
208
209 Coprocessor instructions:
210 "E" 5 bit target register (OP_*_RT)
211 "G" 5 bit destination register (OP_*_RD)
212 "P" 5 bit performance-monitor register (OP_*_PERFREG)
156c2f8b 213 "H" 3 bit sel field (OP_*_SEL)
252b5132
RH		 214
215 Macro instructions:
216 "A" General 32 bit expression
217 "I" 32 bit immediate
218 "F" 64 bit floating point constant in .rdata
219 "L" 64 bit floating point constant in .lit8
220 "f" 32 bit floating point constant
221 "l" 32 bit floating point constant in .lit4
222
223 Other:
224 "()" parens surrounding optional value
225 "," separates operands
226
227 Characters used so far, for quick reference when adding more:
228 "<>(),"
4372b673
NC		 229 "ABCDEFGHIJLMNPRSTUVW"
230 "abcdfhijklopqrstuvwxz"
252b5132
RH		 231*/
232
233/* These are the bits which may be set in the pinfo field of an
234 instructions, if it is not equal to INSN_MACRO. */
235
236/* Modifies the general purpose register in OP_*_RD. */
237#define INSN_WRITE_GPR_D 0x00000001
238/* Modifies the general purpose register in OP_*_RT. */
239#define INSN_WRITE_GPR_T 0x00000002
240/* Modifies general purpose register 31. */
241#define INSN_WRITE_GPR_31 0x00000004
242/* Modifies the floating point register in OP_*_FD. */
243#define INSN_WRITE_FPR_D 0x00000008
244/* Modifies the floating point register in OP_*_FS. */
245#define INSN_WRITE_FPR_S 0x00000010
246/* Modifies the floating point register in OP_*_FT. */
247#define INSN_WRITE_FPR_T 0x00000020
248/* Reads the general purpose register in OP_*_RS. */
249#define INSN_READ_GPR_S 0x00000040
250/* Reads the general purpose register in OP_*_RT. */
251#define INSN_READ_GPR_T 0x00000080
252/* Reads the floating point register in OP_*_FS. */
253#define INSN_READ_FPR_S 0x00000100
254/* Reads the floating point register in OP_*_FT. */
255#define INSN_READ_FPR_T 0x00000200
256/* Reads the floating point register in OP_*_FR. */
257#define INSN_READ_FPR_R 0x00000400
258/* Modifies coprocessor condition code. */
259#define INSN_WRITE_COND_CODE 0x00000800
260/* Reads coprocessor condition code. */
261#define INSN_READ_COND_CODE 0x00001000
262/* TLB operation. */
263#define INSN_TLB 0x00002000
264/* Reads coprocessor register other than floating point register. */
265#define INSN_COP 0x00004000
266/* Instruction loads value from memory, requiring delay. */
267#define INSN_LOAD_MEMORY_DELAY 0x00008000
268/* Instruction loads value from coprocessor, requiring delay. */
269#define INSN_LOAD_COPROC_DELAY 0x00010000
270/* Instruction has unconditional branch delay slot. */
271#define INSN_UNCOND_BRANCH_DELAY 0x00020000
272/* Instruction has conditional branch delay slot. */
273#define INSN_COND_BRANCH_DELAY 0x00040000
274/* Conditional branch likely: if branch not taken, insn nullified. */
275#define INSN_COND_BRANCH_LIKELY 0x00080000
276/* Moves to coprocessor register, requiring delay. */
277#define INSN_COPROC_MOVE_DELAY 0x00100000
278/* Loads coprocessor register from memory, requiring delay. */
279#define INSN_COPROC_MEMORY_DELAY 0x00200000
280/* Reads the HI register. */
281#define INSN_READ_HI 0x00400000
282/* Reads the LO register. */
283#define INSN_READ_LO 0x00800000
284/* Modifies the HI register. */
285#define INSN_WRITE_HI 0x01000000
286/* Modifies the LO register. */
287#define INSN_WRITE_LO 0x02000000
288/* Takes a trap (easier to keep out of delay slot). */
289#define INSN_TRAP 0x04000000
290/* Instruction stores value into memory. */
291#define INSN_STORE_MEMORY 0x08000000
292/* Instruction uses single precision floating point. */
293#define FP_S 0x10000000
294/* Instruction uses double precision floating point. */
295#define FP_D 0x20000000
296/* Instruction is part of the tx39's integer multiply family. */
297#define INSN_MULT 0x40000000
298/* Instruction synchronize shared memory. */
299#define INSN_SYNC 0x80000000
300
301/* Instruction is actually a macro. It should be ignored by the
302 disassembler, and requires special treatment by the assembler. */
303#define INSN_MACRO 0xffffffff
304
e7af610e
NC		 305/* Masks used to mark instructions to indicate which MIPS ISA level
306 they were introduced in. ISAs, as defined below, are logical
307 ORs of these bits, indicatingthat they support the instructions
308 defined at the given level. */
309
310#define INSN_ISA1 0x00000010
311#define INSN_ISA2 0x00000020
312#define INSN_ISA3 0x00000040
313#define INSN_ISA4 0x00000080
314#define INSN_ISA5 0x00000100
315#define INSN_ISA32 0x00000200
84ea6cf2 316#define INSN_ISA64 0x00000400
252b5132
RH		 317
318/* Chip specific instructions. These are bitmasks. */
e7af610e 319
252b5132 320/* MIPS R4650 instruction. */
e7af610e 321#define INSN_4650 0x00010000
252b5132 322/* LSI R4010 instruction. */
e7af610e
NC		 323#define INSN_4010 0x00020000
324/* NEC VR4100 instruction. */
bf40d919 325#define INSN_4100 0x00040000
252b5132 326/* Toshiba R3900 instruction. */
bf40d919 327#define INSN_3900 0x00080000
e7af610e 328/* 32-bit code running on a ISA3+ CPU. */
bf40d919 329#define INSN_GP32 0x00100000
e7af610e
NC		 330
331/* MIPS ISA defines, use instead of hardcoding ISA level. */
332
333#define ISA_UNKNOWN 0 /* Gas internal use. */
334#define ISA_MIPS1 (INSN_ISA1)
335#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
336#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
337#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
84ea6cf2 338#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
e7af610e 339#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
84ea6cf2 340#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
367c01af 341
156c2f8b
NC		 342/* CPU defines, use instead of hardcoding processor number. Keep this
343 in sync with bfd/archures.c in order for machine selection to work. */
e7af610e 344#define CPU_UNKNOWN 0 /* Gas internal use. */
156c2f8b
NC		 345#define CPU_R2000 2000
346#define CPU_R3000 3000
347#define CPU_R3900 3900
348#define CPU_R4000 4000
349#define CPU_R4010 4010
350#define CPU_VR4100 4100
351#define CPU_R4111 4111
352#define CPU_R4300 4300
353#define CPU_R4400 4400
354#define CPU_R4600 4600
355#define CPU_R4650 4650
356#define CPU_R5000 5000
357#define CPU_R6000 6000
358#define CPU_R8000 8000
359#define CPU_R10000 10000
360#define CPU_MIPS16 16
361#define CPU_MIPS32 32
c6c98b38 362#define CPU_MIPS32_4K 3204113 /* 32, 04, octal 'K'. */
84ea6cf2
NC		 363#define CPU_MIPS5 5
364#define CPU_MIPS64 64
c6c98b38 365#define CPU_SB1 12310201 /* octal 'SB', 01. */
156c2f8b 366
2bd7f1f3
GRK		 367/* Test for membership in an ISA including chip specific ISAs.
368 INSN is pointer to an element of the opcode table; ISA is the
369 specified ISA to test against; and CPU is the CPU specific ISA
8eaec934 370 to test, or zero if no CPU specific ISA test is desired.
87f398dd
AH		 371 The gp32 arg is set when you need to force 32-bit register usage on
372 a machine with 64-bit registers; see the documentation under -mgp32
c6c98b38 373 in the MIPS gas docs. */
2bd7f1f3 374
156c2f8b 375#define OPCODE_IS_MEMBER(insn, isa, cpu, gp32) \
e7af610e 376 ((((insn)->membership & isa) != 0 \
8eaec934
NC		 377 && ((insn)->membership & INSN_GP32 ? gp32 : 1) \
378 ) \
156c2f8b
NC		 379 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
380 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
381 || ((cpu == CPU_VR4100 || cpu == CPU_R4111) \
382 && ((insn)->membership & INSN_4100) != 0) \
156c2f8b 383 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0))
252b5132
RH		 384
385/* This is a list of macro expanded instructions.
8eaec934 386
e7af610e
NC		 387 _I appended means immediate
388 _A appended means address
389 _AB appended means address with base register
390 _D appended means 64 bit floating point constant
391 _S appended means 32 bit floating point constant. */
392
393enum
394{
395 M_ABS,
396 M_ADD_I,
397 M_ADDU_I,
398 M_AND_I,
399 M_BEQ,
400 M_BEQ_I,
401 M_BEQL_I,
402 M_BGE,
403 M_BGEL,
404 M_BGE_I,
405 M_BGEL_I,
406 M_BGEU,
407 M_BGEUL,
408 M_BGEU_I,
409 M_BGEUL_I,
410 M_BGT,
411 M_BGTL,
412 M_BGT_I,
413 M_BGTL_I,
414 M_BGTU,
415 M_BGTUL,
416 M_BGTU_I,
417 M_BGTUL_I,
418 M_BLE,
419 M_BLEL,
420 M_BLE_I,
421 M_BLEL_I,
422 M_BLEU,
423 M_BLEUL,
424 M_BLEU_I,
425 M_BLEUL_I,
426 M_BLT,
427 M_BLTL,
428 M_BLT_I,
429 M_BLTL_I,
430 M_BLTU,
431 M_BLTUL,
432 M_BLTU_I,
433 M_BLTUL_I,
434 M_BNE,
435 M_BNE_I,
436 M_BNEL_I,
437 M_DABS,
438 M_DADD_I,
439 M_DADDU_I,
440 M_DDIV_3,
441 M_DDIV_3I,
442 M_DDIVU_3,
443 M_DDIVU_3I,
444 M_DIV_3,
445 M_DIV_3I,
446 M_DIVU_3,
447 M_DIVU_3I,
448 M_DLA_AB,
449 M_DLI,
450 M_DMUL,
8eaec934 451 M_DMUL_I,
e7af610e 452 M_DMULO,
8eaec934 453 M_DMULO_I,
e7af610e 454 M_DMULOU,
8eaec934 455 M_DMULOU_I,
e7af610e
NC		 456 M_DREM_3,
457 M_DREM_3I,
458 M_DREMU_3,
459 M_DREMU_3I,
460 M_DSUB_I,
461 M_DSUBU_I,
462 M_DSUBU_I_2,
463 M_J_A,
464 M_JAL_1,
465 M_JAL_2,
466 M_JAL_A,
467 M_L_DOB,
468 M_L_DAB,
469 M_LA_AB,
470 M_LB_A,
471 M_LB_AB,
472 M_LBU_A,
473 M_LBU_AB,
474 M_LD_A,
475 M_LD_OB,
476 M_LD_AB,
477 M_LDC1_AB,
478 M_LDC2_AB,
479 M_LDC3_AB,
480 M_LDL_AB,
481 M_LDR_AB,
482 M_LH_A,
483 M_LH_AB,
484 M_LHU_A,
485 M_LHU_AB,
486 M_LI,
487 M_LI_D,
488 M_LI_DD,
489 M_LI_S,
490 M_LI_SS,
491 M_LL_AB,
492 M_LLD_AB,
493 M_LS_A,
494 M_LW_A,
495 M_LW_AB,
496 M_LWC0_A,
497 M_LWC0_AB,
498 M_LWC1_A,
499 M_LWC1_AB,
500 M_LWC2_A,
501 M_LWC2_AB,
502 M_LWC3_A,
503 M_LWC3_AB,
504 M_LWL_A,
505 M_LWL_AB,
506 M_LWR_A,
507 M_LWR_AB,
508 M_LWU_AB,
509 M_MUL,
8eaec934 510 M_MUL_I,
e7af610e 511 M_MULO,
8eaec934 512 M_MULO_I,
e7af610e 513 M_MULOU,
8eaec934 514 M_MULOU_I,
e7af610e
NC		 515 M_NOR_I,
516 M_OR_I,
517 M_REM_3,
518 M_REM_3I,
519 M_REMU_3,
520 M_REMU_3I,
521 M_ROL,
522 M_ROL_I,
523 M_ROR,
524 M_ROR_I,
525 M_S_DA,
526 M_S_DOB,
527 M_S_DAB,
528 M_S_S,
529 M_SC_AB,
530 M_SCD_AB,
531 M_SD_A,
532 M_SD_OB,
533 M_SD_AB,
534 M_SDC1_AB,
535 M_SDC2_AB,
536 M_SDC3_AB,
537 M_SDL_AB,
538 M_SDR_AB,
539 M_SEQ,
540 M_SEQ_I,
541 M_SGE,
542 M_SGE_I,
543 M_SGEU,
544 M_SGEU_I,
545 M_SGT,
546 M_SGT_I,
547 M_SGTU,
548 M_SGTU_I,
549 M_SLE,
550 M_SLE_I,
551 M_SLEU,
552 M_SLEU_I,
553 M_SLT_I,
554 M_SLTU_I,
555 M_SNE,
556 M_SNE_I,
557 M_SB_A,
558 M_SB_AB,
559 M_SH_A,
560 M_SH_AB,
561 M_SW_A,
562 M_SW_AB,
563 M_SWC0_A,
564 M_SWC0_AB,
565 M_SWC1_A,
566 M_SWC1_AB,
567 M_SWC2_A,
568 M_SWC2_AB,
569 M_SWC3_A,
570 M_SWC3_AB,
571 M_SWL_A,
572 M_SWL_AB,
573 M_SWR_A,
574 M_SWR_AB,
575 M_SUB_I,
576 M_SUBU_I,
577 M_SUBU_I_2,
578 M_TEQ_I,
579 M_TGE_I,
580 M_TGEU_I,
581 M_TLT_I,
582 M_TLTU_I,
583 M_TNE_I,
584 M_TRUNCWD,
585 M_TRUNCWS,
586 M_ULD,
587 M_ULD_A,
588 M_ULH,
589 M_ULH_A,
590 M_ULHU,
591 M_ULHU_A,
592 M_ULW,
593 M_ULW_A,
594 M_USH,
595 M_USH_A,
596 M_USW,
597 M_USW_A,
598 M_USD,
599 M_USD_A,
600 M_XOR_I,
601 M_COP0,
602 M_COP1,
603 M_COP2,
604 M_COP3,
605 M_NUM_MACROS
252b5132
RH		 606};
607
608
609/* The order of overloaded instructions matters. Label arguments and
610 register arguments look the same. Instructions that can have either
611 for arguments must apear in the correct order in this table for the
612 assembler to pick the right one. In other words, entries with
613 immediate operands must apear after the same instruction with
614 registers.
615
616 Many instructions are short hand for other instructions (i.e., The
617 jal <register> instruction is short for jalr <register>). */
618
619extern const struct mips_opcode mips_builtin_opcodes[];
620extern const int bfd_mips_num_builtin_opcodes;
621extern struct mips_opcode *mips_opcodes;
622extern int bfd_mips_num_opcodes;
623#define NUMOPCODES bfd_mips_num_opcodes
624
625\f
626/* The rest of this file adds definitions for the mips16 TinyRISC
627 processor. */
628
629/* These are the bitmasks and shift counts used for the different
630 fields in the instruction formats. Other than OP, no masks are
631 provided for the fixed portions of an instruction, since they are
632 not needed.
633
634 The I format uses IMM11.
635
636 The RI format uses RX and IMM8.
637
638 The RR format uses RX, and RY.
639
640 The RRI format uses RX, RY, and IMM5.
641
642 The RRR format uses RX, RY, and RZ.
643
644 The RRI_A format uses RX, RY, and IMM4.
645
646 The SHIFT format uses RX, RY, and SHAMT.
647
648 The I8 format uses IMM8.
649
650 The I8_MOVR32 format uses RY and REGR32.
651
652 The IR_MOV32R format uses REG32R and MOV32Z.
653
654 The I64 format uses IMM8.
655
656 The RI64 format uses RY and IMM5.
657 */
658
659#define MIPS16OP_MASK_OP 0x1f
660#define MIPS16OP_SH_OP 11
661#define MIPS16OP_MASK_IMM11 0x7ff
662#define MIPS16OP_SH_IMM11 0
663#define MIPS16OP_MASK_RX 0x7
664#define MIPS16OP_SH_RX 8
665#define MIPS16OP_MASK_IMM8 0xff
666#define MIPS16OP_SH_IMM8 0
667#define MIPS16OP_MASK_RY 0x7
668#define MIPS16OP_SH_RY 5
669#define MIPS16OP_MASK_IMM5 0x1f
670#define MIPS16OP_SH_IMM5 0
671#define MIPS16OP_MASK_RZ 0x7
672#define MIPS16OP_SH_RZ 2
673#define MIPS16OP_MASK_IMM4 0xf
674#define MIPS16OP_SH_IMM4 0
675#define MIPS16OP_MASK_REGR32 0x1f
676#define MIPS16OP_SH_REGR32 0
677#define MIPS16OP_MASK_REG32R 0x1f
678#define MIPS16OP_SH_REG32R 3
679#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
680#define MIPS16OP_MASK_MOVE32Z 0x7
681#define MIPS16OP_SH_MOVE32Z 0
682#define MIPS16OP_MASK_IMM6 0x3f
683#define MIPS16OP_SH_IMM6 5
684
685/* These are the characters which may appears in the args field of an
686 instruction. They appear in the order in which the fields appear
687 when the instruction is used. Commas and parentheses in the args
688 string are ignored when assembling, and written into the output
689 when disassembling.
690
691 "y" 3 bit register (MIPS16OP_*_RY)
692 "x" 3 bit register (MIPS16OP_*_RX)
693 "z" 3 bit register (MIPS16OP_*_RZ)
694 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
695 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
696 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
697 "0" zero register ($0)
698 "S" stack pointer ($sp or $29)
699 "P" program counter
700 "R" return address register ($ra or $31)
701 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
702 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
703 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
704 "a" 26 bit jump address
705 "e" 11 bit extension value
706 "l" register list for entry instruction
707 "L" register list for exit instruction
708
709 The remaining codes may be extended. Except as otherwise noted,
710 the full extended operand is a 16 bit signed value.
711 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
712 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
713 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
714 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
715 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
716 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
717 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
718 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
719 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
720 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
721 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
722 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
723 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
724 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
725 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
726 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
727 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
728 "q" 11 bit branch address (MIPS16OP_*_IMM11)
729 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
730 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
731 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
732 */
733
734/* For the mips16, we use the same opcode table format and a few of
735 the same flags. However, most of the flags are different. */
736
737/* Modifies the register in MIPS16OP_*_RX. */
738#define MIPS16_INSN_WRITE_X 0x00000001
739/* Modifies the register in MIPS16OP_*_RY. */
740#define MIPS16_INSN_WRITE_Y 0x00000002
741/* Modifies the register in MIPS16OP_*_RZ. */
742#define MIPS16_INSN_WRITE_Z 0x00000004
743/* Modifies the T ($24) register. */
744#define MIPS16_INSN_WRITE_T 0x00000008
745/* Modifies the SP ($29) register. */
746#define MIPS16_INSN_WRITE_SP 0x00000010
747/* Modifies the RA ($31) register. */
748#define MIPS16_INSN_WRITE_31 0x00000020
749/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
750#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
751/* Reads the register in MIPS16OP_*_RX. */
752#define MIPS16_INSN_READ_X 0x00000080
753/* Reads the register in MIPS16OP_*_RY. */
754#define MIPS16_INSN_READ_Y 0x00000100
755/* Reads the register in MIPS16OP_*_MOVE32Z. */
756#define MIPS16_INSN_READ_Z 0x00000200
757/* Reads the T ($24) register. */
758#define MIPS16_INSN_READ_T 0x00000400
759/* Reads the SP ($29) register. */
760#define MIPS16_INSN_READ_SP 0x00000800
761/* Reads the RA ($31) register. */
762#define MIPS16_INSN_READ_31 0x00001000
763/* Reads the program counter. */
764#define MIPS16_INSN_READ_PC 0x00002000
765/* Reads the general purpose register in MIPS16OP_*_REGR32. */
766#define MIPS16_INSN_READ_GPR_X 0x00004000
767/* Is a branch insn. */
768#define MIPS16_INSN_BRANCH 0x00010000
769
770/* The following flags have the same value for the mips16 opcode
771 table:
772 INSN_UNCOND_BRANCH_DELAY
773 INSN_COND_BRANCH_DELAY
774 INSN_COND_BRANCH_LIKELY (never used)
775 INSN_READ_HI
776 INSN_READ_LO
777 INSN_WRITE_HI
778 INSN_WRITE_LO
779 INSN_TRAP
780 INSN_ISA3
781 */
782
783extern const struct mips_opcode mips16_opcodes[];
784extern const int bfd_mips16_num_opcodes;
785
786#endif /* _MIPS_H_ */
GDB Binutils - Deliverables
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