Commit | Line | Data |
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252b5132 | 1 | /* mips.h. Mips opcode list for GDB, the GNU debugger. |
c3aa17e9 | 2 | Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
e407c74b | 3 | 2003, 2004, 2005, 2008, 2009, 2010, 2013 |
4f1d9bd8 | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by Ralph Campbell and OSF |
6 | Commented and modified by Ian Lance Taylor, Cygnus Support | |
7 | ||
e4e42b45 | 8 | This file is part of GDB, GAS, and the GNU binutils. |
252b5132 | 9 | |
e4e42b45 NC |
10 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
11 | them and/or modify them under the terms of the GNU General Public | |
12 | License as published by the Free Software Foundation; either version 3, | |
13 | or (at your option) any later version. | |
252b5132 | 14 | |
e4e42b45 NC |
15 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
16 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
17 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
18 | the GNU General Public License for more details. | |
252b5132 | 19 | |
e4e42b45 NC |
20 | You should have received a copy of the GNU General Public License |
21 | along with this file; see the file COPYING3. If not, write to the Free | |
22 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
23 | MA 02110-1301, USA. */ | |
252b5132 RH |
24 | |
25 | #ifndef _MIPS_H_ | |
26 | #define _MIPS_H_ | |
27 | ||
35d0a169 MR |
28 | #include "bfd.h" |
29 | ||
252b5132 RH |
30 | /* These are bit masks and shift counts to use to access the various |
31 | fields of an instruction. To retrieve the X field of an | |
32 | instruction, use the expression | |
33 | (i >> OP_SH_X) & OP_MASK_X | |
34 | To set the same field (to j), use | |
35 | i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) | |
36 | ||
37 | Make sure you use fields that are appropriate for the instruction, | |
8eaec934 | 38 | of course. |
252b5132 | 39 | |
8eaec934 | 40 | The 'i' format uses OP, RS, RT and IMMEDIATE. |
252b5132 RH |
41 | |
42 | The 'j' format uses OP and TARGET. | |
43 | ||
44 | The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. | |
45 | ||
46 | The 'b' format uses OP, RS, RT and DELTA. | |
47 | ||
48 | The floating point 'i' format uses OP, RS, RT and IMMEDIATE. | |
49 | ||
50 | The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. | |
51 | ||
52 | A breakpoint instruction uses OP, CODE and SPEC (10 bits of the | |
53 | breakpoint instruction are not defined; Kane says the breakpoint | |
54 | code field in BREAK is 20 bits; yet MIPS assemblers and debuggers | |
55 | only use ten bits). An optional two-operand form of break/sdbbp | |
4372b673 NC |
56 | allows the lower ten bits to be set too, and MIPS32 and later |
57 | architectures allow 20 bits to be set with a signal operand | |
58 | (using CODE20). | |
252b5132 | 59 | |
4372b673 | 60 | The syscall instruction uses CODE20. |
252b5132 RH |
61 | |
62 | The general coprocessor instructions use COPZ. */ | |
63 | ||
64 | #define OP_MASK_OP 0x3f | |
65 | #define OP_SH_OP 26 | |
66 | #define OP_MASK_RS 0x1f | |
67 | #define OP_SH_RS 21 | |
68 | #define OP_MASK_FR 0x1f | |
69 | #define OP_SH_FR 21 | |
70 | #define OP_MASK_FMT 0x1f | |
71 | #define OP_SH_FMT 21 | |
72 | #define OP_MASK_BCC 0x7 | |
73 | #define OP_SH_BCC 18 | |
74 | #define OP_MASK_CODE 0x3ff | |
75 | #define OP_SH_CODE 16 | |
76 | #define OP_MASK_CODE2 0x3ff | |
77 | #define OP_SH_CODE2 6 | |
78 | #define OP_MASK_RT 0x1f | |
79 | #define OP_SH_RT 16 | |
80 | #define OP_MASK_FT 0x1f | |
81 | #define OP_SH_FT 16 | |
82 | #define OP_MASK_CACHE 0x1f | |
83 | #define OP_SH_CACHE 16 | |
84 | #define OP_MASK_RD 0x1f | |
85 | #define OP_SH_RD 11 | |
86 | #define OP_MASK_FS 0x1f | |
87 | #define OP_SH_FS 11 | |
88 | #define OP_MASK_PREFX 0x1f | |
89 | #define OP_SH_PREFX 11 | |
90 | #define OP_MASK_CCC 0x7 | |
91 | #define OP_SH_CCC 8 | |
4372b673 NC |
92 | #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ |
93 | #define OP_SH_CODE20 6 | |
252b5132 RH |
94 | #define OP_MASK_SHAMT 0x1f |
95 | #define OP_SH_SHAMT 6 | |
df58fc94 RS |
96 | #define OP_MASK_EXTLSB OP_MASK_SHAMT |
97 | #define OP_SH_EXTLSB OP_SH_SHAMT | |
98 | #define OP_MASK_STYPE OP_MASK_SHAMT | |
99 | #define OP_SH_STYPE OP_SH_SHAMT | |
252b5132 RH |
100 | #define OP_MASK_FD 0x1f |
101 | #define OP_SH_FD 6 | |
102 | #define OP_MASK_TARGET 0x3ffffff | |
103 | #define OP_SH_TARGET 0 | |
104 | #define OP_MASK_COPZ 0x1ffffff | |
105 | #define OP_SH_COPZ 0 | |
106 | #define OP_MASK_IMMEDIATE 0xffff | |
107 | #define OP_SH_IMMEDIATE 0 | |
108 | #define OP_MASK_DELTA 0xffff | |
109 | #define OP_SH_DELTA 0 | |
110 | #define OP_MASK_FUNCT 0x3f | |
111 | #define OP_SH_FUNCT 0 | |
112 | #define OP_MASK_SPEC 0x3f | |
113 | #define OP_SH_SPEC 0 | |
4372b673 NC |
114 | #define OP_SH_LOCC 8 /* FP condition code. */ |
115 | #define OP_SH_HICC 18 /* FP condition code. */ | |
252b5132 | 116 | #define OP_MASK_CC 0x7 |
4372b673 NC |
117 | #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ |
118 | #define OP_MASK_COP1NORM 0x1 /* a single bit. */ | |
119 | #define OP_SH_COP1SPEC 21 /* COP1 encodings. */ | |
252b5132 RH |
120 | #define OP_MASK_COP1SPEC 0xf |
121 | #define OP_MASK_COP1SCLR 0x4 | |
122 | #define OP_MASK_COP1CMP 0x3 | |
123 | #define OP_SH_COP1CMP 4 | |
4372b673 | 124 | #define OP_SH_FORMAT 21 /* FP short format field. */ |
252b5132 RH |
125 | #define OP_MASK_FORMAT 0x7 |
126 | #define OP_SH_TRUE 16 | |
127 | #define OP_MASK_TRUE 0x1 | |
128 | #define OP_SH_GE 17 | |
129 | #define OP_MASK_GE 0x01 | |
130 | #define OP_SH_UNSIGNED 16 | |
131 | #define OP_MASK_UNSIGNED 0x1 | |
132 | #define OP_SH_HINT 16 | |
133 | #define OP_MASK_HINT 0x1f | |
4372b673 | 134 | #define OP_SH_MMI 0 /* Multimedia (parallel) op. */ |
8eaec934 | 135 | #define OP_MASK_MMI 0x3f |
252b5132 RH |
136 | #define OP_SH_MMISUB 6 |
137 | #define OP_MASK_MMISUB 0x1f | |
4372b673 | 138 | #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ |
252b5132 | 139 | #define OP_SH_PERFREG 1 |
4372b673 NC |
140 | #define OP_SH_SEL 0 /* Coprocessor select field. */ |
141 | #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ | |
142 | #define OP_SH_CODE19 6 /* 19 bit wait code. */ | |
143 | #define OP_MASK_CODE19 0x7ffff | |
deec1734 CD |
144 | #define OP_SH_ALN 21 |
145 | #define OP_MASK_ALN 0x7 | |
146 | #define OP_SH_VSEL 21 | |
147 | #define OP_MASK_VSEL 0x1f | |
9752cf1b RS |
148 | #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits, |
149 | but 0x8-0xf don't select bytes. */ | |
150 | #define OP_SH_VECBYTE 22 | |
151 | #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ | |
152 | #define OP_SH_VECALIGN 21 | |
af7ee8bf CD |
153 | #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */ |
154 | #define OP_SH_INSMSB 11 | |
155 | #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ | |
156 | #define OP_SH_EXTMSBD 11 | |
deec1734 | 157 | |
93c34b9b CF |
158 | /* MIPS DSP ASE */ |
159 | #define OP_SH_DSPACC 11 | |
160 | #define OP_MASK_DSPACC 0x3 | |
161 | #define OP_SH_DSPACC_S 21 | |
162 | #define OP_MASK_DSPACC_S 0x3 | |
163 | #define OP_SH_DSPSFT 20 | |
164 | #define OP_MASK_DSPSFT 0x3f | |
165 | #define OP_SH_DSPSFT_7 19 | |
166 | #define OP_MASK_DSPSFT_7 0x7f | |
167 | #define OP_SH_SA3 21 | |
168 | #define OP_MASK_SA3 0x7 | |
169 | #define OP_SH_SA4 21 | |
170 | #define OP_MASK_SA4 0xf | |
171 | #define OP_SH_IMM8 16 | |
172 | #define OP_MASK_IMM8 0xff | |
173 | #define OP_SH_IMM10 16 | |
174 | #define OP_MASK_IMM10 0x3ff | |
175 | #define OP_SH_WRDSP 11 | |
176 | #define OP_MASK_WRDSP 0x3f | |
177 | #define OP_SH_RDDSP 16 | |
178 | #define OP_MASK_RDDSP 0x3f | |
8b082fb1 TS |
179 | #define OP_SH_BP 11 |
180 | #define OP_MASK_BP 0x3 | |
93c34b9b | 181 | |
089b39de CF |
182 | /* MIPS MT ASE */ |
183 | #define OP_SH_MT_U 5 | |
184 | #define OP_MASK_MT_U 0x1 | |
185 | #define OP_SH_MT_H 4 | |
186 | #define OP_MASK_MT_H 0x1 | |
187 | #define OP_SH_MTACC_T 18 | |
188 | #define OP_MASK_MTACC_T 0x3 | |
189 | #define OP_SH_MTACC_D 13 | |
190 | #define OP_MASK_MTACC_D 0x3 | |
191 | ||
dec0624d MR |
192 | /* MIPS MCU ASE */ |
193 | #define OP_MASK_3BITPOS 0x7 | |
194 | #define OP_SH_3BITPOS 12 | |
195 | #define OP_MASK_OFFSET12 0xfff | |
196 | #define OP_SH_OFFSET12 0 | |
197 | ||
640c0ccd CD |
198 | #define OP_OP_COP0 0x10 |
199 | #define OP_OP_COP1 0x11 | |
200 | #define OP_OP_COP2 0x12 | |
201 | #define OP_OP_COP3 0x13 | |
202 | #define OP_OP_LWC1 0x31 | |
203 | #define OP_OP_LWC2 0x32 | |
204 | #define OP_OP_LWC3 0x33 /* a.k.a. pref */ | |
205 | #define OP_OP_LDC1 0x35 | |
206 | #define OP_OP_LDC2 0x36 | |
207 | #define OP_OP_LDC3 0x37 /* a.k.a. ld */ | |
208 | #define OP_OP_SWC1 0x39 | |
209 | #define OP_OP_SWC2 0x3a | |
210 | #define OP_OP_SWC3 0x3b | |
211 | #define OP_OP_SDC1 0x3d | |
212 | #define OP_OP_SDC2 0x3e | |
213 | #define OP_OP_SDC3 0x3f /* a.k.a. sd */ | |
214 | ||
b015e599 AP |
215 | /* MIPS VIRT ASE */ |
216 | #define OP_MASK_CODE10 0x3ff | |
217 | #define OP_SH_CODE10 11 | |
218 | ||
deec1734 CD |
219 | /* Values in the 'VSEL' field. */ |
220 | #define MDMX_FMTSEL_IMM_QH 0x1d | |
221 | #define MDMX_FMTSEL_IMM_OB 0x1e | |
222 | #define MDMX_FMTSEL_VEC_QH 0x15 | |
223 | #define MDMX_FMTSEL_VEC_OB 0x16 | |
4372b673 | 224 | |
9bcd4f99 TS |
225 | /* UDI */ |
226 | #define OP_SH_UDI1 6 | |
227 | #define OP_MASK_UDI1 0x1f | |
228 | #define OP_SH_UDI2 6 | |
229 | #define OP_MASK_UDI2 0x3ff | |
230 | #define OP_SH_UDI3 6 | |
231 | #define OP_MASK_UDI3 0x7fff | |
232 | #define OP_SH_UDI4 6 | |
233 | #define OP_MASK_UDI4 0xfffff | |
234 | ||
bb35fb24 NC |
235 | /* Octeon */ |
236 | #define OP_SH_BBITIND 16 | |
237 | #define OP_MASK_BBITIND 0x1f | |
238 | #define OP_SH_CINSPOS 6 | |
239 | #define OP_MASK_CINSPOS 0x1f | |
240 | #define OP_SH_CINSLM1 11 | |
241 | #define OP_MASK_CINSLM1 0x1f | |
dd3cbb7e NC |
242 | #define OP_SH_SEQI 6 |
243 | #define OP_MASK_SEQI 0x3ff | |
bb35fb24 | 244 | |
98675402 RS |
245 | /* Loongson */ |
246 | #define OP_SH_OFFSET_A 6 | |
247 | #define OP_MASK_OFFSET_A 0xff | |
248 | #define OP_SH_OFFSET_B 3 | |
249 | #define OP_MASK_OFFSET_B 0xff | |
250 | #define OP_SH_OFFSET_C 6 | |
251 | #define OP_MASK_OFFSET_C 0x1ff | |
252 | #define OP_SH_RZ 0 | |
253 | #define OP_MASK_RZ 0x1f | |
254 | #define OP_SH_FZ 0 | |
255 | #define OP_MASK_FZ 0x1f | |
256 | ||
df58fc94 RS |
257 | /* Every MICROMIPSOP_X definition requires a corresponding OP_X |
258 | definition, and vice versa. This simplifies various parts | |
259 | of the operand handling in GAS. The fields below only exist | |
260 | in the microMIPS encoding, so define each one to have an empty | |
261 | range. */ | |
df58fc94 RS |
262 | #define OP_MASK_TRAP 0 |
263 | #define OP_SH_TRAP 0 | |
df58fc94 RS |
264 | #define OP_MASK_OFFSET10 0 |
265 | #define OP_SH_OFFSET10 0 | |
266 | #define OP_MASK_RS3 0 | |
267 | #define OP_SH_RS3 0 | |
268 | #define OP_MASK_MB 0 | |
269 | #define OP_SH_MB 0 | |
270 | #define OP_MASK_MC 0 | |
271 | #define OP_SH_MC 0 | |
272 | #define OP_MASK_MD 0 | |
273 | #define OP_SH_MD 0 | |
274 | #define OP_MASK_ME 0 | |
275 | #define OP_SH_ME 0 | |
276 | #define OP_MASK_MF 0 | |
277 | #define OP_SH_MF 0 | |
278 | #define OP_MASK_MG 0 | |
279 | #define OP_SH_MG 0 | |
280 | #define OP_MASK_MH 0 | |
281 | #define OP_SH_MH 0 | |
282 | #define OP_MASK_MI 0 | |
283 | #define OP_SH_MI 0 | |
284 | #define OP_MASK_MJ 0 | |
285 | #define OP_SH_MJ 0 | |
286 | #define OP_MASK_ML 0 | |
287 | #define OP_SH_ML 0 | |
288 | #define OP_MASK_MM 0 | |
289 | #define OP_SH_MM 0 | |
290 | #define OP_MASK_MN 0 | |
291 | #define OP_SH_MN 0 | |
292 | #define OP_MASK_MP 0 | |
293 | #define OP_SH_MP 0 | |
294 | #define OP_MASK_MQ 0 | |
295 | #define OP_SH_MQ 0 | |
296 | #define OP_MASK_IMMA 0 | |
297 | #define OP_SH_IMMA 0 | |
298 | #define OP_MASK_IMMB 0 | |
299 | #define OP_SH_IMMB 0 | |
300 | #define OP_MASK_IMMC 0 | |
301 | #define OP_SH_IMMC 0 | |
302 | #define OP_MASK_IMMF 0 | |
303 | #define OP_SH_IMMF 0 | |
304 | #define OP_MASK_IMMG 0 | |
305 | #define OP_SH_IMMG 0 | |
306 | #define OP_MASK_IMMH 0 | |
307 | #define OP_SH_IMMH 0 | |
308 | #define OP_MASK_IMMI 0 | |
309 | #define OP_SH_IMMI 0 | |
310 | #define OP_MASK_IMMJ 0 | |
311 | #define OP_SH_IMMJ 0 | |
312 | #define OP_MASK_IMML 0 | |
313 | #define OP_SH_IMML 0 | |
314 | #define OP_MASK_IMMM 0 | |
315 | #define OP_SH_IMMM 0 | |
316 | #define OP_MASK_IMMN 0 | |
317 | #define OP_SH_IMMN 0 | |
318 | #define OP_MASK_IMMO 0 | |
319 | #define OP_SH_IMMO 0 | |
320 | #define OP_MASK_IMMP 0 | |
321 | #define OP_SH_IMMP 0 | |
322 | #define OP_MASK_IMMQ 0 | |
323 | #define OP_SH_IMMQ 0 | |
324 | #define OP_MASK_IMMU 0 | |
325 | #define OP_SH_IMMU 0 | |
326 | #define OP_MASK_IMMW 0 | |
327 | #define OP_SH_IMMW 0 | |
328 | #define OP_MASK_IMMX 0 | |
329 | #define OP_SH_IMMX 0 | |
330 | #define OP_MASK_IMMY 0 | |
331 | #define OP_SH_IMMY 0 | |
332 | ||
7f3c4072 CM |
333 | /* Enhanced VA Scheme */ |
334 | #define OP_SH_EVAOFFSET 7 | |
335 | #define OP_MASK_EVAOFFSET 0x1ff | |
336 | ||
252b5132 RH |
337 | /* This structure holds information for a particular instruction. */ |
338 | ||
339 | struct mips_opcode | |
340 | { | |
341 | /* The name of the instruction. */ | |
342 | const char *name; | |
343 | /* A string describing the arguments for this instruction. */ | |
344 | const char *args; | |
345 | /* The basic opcode for the instruction. When assembling, this | |
346 | opcode is modified by the arguments to produce the actual opcode | |
347 | that is used. If pinfo is INSN_MACRO, then this is 0. */ | |
348 | unsigned long match; | |
349 | /* If pinfo is not INSN_MACRO, then this is a bit mask for the | |
350 | relevant portions of the opcode when disassembling. If the | |
351 | actual opcode anded with the match field equals the opcode field, | |
352 | then we have found the correct instruction. If pinfo is | |
353 | INSN_MACRO, then this field is the macro identifier. */ | |
354 | unsigned long mask; | |
355 | /* For a macro, this is INSN_MACRO. Otherwise, it is a collection | |
356 | of bits describing the instruction, notably any relevant hazard | |
357 | information. */ | |
358 | unsigned long pinfo; | |
dc9a9f39 FF |
359 | /* A collection of additional bits describing the instruction. */ |
360 | unsigned long pinfo2; | |
252b5132 RH |
361 | /* A collection of bits describing the instruction sets of which this |
362 | instruction or macro is a member. */ | |
363 | unsigned long membership; | |
d301a56b RS |
364 | /* A collection of bits describing the ASE of which this instruction |
365 | or macro is a member. */ | |
366 | unsigned long ase; | |
35d0a169 MR |
367 | /* A collection of bits describing the instruction sets of which this |
368 | instruction or macro is not a member. */ | |
369 | unsigned long exclusions; | |
252b5132 RH |
370 | }; |
371 | ||
27abff54 | 372 | /* These are the characters which may appear in the args field of an |
252b5132 RH |
373 | instruction. They appear in the order in which the fields appear |
374 | when the instruction is used. Commas and parentheses in the args | |
375 | string are ignored when assembling, and written into the output | |
376 | when disassembling. | |
377 | ||
378 | Each of these characters corresponds to a mask field defined above. | |
379 | ||
de9a3e51 | 380 | "1" 5 bit sync type (OP_*_SHAMT) |
252b5132 RH |
381 | "<" 5 bit shift amount (OP_*_SHAMT) |
382 | ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) | |
383 | "a" 26 bit target address (OP_*_TARGET) | |
384 | "b" 5 bit base register (OP_*_RS) | |
385 | "c" 10 bit breakpoint code (OP_*_CODE) | |
386 | "d" 5 bit destination register specifier (OP_*_RD) | |
387 | "h" 5 bit prefx hint (OP_*_PREFX) | |
388 | "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) | |
389 | "j" 16 bit signed immediate (OP_*_DELTA) | |
390 | "k" 5 bit cache opcode in target register position (OP_*_CACHE) | |
9752cf1b | 391 | Also used for immediate operands in vr5400 vector insns. |
252b5132 RH |
392 | "o" 16 bit signed offset (OP_*_DELTA) |
393 | "p" 16 bit PC relative branch target address (OP_*_DELTA) | |
394 | "q" 10 bit extra breakpoint code (OP_*_CODE2) | |
395 | "r" 5 bit same register used as both source and target (OP_*_RS) | |
396 | "s" 5 bit source register specifier (OP_*_RS) | |
397 | "t" 5 bit target register (OP_*_RT) | |
398 | "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) | |
399 | "v" 5 bit same register used as both source and destination (OP_*_RS) | |
400 | "w" 5 bit same register used as both target and destination (OP_*_RT) | |
4372b673 NC |
401 | "U" 5 bit same destination register in both OP_*_RD and OP_*_RT |
402 | (used by clo and clz) | |
252b5132 | 403 | "C" 25 bit coprocessor function code (OP_*_COPZ) |
4372b673 NC |
404 | "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) |
405 | "J" 19 bit wait function code (OP_*_CODE19) | |
252b5132 RH |
406 | "x" accept and ignore register name |
407 | "z" must be zero register | |
af7ee8bf | 408 | "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) |
ef0ee844 | 409 | "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes |
df58fc94 RS |
410 | LSB (OP_*_SHAMT; OP_*_EXTLSB or OP_*_STYPE may be used for |
411 | microMIPS compatibility). | |
071742cf | 412 | Enforces: 0 <= pos < 32. |
ef0ee844 | 413 | "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). |
5f74bc13 | 414 | Requires that "+A" or "+E" occur first to set position. |
071742cf | 415 | Enforces: 0 < (pos+size) <= 32. |
ef0ee844 | 416 | "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). |
5f74bc13 | 417 | Requires that "+A" or "+E" occur first to set position. |
071742cf | 418 | Enforces: 0 < (pos+size) <= 32. |
5f74bc13 CD |
419 | (Also used by "dext" w/ different limits, but limits for |
420 | that are checked by the M_DEXT macro.) | |
ef0ee844 | 421 | "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). |
5f74bc13 | 422 | Enforces: 32 <= pos < 64. |
ef0ee844 | 423 | "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). |
5f74bc13 CD |
424 | Requires that "+A" or "+E" occur first to set position. |
425 | Enforces: 32 < (pos+size) <= 64. | |
426 | "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). | |
427 | Requires that "+A" or "+E" occur first to set position. | |
428 | Enforces: 32 < (pos+size) <= 64. | |
429 | "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD). | |
430 | Requires that "+A" or "+E" occur first to set position. | |
431 | Enforces: 32 < (pos+size) <= 64. | |
252b5132 RH |
432 | |
433 | Floating point instructions: | |
434 | "D" 5 bit destination register (OP_*_FD) | |
435 | "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) | |
436 | "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) | |
437 | "S" 5 bit fs source 1 register (OP_*_FS) | |
438 | "T" 5 bit ft source 2 register (OP_*_FT) | |
439 | "R" 5 bit fr source 3 register (OP_*_FR) | |
440 | "V" 5 bit same register used as floating source and destination (OP_*_FS) | |
441 | "W" 5 bit same register used as floating target and destination (OP_*_FT) | |
442 | ||
443 | Coprocessor instructions: | |
444 | "E" 5 bit target register (OP_*_RT) | |
445 | "G" 5 bit destination register (OP_*_RD) | |
8ff529d8 | 446 | "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) |
252b5132 | 447 | "P" 5 bit performance-monitor register (OP_*_PERFREG) |
9752cf1b RS |
448 | "e" 5 bit vector register byte specifier (OP_*_VECBYTE) |
449 | "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) | |
450 | see also "k" above | |
bbcc0807 CD |
451 | "+D" Combined destination register ("G") and sel ("H") for CP0 ops, |
452 | for pretty-printing in disassembly only. | |
252b5132 RH |
453 | |
454 | Macro instructions: | |
455 | "A" General 32 bit expression | |
5f74bc13 CD |
456 | "I" 32 bit immediate (value placed in imm_expr). |
457 | "+I" 32 bit immediate (value placed in imm2_expr). | |
252b5132 RH |
458 | "F" 64 bit floating point constant in .rdata |
459 | "L" 64 bit floating point constant in .lit8 | |
460 | "f" 32 bit floating point constant | |
461 | "l" 32 bit floating point constant in .lit4 | |
462 | ||
deec1734 CD |
463 | MDMX instruction operands (note that while these use the FP register |
464 | fields, they accept both $fN and $vN names for the registers): | |
465 | "O" MDMX alignment offset (OP_*_ALN) | |
466 | "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT) | |
467 | "X" MDMX destination register (OP_*_FD) | |
468 | "Y" MDMX source register (OP_*_FS) | |
469 | "Z" MDMX source register (OP_*_FT) | |
470 | ||
93c34b9b | 471 | DSP ASE usage: |
8b082fb1 | 472 | "2" 2 bit unsigned immediate for byte align (OP_*_BP) |
93c34b9b CF |
473 | "3" 3 bit unsigned immediate (OP_*_SA3) |
474 | "4" 4 bit unsigned immediate (OP_*_SA4) | |
475 | "5" 8 bit unsigned immediate (OP_*_IMM8) | |
476 | "6" 5 bit unsigned immediate (OP_*_RS) | |
477 | "7" 2 bit dsp accumulator register (OP_*_DSPACC) | |
478 | "8" 6 bit unsigned immediate (OP_*_WRDSP) | |
479 | "9" 2 bit dsp accumulator register (OP_*_DSPACC_S) | |
480 | "0" 6 bit signed immediate (OP_*_DSPSFT) | |
481 | ":" 7 bit signed immediate (OP_*_DSPSFT_7) | |
482 | "'" 6 bit unsigned immediate (OP_*_RDDSP) | |
483 | "@" 10 bit signed immediate (OP_*_IMM10) | |
484 | ||
089b39de | 485 | MT ASE usage: |
a9e24354 TS |
486 | "!" 1 bit usermode flag (OP_*_MT_U) |
487 | "$" 1 bit load high flag (OP_*_MT_H) | |
089b39de CF |
488 | "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) |
489 | "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) | |
490 | "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) | |
491 | "+t" 5 bit coprocessor 0 destination register (OP_*_RT) | |
492 | "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only | |
493 | ||
dec0624d MR |
494 | MCU ASE usage: |
495 | "~" 12 bit offset (OP_*_OFFSET12) | |
496 | "\" 3 bit position for aset and aclr (OP_*_3BITPOS) | |
497 | ||
b015e599 AP |
498 | VIRT ASE usage: |
499 | "+J" 10-bit hypcall code (OP_*CODE10) | |
500 | ||
9bcd4f99 TS |
501 | UDI immediates: |
502 | "+1" UDI immediate bits 6-10 | |
503 | "+2" UDI immediate bits 6-15 | |
504 | "+3" UDI immediate bits 6-20 | |
505 | "+4" UDI immediate bits 6-25 | |
506 | ||
bb35fb24 NC |
507 | Octeon: |
508 | "+x" Bit index field of bbit. Enforces: 0 <= index < 32. | |
509 | "+X" Bit index field of bbit aliasing bbit32. Matches if 32 <= index < 64, | |
510 | otherwise skips to next candidate. | |
511 | "+p" Position field of cins/cins32/exts/exts32. Enforces 0 <= pos < 32. | |
512 | "+P" Position field of cins/exts aliasing cins32/exts32. Matches if | |
513 | 32 <= pos < 64, otherwise skips to next candidate. | |
dd3cbb7e | 514 | "+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512. |
bb35fb24 NC |
515 | "+s" Length-minus-one field of cins/exts. Enforces: 0 <= lenm1 < 32. |
516 | "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing | |
517 | cint32/exts32. Enforces non-negative value and that | |
518 | pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous | |
519 | position field is "+p" or "+P". | |
520 | ||
1bec78e9 RS |
521 | Loongson-3A: |
522 | "+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A) | |
523 | "+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B) | |
524 | "+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C) | |
525 | "+z" 5-bit rz register (OP_*_RZ) | |
526 | "+Z" 5-bit fz register (OP_*_FZ) | |
527 | ||
7f3c4072 CM |
528 | Enhanced VA Scheme: |
529 | "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET) | |
530 | ||
252b5132 RH |
531 | Other: |
532 | "()" parens surrounding optional value | |
533 | "," separates operands | |
9752cf1b | 534 | "[]" brackets around index for vector-op scalar operand specifier (vr5400) |
af7ee8bf | 535 | "+" Start of extension sequence. |
252b5132 RH |
536 | |
537 | Characters used so far, for quick reference when adding more: | |
de9a3e51 | 538 | "1234567890" |
dec0624d | 539 | "%[]<>(),+:'@!$*&\~" |
af7ee8bf | 540 | "ABCDEFGHIJKLMNOPQRSTUVWXYZ" |
089b39de | 541 | "abcdefghijklopqrstuvwxz" |
af7ee8bf CD |
542 | |
543 | Extension character sequences used so far ("+" followed by the | |
544 | following), for quick reference when adding more: | |
9bcd4f99 | 545 | "1234" |
b015e599 | 546 | "ABCDEFGHIJPQSTXZ" |
7f3c4072 | 547 | "abcjpstxz" |
252b5132 RH |
548 | */ |
549 | ||
550 | /* These are the bits which may be set in the pinfo field of an | |
551 | instructions, if it is not equal to INSN_MACRO. */ | |
552 | ||
553 | /* Modifies the general purpose register in OP_*_RD. */ | |
554 | #define INSN_WRITE_GPR_D 0x00000001 | |
555 | /* Modifies the general purpose register in OP_*_RT. */ | |
556 | #define INSN_WRITE_GPR_T 0x00000002 | |
557 | /* Modifies general purpose register 31. */ | |
558 | #define INSN_WRITE_GPR_31 0x00000004 | |
559 | /* Modifies the floating point register in OP_*_FD. */ | |
560 | #define INSN_WRITE_FPR_D 0x00000008 | |
561 | /* Modifies the floating point register in OP_*_FS. */ | |
562 | #define INSN_WRITE_FPR_S 0x00000010 | |
563 | /* Modifies the floating point register in OP_*_FT. */ | |
564 | #define INSN_WRITE_FPR_T 0x00000020 | |
565 | /* Reads the general purpose register in OP_*_RS. */ | |
566 | #define INSN_READ_GPR_S 0x00000040 | |
567 | /* Reads the general purpose register in OP_*_RT. */ | |
568 | #define INSN_READ_GPR_T 0x00000080 | |
569 | /* Reads the floating point register in OP_*_FS. */ | |
570 | #define INSN_READ_FPR_S 0x00000100 | |
571 | /* Reads the floating point register in OP_*_FT. */ | |
572 | #define INSN_READ_FPR_T 0x00000200 | |
573 | /* Reads the floating point register in OP_*_FR. */ | |
574 | #define INSN_READ_FPR_R 0x00000400 | |
575 | /* Modifies coprocessor condition code. */ | |
576 | #define INSN_WRITE_COND_CODE 0x00000800 | |
577 | /* Reads coprocessor condition code. */ | |
578 | #define INSN_READ_COND_CODE 0x00001000 | |
579 | /* TLB operation. */ | |
580 | #define INSN_TLB 0x00002000 | |
581 | /* Reads coprocessor register other than floating point register. */ | |
582 | #define INSN_COP 0x00004000 | |
583 | /* Instruction loads value from memory, requiring delay. */ | |
584 | #define INSN_LOAD_MEMORY_DELAY 0x00008000 | |
585 | /* Instruction loads value from coprocessor, requiring delay. */ | |
586 | #define INSN_LOAD_COPROC_DELAY 0x00010000 | |
587 | /* Instruction has unconditional branch delay slot. */ | |
588 | #define INSN_UNCOND_BRANCH_DELAY 0x00020000 | |
589 | /* Instruction has conditional branch delay slot. */ | |
590 | #define INSN_COND_BRANCH_DELAY 0x00040000 | |
591 | /* Conditional branch likely: if branch not taken, insn nullified. */ | |
592 | #define INSN_COND_BRANCH_LIKELY 0x00080000 | |
593 | /* Moves to coprocessor register, requiring delay. */ | |
594 | #define INSN_COPROC_MOVE_DELAY 0x00100000 | |
595 | /* Loads coprocessor register from memory, requiring delay. */ | |
596 | #define INSN_COPROC_MEMORY_DELAY 0x00200000 | |
597 | /* Reads the HI register. */ | |
598 | #define INSN_READ_HI 0x00400000 | |
599 | /* Reads the LO register. */ | |
600 | #define INSN_READ_LO 0x00800000 | |
601 | /* Modifies the HI register. */ | |
602 | #define INSN_WRITE_HI 0x01000000 | |
603 | /* Modifies the LO register. */ | |
604 | #define INSN_WRITE_LO 0x02000000 | |
bcd530a7 RS |
605 | /* Not to be placed in a branch delay slot, either architecturally |
606 | or for ease of handling (such as with instructions that take a trap). */ | |
607 | #define INSN_NO_DELAY_SLOT 0x04000000 | |
252b5132 RH |
608 | /* Instruction stores value into memory. */ |
609 | #define INSN_STORE_MEMORY 0x08000000 | |
610 | /* Instruction uses single precision floating point. */ | |
611 | #define FP_S 0x10000000 | |
612 | /* Instruction uses double precision floating point. */ | |
613 | #define FP_D 0x20000000 | |
614 | /* Instruction is part of the tx39's integer multiply family. */ | |
615 | #define INSN_MULT 0x40000000 | |
2b0c8b40 MR |
616 | /* Modifies the general purpose register in MICROMIPSOP_*_RS. */ |
617 | #define INSN_WRITE_GPR_S 0x80000000 | |
d0799671 AN |
618 | /* Instruction is actually a macro. It should be ignored by the |
619 | disassembler, and requires special treatment by the assembler. */ | |
620 | #define INSN_MACRO 0xffffffff | |
dc9a9f39 FF |
621 | |
622 | /* These are the bits which may be set in the pinfo2 field of an | |
623 | instruction. */ | |
624 | ||
625 | /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ | |
239cb185 | 626 | #define INSN2_ALIAS 0x00000001 |
dc9a9f39 | 627 | /* Instruction reads MDMX accumulator. */ |
239cb185 | 628 | #define INSN2_READ_MDMX_ACC 0x00000002 |
dc9a9f39 | 629 | /* Instruction writes MDMX accumulator. */ |
239cb185 | 630 | #define INSN2_WRITE_MDMX_ACC 0x00000004 |
d0799671 AN |
631 | /* Macro uses single-precision floating-point instructions. This should |
632 | only be set for macros. For instructions, FP_S in pinfo carries the | |
633 | same information. */ | |
634 | #define INSN2_M_FP_S 0x00000008 | |
635 | /* Macro uses double-precision floating-point instructions. This should | |
636 | only be set for macros. For instructions, FP_D in pinfo carries the | |
637 | same information. */ | |
638 | #define INSN2_M_FP_D 0x00000010 | |
98675402 RS |
639 | /* Modifies the general purpose register in OP_*_RZ. */ |
640 | #define INSN2_WRITE_GPR_Z 0x00000020 | |
641 | /* Modifies the floating point register in OP_*_FZ. */ | |
642 | #define INSN2_WRITE_FPR_Z 0x00000040 | |
643 | /* Reads the general purpose register in OP_*_RZ. */ | |
644 | #define INSN2_READ_GPR_Z 0x00000080 | |
645 | /* Reads the floating point register in OP_*_FZ. */ | |
646 | #define INSN2_READ_FPR_Z 0x00000100 | |
647 | /* Reads the general purpose register in OP_*_RD. */ | |
648 | #define INSN2_READ_GPR_D 0x00000200 | |
649 | ||
252b5132 | 650 | |
df58fc94 RS |
651 | /* Instruction has a branch delay slot that requires a 16-bit instruction. */ |
652 | #define INSN2_BRANCH_DELAY_16BIT 0x00000400 | |
653 | /* Instruction has a branch delay slot that requires a 32-bit instruction. */ | |
654 | #define INSN2_BRANCH_DELAY_32BIT 0x00000800 | |
df58fc94 | 655 | /* Reads the floating point register in MICROMIPSOP_*_FD. */ |
2b0c8b40 MR |
656 | #define INSN2_READ_FPR_D 0x00001000 |
657 | /* Modifies the general purpose register in MICROMIPSOP_*_MB. */ | |
658 | #define INSN2_WRITE_GPR_MB 0x00002000 | |
659 | /* Reads the general purpose register in MICROMIPSOP_*_MC. */ | |
660 | #define INSN2_READ_GPR_MC 0x00004000 | |
661 | /* Reads/writes the general purpose register in MICROMIPSOP_*_MD. */ | |
662 | #define INSN2_MOD_GPR_MD 0x00008000 | |
663 | /* Reads the general purpose register in MICROMIPSOP_*_ME. */ | |
664 | #define INSN2_READ_GPR_ME 0x00010000 | |
665 | /* Reads/writes the general purpose register in MICROMIPSOP_*_MF. */ | |
666 | #define INSN2_MOD_GPR_MF 0x00020000 | |
667 | /* Reads the general purpose register in MICROMIPSOP_*_MG. */ | |
668 | #define INSN2_READ_GPR_MG 0x00040000 | |
669 | /* Reads the general purpose register in MICROMIPSOP_*_MJ. */ | |
670 | #define INSN2_READ_GPR_MJ 0x00080000 | |
671 | /* Modifies the general purpose register in MICROMIPSOP_*_MJ. */ | |
672 | #define INSN2_WRITE_GPR_MJ 0x00100000 | |
673 | /* Reads the general purpose register in MICROMIPSOP_*_MP. */ | |
674 | #define INSN2_READ_GPR_MP 0x00200000 | |
675 | /* Modifies the general purpose register in MICROMIPSOP_*_MP. */ | |
676 | #define INSN2_WRITE_GPR_MP 0x00400000 | |
677 | /* Reads the general purpose register in MICROMIPSOP_*_MQ. */ | |
678 | #define INSN2_READ_GPR_MQ 0x00800000 | |
df58fc94 | 679 | /* Reads/Writes the stack pointer ($29). */ |
2b0c8b40 | 680 | #define INSN2_MOD_SP 0x01000000 |
df58fc94 | 681 | /* Reads the RA ($31) register. */ |
2b0c8b40 | 682 | #define INSN2_READ_GPR_31 0x02000000 |
df58fc94 | 683 | /* Reads the global pointer ($28). */ |
2b0c8b40 | 684 | #define INSN2_READ_GP 0x04000000 |
df58fc94 | 685 | /* Reads the program counter ($pc). */ |
2b0c8b40 | 686 | #define INSN2_READ_PC 0x08000000 |
df58fc94 | 687 | /* Is an unconditional branch insn. */ |
2b0c8b40 | 688 | #define INSN2_UNCOND_BRANCH 0x10000000 |
df58fc94 | 689 | /* Is a conditional branch insn. */ |
2b0c8b40 MR |
690 | #define INSN2_COND_BRANCH 0x20000000 |
691 | /* Modifies the general purpose registers in MICROMIPSOP_*_MH/I. */ | |
692 | #define INSN2_WRITE_GPR_MHI 0x40000000 | |
693 | /* Reads the general purpose registers in MICROMIPSOP_*_MM/N. */ | |
694 | #define INSN2_READ_GPR_MMN 0x80000000 | |
df58fc94 | 695 | |
e7af610e | 696 | /* Masks used to mark instructions to indicate which MIPS ISA level |
56950294 MS |
697 | they were introduced in. INSN_ISA_MASK masks an enumeration that |
698 | specifies the base ISA level(s). The remainder of a 32-bit | |
699 | word constructed using these macros is a bitmask of the remaining | |
700 | INSN_* values below. */ | |
701 | ||
702 | #define INSN_ISA_MASK 0x0000000ful | |
703 | ||
704 | /* We cannot start at zero due to ISA_UNKNOWN below. */ | |
705 | #define INSN_ISA1 1 | |
706 | #define INSN_ISA2 2 | |
707 | #define INSN_ISA3 3 | |
708 | #define INSN_ISA4 4 | |
709 | #define INSN_ISA5 5 | |
710 | #define INSN_ISA32 6 | |
711 | #define INSN_ISA32R2 7 | |
712 | #define INSN_ISA64 8 | |
713 | #define INSN_ISA64R2 9 | |
714 | /* Below this point the INSN_* values correspond to combinations of ISAs. | |
715 | They are only for use in the opcodes table to indicate membership of | |
716 | a combination of ISAs that cannot be expressed using the usual inclusion | |
717 | ordering on the above INSN_* values. */ | |
718 | #define INSN_ISA3_32 10 | |
719 | #define INSN_ISA3_32R2 11 | |
720 | #define INSN_ISA4_32 12 | |
721 | #define INSN_ISA4_32R2 13 | |
722 | #define INSN_ISA5_32R2 14 | |
723 | ||
724 | /* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through | |
725 | INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2, | |
726 | this table describes whether at least one of the ISAs described by X | |
727 | is/are implemented by ISA Y. (Think of Y as the ISA level supported by | |
728 | a particular core and X as the ISA level(s) at which a certain instruction | |
729 | is defined.) The ISA(s) described by X is/are implemented by Y iff | |
730 | (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1 | |
731 | is non-zero. */ | |
732 | static const unsigned int mips_isa_table[] = | |
733 | { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff }; | |
252b5132 | 734 | |
e6429699 | 735 | /* Masks used for Chip specific instructions. */ |
432233b3 | 736 | #define INSN_CHIP_MASK 0xc3ff0f20 |
e6429699 AN |
737 | |
738 | /* Cavium Networks Octeon instructions. */ | |
739 | #define INSN_OCTEON 0x00000800 | |
dd6a37e7 | 740 | #define INSN_OCTEONP 0x00000200 |
432233b3 | 741 | #define INSN_OCTEON2 0x00000100 |
e6429699 | 742 | |
e407c74b NC |
743 | /* MIPS R5900 instruction */ |
744 | #define INSN_5900 0x00004000 | |
f79e2745 | 745 | |
252b5132 | 746 | /* MIPS R4650 instruction. */ |
e7af610e | 747 | #define INSN_4650 0x00010000 |
252b5132 | 748 | /* LSI R4010 instruction. */ |
e7af610e NC |
749 | #define INSN_4010 0x00020000 |
750 | /* NEC VR4100 instruction. */ | |
bf40d919 | 751 | #define INSN_4100 0x00040000 |
252b5132 | 752 | /* Toshiba R3900 instruction. */ |
bf40d919 | 753 | #define INSN_3900 0x00080000 |
99c14723 TS |
754 | /* MIPS R10000 instruction. */ |
755 | #define INSN_10000 0x00100000 | |
2228315b CD |
756 | /* Broadcom SB-1 instruction. */ |
757 | #define INSN_SB1 0x00200000 | |
9752cf1b RS |
758 | /* NEC VR4111/VR4181 instruction. */ |
759 | #define INSN_4111 0x00400000 | |
760 | /* NEC VR4120 instruction. */ | |
761 | #define INSN_4120 0x00800000 | |
762 | /* NEC VR5400 instruction. */ | |
763 | #define INSN_5400 0x01000000 | |
764 | /* NEC VR5500 instruction. */ | |
765 | #define INSN_5500 0x02000000 | |
39a7806d | 766 | |
350cc38d MS |
767 | /* ST Microelectronics Loongson 2E. */ |
768 | #define INSN_LOONGSON_2E 0x40000000 | |
769 | /* ST Microelectronics Loongson 2F. */ | |
435b94a4 | 770 | #define INSN_LOONGSON_2F 0x80000000 |
fd503541 | 771 | /* Loongson 3A. */ |
435b94a4 | 772 | #define INSN_LOONGSON_3A 0x00000400 |
52b6b6b9 | 773 | /* RMI Xlr instruction */ |
d301a56b | 774 | #define INSN_XLR 0x00000020 |
39a7806d | 775 | |
d301a56b RS |
776 | /* DSP ASE */ |
777 | #define ASE_DSP 0x00000001 | |
778 | #define ASE_DSP64 0x00000002 | |
779 | /* DSP R2 ASE */ | |
780 | #define ASE_DSPR2 0x00000004 | |
7f3c4072 CM |
781 | /* Enhanced VA Scheme */ |
782 | #define ASE_EVA 0x00000008 | |
dec0624d | 783 | /* MCU (MicroController) ASE */ |
d301a56b RS |
784 | #define ASE_MCU 0x00000010 |
785 | /* MDMX ASE */ | |
786 | #define ASE_MDMX 0x00000020 | |
787 | /* MIPS-3D ASE */ | |
788 | #define ASE_MIPS3D 0x00000040 | |
789 | /* MT ASE */ | |
790 | #define ASE_MT 0x00000080 | |
791 | /* SmartMIPS ASE */ | |
792 | #define ASE_SMARTMIPS 0x00000100 | |
793 | /* Virtualization ASE */ | |
794 | #define ASE_VIRT 0x00000200 | |
795 | #define ASE_VIRT64 0x00000400 | |
dec0624d | 796 | |
e7af610e NC |
797 | /* MIPS ISA defines, use instead of hardcoding ISA level. */ |
798 | ||
799 | #define ISA_UNKNOWN 0 /* Gas internal use. */ | |
56950294 MS |
800 | #define ISA_MIPS1 INSN_ISA1 |
801 | #define ISA_MIPS2 INSN_ISA2 | |
802 | #define ISA_MIPS3 INSN_ISA3 | |
803 | #define ISA_MIPS4 INSN_ISA4 | |
804 | #define ISA_MIPS5 INSN_ISA5 | |
af7ee8bf | 805 | |
56950294 MS |
806 | #define ISA_MIPS32 INSN_ISA32 |
807 | #define ISA_MIPS64 INSN_ISA64 | |
367c01af | 808 | |
56950294 MS |
809 | #define ISA_MIPS32R2 INSN_ISA32R2 |
810 | #define ISA_MIPS64R2 INSN_ISA64R2 | |
5f74bc13 | 811 | |
af7ee8bf | 812 | |
156c2f8b NC |
813 | /* CPU defines, use instead of hardcoding processor number. Keep this |
814 | in sync with bfd/archures.c in order for machine selection to work. */ | |
e7af610e | 815 | #define CPU_UNKNOWN 0 /* Gas internal use. */ |
156c2f8b NC |
816 | #define CPU_R3000 3000 |
817 | #define CPU_R3900 3900 | |
818 | #define CPU_R4000 4000 | |
819 | #define CPU_R4010 4010 | |
820 | #define CPU_VR4100 4100 | |
821 | #define CPU_R4111 4111 | |
9752cf1b | 822 | #define CPU_VR4120 4120 |
156c2f8b NC |
823 | #define CPU_R4300 4300 |
824 | #define CPU_R4400 4400 | |
825 | #define CPU_R4600 4600 | |
826 | #define CPU_R4650 4650 | |
827 | #define CPU_R5000 5000 | |
9752cf1b RS |
828 | #define CPU_VR5400 5400 |
829 | #define CPU_VR5500 5500 | |
e407c74b | 830 | #define CPU_R5900 5900 |
156c2f8b | 831 | #define CPU_R6000 6000 |
5a7ea749 | 832 | #define CPU_RM7000 7000 |
156c2f8b | 833 | #define CPU_R8000 8000 |
98e7aba8 | 834 | #define CPU_RM9000 9000 |
156c2f8b | 835 | #define CPU_R10000 10000 |
d1cf510e | 836 | #define CPU_R12000 12000 |
3aa3176b TS |
837 | #define CPU_R14000 14000 |
838 | #define CPU_R16000 16000 | |
156c2f8b NC |
839 | #define CPU_MIPS16 16 |
840 | #define CPU_MIPS32 32 | |
af7ee8bf | 841 | #define CPU_MIPS32R2 33 |
84ea6cf2 NC |
842 | #define CPU_MIPS5 5 |
843 | #define CPU_MIPS64 64 | |
5f74bc13 | 844 | #define CPU_MIPS64R2 65 |
c6c98b38 | 845 | #define CPU_SB1 12310201 /* octal 'SB', 01. */ |
350cc38d MS |
846 | #define CPU_LOONGSON_2E 3001 |
847 | #define CPU_LOONGSON_2F 3002 | |
fd503541 | 848 | #define CPU_LOONGSON_3A 3003 |
e6429699 | 849 | #define CPU_OCTEON 6501 |
dd6a37e7 | 850 | #define CPU_OCTEONP 6601 |
432233b3 | 851 | #define CPU_OCTEON2 6502 |
52b6b6b9 | 852 | #define CPU_XLR 887682 /* decimal 'XLR' */ |
156c2f8b | 853 | |
35d0a169 MR |
854 | /* Return true if the given CPU is included in INSN_* mask MASK. */ |
855 | ||
856 | static inline bfd_boolean | |
857 | cpu_is_member (int cpu, unsigned int mask) | |
858 | { | |
859 | switch (cpu) | |
860 | { | |
861 | case CPU_R4650: | |
862 | case CPU_RM7000: | |
863 | case CPU_RM9000: | |
864 | return (mask & INSN_4650) != 0; | |
865 | ||
866 | case CPU_R4010: | |
867 | return (mask & INSN_4010) != 0; | |
868 | ||
869 | case CPU_VR4100: | |
870 | return (mask & INSN_4100) != 0; | |
871 | ||
872 | case CPU_R3900: | |
873 | return (mask & INSN_3900) != 0; | |
874 | ||
875 | case CPU_R10000: | |
876 | case CPU_R12000: | |
877 | case CPU_R14000: | |
878 | case CPU_R16000: | |
879 | return (mask & INSN_10000) != 0; | |
880 | ||
881 | case CPU_SB1: | |
882 | return (mask & INSN_SB1) != 0; | |
883 | ||
884 | case CPU_R4111: | |
885 | return (mask & INSN_4111) != 0; | |
886 | ||
887 | case CPU_VR4120: | |
888 | return (mask & INSN_4120) != 0; | |
889 | ||
890 | case CPU_VR5400: | |
891 | return (mask & INSN_5400) != 0; | |
892 | ||
893 | case CPU_VR5500: | |
894 | return (mask & INSN_5500) != 0; | |
895 | ||
e407c74b NC |
896 | case CPU_R5900: |
897 | return (mask & INSN_5900) != 0; | |
898 | ||
35d0a169 MR |
899 | case CPU_LOONGSON_2E: |
900 | return (mask & INSN_LOONGSON_2E) != 0; | |
901 | ||
902 | case CPU_LOONGSON_2F: | |
903 | return (mask & INSN_LOONGSON_2F) != 0; | |
904 | ||
905 | case CPU_LOONGSON_3A: | |
906 | return (mask & INSN_LOONGSON_3A) != 0; | |
907 | ||
908 | case CPU_OCTEON: | |
909 | return (mask & INSN_OCTEON) != 0; | |
910 | ||
911 | case CPU_OCTEONP: | |
912 | return (mask & INSN_OCTEONP) != 0; | |
913 | ||
914 | case CPU_OCTEON2: | |
915 | return (mask & INSN_OCTEON2) != 0; | |
916 | ||
917 | case CPU_XLR: | |
918 | return (mask & INSN_XLR) != 0; | |
919 | ||
920 | default: | |
921 | return FALSE; | |
922 | } | |
923 | } | |
924 | ||
1f25f5d3 CD |
925 | /* Test for membership in an ISA including chip specific ISAs. INSN |
926 | is pointer to an element of the opcode table; ISA is the specified | |
927 | ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to | |
35d0a169 MR |
928 | test, or zero if no CPU specific ISA test is desired. Return true |
929 | if instruction INSN is available to the given ISA and CPU. */ | |
930 | ||
931 | static inline bfd_boolean | |
d301a56b | 932 | opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu) |
35d0a169 MR |
933 | { |
934 | if (!cpu_is_member (cpu, insn->exclusions)) | |
935 | { | |
936 | /* Test for ISA level compatibility. */ | |
937 | if ((isa & INSN_ISA_MASK) != 0 | |
938 | && (insn->membership & INSN_ISA_MASK) != 0 | |
939 | && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1] | |
940 | >> ((insn->membership & INSN_ISA_MASK) - 1)) & 1) != 0) | |
941 | return TRUE; | |
942 | ||
943 | /* Test for ASE compatibility. */ | |
d301a56b | 944 | if ((ase & insn->ase) != 0) |
35d0a169 MR |
945 | return TRUE; |
946 | ||
947 | /* Test for processor-specific extensions. */ | |
948 | if (cpu_is_member (cpu, insn->membership)) | |
949 | return TRUE; | |
950 | } | |
951 | return FALSE; | |
952 | } | |
252b5132 RH |
953 | |
954 | /* This is a list of macro expanded instructions. | |
8eaec934 | 955 | |
e7af610e NC |
956 | _I appended means immediate |
957 | _A appended means address | |
958 | _AB appended means address with base register | |
959 | _D appended means 64 bit floating point constant | |
960 | _S appended means 32 bit floating point constant. */ | |
961 | ||
962 | enum | |
963 | { | |
964 | M_ABS, | |
dec0624d MR |
965 | M_ACLR_AB, |
966 | M_ACLR_OB, | |
e7af610e NC |
967 | M_ADD_I, |
968 | M_ADDU_I, | |
969 | M_AND_I, | |
dec0624d MR |
970 | M_ASET_AB, |
971 | M_ASET_OB, | |
8b082fb1 | 972 | M_BALIGN, |
df58fc94 RS |
973 | M_BC1FL, |
974 | M_BC1TL, | |
975 | M_BC2FL, | |
976 | M_BC2TL, | |
e7af610e NC |
977 | M_BEQ, |
978 | M_BEQ_I, | |
df58fc94 | 979 | M_BEQL, |
e7af610e NC |
980 | M_BEQL_I, |
981 | M_BGE, | |
982 | M_BGEL, | |
983 | M_BGE_I, | |
984 | M_BGEL_I, | |
985 | M_BGEU, | |
986 | M_BGEUL, | |
987 | M_BGEU_I, | |
988 | M_BGEUL_I, | |
df58fc94 RS |
989 | M_BGEZ, |
990 | M_BGEZL, | |
991 | M_BGEZALL, | |
e7af610e NC |
992 | M_BGT, |
993 | M_BGTL, | |
994 | M_BGT_I, | |
995 | M_BGTL_I, | |
996 | M_BGTU, | |
997 | M_BGTUL, | |
998 | M_BGTU_I, | |
999 | M_BGTUL_I, | |
df58fc94 RS |
1000 | M_BGTZ, |
1001 | M_BGTZL, | |
e7af610e NC |
1002 | M_BLE, |
1003 | M_BLEL, | |
1004 | M_BLE_I, | |
1005 | M_BLEL_I, | |
1006 | M_BLEU, | |
1007 | M_BLEUL, | |
1008 | M_BLEU_I, | |
1009 | M_BLEUL_I, | |
df58fc94 RS |
1010 | M_BLEZ, |
1011 | M_BLEZL, | |
e7af610e NC |
1012 | M_BLT, |
1013 | M_BLTL, | |
1014 | M_BLT_I, | |
1015 | M_BLTL_I, | |
1016 | M_BLTU, | |
1017 | M_BLTUL, | |
1018 | M_BLTU_I, | |
1019 | M_BLTUL_I, | |
df58fc94 RS |
1020 | M_BLTZ, |
1021 | M_BLTZL, | |
1022 | M_BLTZALL, | |
e7af610e | 1023 | M_BNE, |
df58fc94 | 1024 | M_BNEL, |
e7af610e NC |
1025 | M_BNE_I, |
1026 | M_BNEL_I, | |
d43b4baf | 1027 | M_CACHE_AB, |
df58fc94 | 1028 | M_CACHE_OB, |
7f3c4072 CM |
1029 | M_CACHEE_AB, |
1030 | M_CACHEE_OB, | |
e7af610e NC |
1031 | M_DABS, |
1032 | M_DADD_I, | |
1033 | M_DADDU_I, | |
1034 | M_DDIV_3, | |
1035 | M_DDIV_3I, | |
1036 | M_DDIVU_3, | |
1037 | M_DDIVU_3I, | |
5f74bc13 CD |
1038 | M_DEXT, |
1039 | M_DINS, | |
e7af610e NC |
1040 | M_DIV_3, |
1041 | M_DIV_3I, | |
1042 | M_DIVU_3, | |
1043 | M_DIVU_3I, | |
1044 | M_DLA_AB, | |
1abe91b1 | 1045 | M_DLCA_AB, |
e7af610e NC |
1046 | M_DLI, |
1047 | M_DMUL, | |
8eaec934 | 1048 | M_DMUL_I, |
e7af610e | 1049 | M_DMULO, |
8eaec934 | 1050 | M_DMULO_I, |
e7af610e | 1051 | M_DMULOU, |
8eaec934 | 1052 | M_DMULOU_I, |
e7af610e NC |
1053 | M_DREM_3, |
1054 | M_DREM_3I, | |
1055 | M_DREMU_3, | |
1056 | M_DREMU_3I, | |
1057 | M_DSUB_I, | |
1058 | M_DSUBU_I, | |
1059 | M_DSUBU_I_2, | |
1060 | M_J_A, | |
1061 | M_JAL_1, | |
1062 | M_JAL_2, | |
1063 | M_JAL_A, | |
df58fc94 RS |
1064 | M_JALS_1, |
1065 | M_JALS_2, | |
1066 | M_JALS_A, | |
e7af610e NC |
1067 | M_L_DOB, |
1068 | M_L_DAB, | |
1069 | M_LA_AB, | |
1070 | M_LB_A, | |
1071 | M_LB_AB, | |
7f3c4072 CM |
1072 | M_LBE_OB, |
1073 | M_LBE_AB, | |
e7af610e NC |
1074 | M_LBU_A, |
1075 | M_LBU_AB, | |
7f3c4072 CM |
1076 | M_LBUE_OB, |
1077 | M_LBUE_AB, | |
1abe91b1 | 1078 | M_LCA_AB, |
e7af610e NC |
1079 | M_LD_A, |
1080 | M_LD_OB, | |
1081 | M_LD_AB, | |
1082 | M_LDC1_AB, | |
1083 | M_LDC2_AB, | |
df58fc94 | 1084 | M_LDC2_OB, |
c77c0862 | 1085 | M_LQC2_AB, |
e7af610e NC |
1086 | M_LDC3_AB, |
1087 | M_LDL_AB, | |
df58fc94 RS |
1088 | M_LDL_OB, |
1089 | M_LDM_AB, | |
1090 | M_LDM_OB, | |
1091 | M_LDP_AB, | |
1092 | M_LDP_OB, | |
e7af610e | 1093 | M_LDR_AB, |
df58fc94 | 1094 | M_LDR_OB, |
e7af610e NC |
1095 | M_LH_A, |
1096 | M_LH_AB, | |
7f3c4072 CM |
1097 | M_LHE_OB, |
1098 | M_LHE_AB, | |
e7af610e NC |
1099 | M_LHU_A, |
1100 | M_LHU_AB, | |
7f3c4072 CM |
1101 | M_LHUE_OB, |
1102 | M_LHUE_AB, | |
e7af610e NC |
1103 | M_LI, |
1104 | M_LI_D, | |
1105 | M_LI_DD, | |
1106 | M_LI_S, | |
1107 | M_LI_SS, | |
1108 | M_LL_AB, | |
df58fc94 | 1109 | M_LL_OB, |
e7af610e | 1110 | M_LLD_AB, |
df58fc94 | 1111 | M_LLD_OB, |
7f3c4072 CM |
1112 | M_LLE_AB, |
1113 | M_LLE_OB, | |
e407c74b | 1114 | M_LQ_AB, |
e7af610e NC |
1115 | M_LS_A, |
1116 | M_LW_A, | |
1117 | M_LW_AB, | |
7f3c4072 CM |
1118 | M_LWE_OB, |
1119 | M_LWE_AB, | |
e7af610e NC |
1120 | M_LWC0_A, |
1121 | M_LWC0_AB, | |
1122 | M_LWC1_A, | |
1123 | M_LWC1_AB, | |
1124 | M_LWC2_A, | |
1125 | M_LWC2_AB, | |
df58fc94 | 1126 | M_LWC2_OB, |
e7af610e NC |
1127 | M_LWC3_A, |
1128 | M_LWC3_AB, | |
1129 | M_LWL_A, | |
1130 | M_LWL_AB, | |
df58fc94 | 1131 | M_LWL_OB, |
7f3c4072 CM |
1132 | M_LWLE_AB, |
1133 | M_LWLE_OB, | |
df58fc94 RS |
1134 | M_LWM_AB, |
1135 | M_LWM_OB, | |
1136 | M_LWP_AB, | |
1137 | M_LWP_OB, | |
e7af610e NC |
1138 | M_LWR_A, |
1139 | M_LWR_AB, | |
df58fc94 | 1140 | M_LWR_OB, |
7f3c4072 CM |
1141 | M_LWRE_AB, |
1142 | M_LWRE_OB, | |
e7af610e | 1143 | M_LWU_AB, |
df58fc94 | 1144 | M_LWU_OB, |
52b6b6b9 JM |
1145 | M_MSGSND, |
1146 | M_MSGLD, | |
1147 | M_MSGLD_T, | |
1148 | M_MSGWAIT, | |
1149 | M_MSGWAIT_T, | |
a58ec95a | 1150 | M_MOVE, |
e7af610e | 1151 | M_MUL, |
8eaec934 | 1152 | M_MUL_I, |
e7af610e | 1153 | M_MULO, |
8eaec934 | 1154 | M_MULO_I, |
e7af610e | 1155 | M_MULOU, |
8eaec934 | 1156 | M_MULOU_I, |
e7af610e NC |
1157 | M_NOR_I, |
1158 | M_OR_I, | |
3eebd5eb | 1159 | M_PREF_AB, |
df58fc94 | 1160 | M_PREF_OB, |
7f3c4072 CM |
1161 | M_PREFE_AB, |
1162 | M_PREFE_OB, | |
e7af610e NC |
1163 | M_REM_3, |
1164 | M_REM_3I, | |
1165 | M_REMU_3, | |
1166 | M_REMU_3I, | |
771c7ce4 | 1167 | M_DROL, |
e7af610e | 1168 | M_ROL, |
771c7ce4 | 1169 | M_DROL_I, |
e7af610e | 1170 | M_ROL_I, |
771c7ce4 | 1171 | M_DROR, |
e7af610e | 1172 | M_ROR, |
771c7ce4 | 1173 | M_DROR_I, |
e7af610e NC |
1174 | M_ROR_I, |
1175 | M_S_DA, | |
1176 | M_S_DOB, | |
1177 | M_S_DAB, | |
1178 | M_S_S, | |
dd6a37e7 AP |
1179 | M_SAA_AB, |
1180 | M_SAA_OB, | |
1181 | M_SAAD_AB, | |
1182 | M_SAAD_OB, | |
e7af610e | 1183 | M_SC_AB, |
df58fc94 | 1184 | M_SC_OB, |
e7af610e | 1185 | M_SCD_AB, |
df58fc94 | 1186 | M_SCD_OB, |
7f3c4072 CM |
1187 | M_SCE_AB, |
1188 | M_SCE_OB, | |
e7af610e NC |
1189 | M_SD_A, |
1190 | M_SD_OB, | |
1191 | M_SD_AB, | |
1192 | M_SDC1_AB, | |
1193 | M_SDC2_AB, | |
df58fc94 | 1194 | M_SDC2_OB, |
c77c0862 | 1195 | M_SQC2_AB, |
e7af610e NC |
1196 | M_SDC3_AB, |
1197 | M_SDL_AB, | |
df58fc94 RS |
1198 | M_SDL_OB, |
1199 | M_SDM_AB, | |
1200 | M_SDM_OB, | |
1201 | M_SDP_AB, | |
1202 | M_SDP_OB, | |
e7af610e | 1203 | M_SDR_AB, |
df58fc94 | 1204 | M_SDR_OB, |
e7af610e NC |
1205 | M_SEQ, |
1206 | M_SEQ_I, | |
1207 | M_SGE, | |
1208 | M_SGE_I, | |
1209 | M_SGEU, | |
1210 | M_SGEU_I, | |
1211 | M_SGT, | |
1212 | M_SGT_I, | |
1213 | M_SGTU, | |
1214 | M_SGTU_I, | |
1215 | M_SLE, | |
1216 | M_SLE_I, | |
1217 | M_SLEU, | |
1218 | M_SLEU_I, | |
1219 | M_SLT_I, | |
1220 | M_SLTU_I, | |
1221 | M_SNE, | |
1222 | M_SNE_I, | |
1223 | M_SB_A, | |
1224 | M_SB_AB, | |
7f3c4072 CM |
1225 | M_SBE_OB, |
1226 | M_SBE_AB, | |
e7af610e NC |
1227 | M_SH_A, |
1228 | M_SH_AB, | |
7f3c4072 CM |
1229 | M_SHE_OB, |
1230 | M_SHE_AB, | |
e407c74b | 1231 | M_SQ_AB, |
e7af610e NC |
1232 | M_SW_A, |
1233 | M_SW_AB, | |
7f3c4072 CM |
1234 | M_SWE_OB, |
1235 | M_SWE_AB, | |
e7af610e NC |
1236 | M_SWC0_A, |
1237 | M_SWC0_AB, | |
1238 | M_SWC1_A, | |
1239 | M_SWC1_AB, | |
1240 | M_SWC2_A, | |
1241 | M_SWC2_AB, | |
df58fc94 | 1242 | M_SWC2_OB, |
e7af610e NC |
1243 | M_SWC3_A, |
1244 | M_SWC3_AB, | |
1245 | M_SWL_A, | |
1246 | M_SWL_AB, | |
df58fc94 | 1247 | M_SWL_OB, |
7f3c4072 CM |
1248 | M_SWLE_AB, |
1249 | M_SWLE_OB, | |
df58fc94 RS |
1250 | M_SWM_AB, |
1251 | M_SWM_OB, | |
1252 | M_SWP_AB, | |
1253 | M_SWP_OB, | |
e7af610e NC |
1254 | M_SWR_A, |
1255 | M_SWR_AB, | |
df58fc94 | 1256 | M_SWR_OB, |
7f3c4072 CM |
1257 | M_SWRE_AB, |
1258 | M_SWRE_OB, | |
e7af610e NC |
1259 | M_SUB_I, |
1260 | M_SUBU_I, | |
1261 | M_SUBU_I_2, | |
1262 | M_TEQ_I, | |
1263 | M_TGE_I, | |
1264 | M_TGEU_I, | |
1265 | M_TLT_I, | |
1266 | M_TLTU_I, | |
1267 | M_TNE_I, | |
1268 | M_TRUNCWD, | |
1269 | M_TRUNCWS, | |
1270 | M_ULD, | |
1271 | M_ULD_A, | |
1272 | M_ULH, | |
1273 | M_ULH_A, | |
1274 | M_ULHU, | |
1275 | M_ULHU_A, | |
1276 | M_ULW, | |
1277 | M_ULW_A, | |
1278 | M_USH, | |
1279 | M_USH_A, | |
1280 | M_USW, | |
1281 | M_USW_A, | |
1282 | M_USD, | |
1283 | M_USD_A, | |
1284 | M_XOR_I, | |
1285 | M_COP0, | |
1286 | M_COP1, | |
1287 | M_COP2, | |
1288 | M_COP3, | |
1289 | M_NUM_MACROS | |
252b5132 RH |
1290 | }; |
1291 | ||
1292 | ||
1293 | /* The order of overloaded instructions matters. Label arguments and | |
1294 | register arguments look the same. Instructions that can have either | |
1295 | for arguments must apear in the correct order in this table for the | |
1296 | assembler to pick the right one. In other words, entries with | |
1297 | immediate operands must apear after the same instruction with | |
1298 | registers. | |
1299 | ||
1300 | Many instructions are short hand for other instructions (i.e., The | |
1301 | jal <register> instruction is short for jalr <register>). */ | |
1302 | ||
1303 | extern const struct mips_opcode mips_builtin_opcodes[]; | |
1304 | extern const int bfd_mips_num_builtin_opcodes; | |
1305 | extern struct mips_opcode *mips_opcodes; | |
1306 | extern int bfd_mips_num_opcodes; | |
1307 | #define NUMOPCODES bfd_mips_num_opcodes | |
1308 | ||
1309 | \f | |
1310 | /* The rest of this file adds definitions for the mips16 TinyRISC | |
1311 | processor. */ | |
1312 | ||
1313 | /* These are the bitmasks and shift counts used for the different | |
1314 | fields in the instruction formats. Other than OP, no masks are | |
1315 | provided for the fixed portions of an instruction, since they are | |
1316 | not needed. | |
1317 | ||
1318 | The I format uses IMM11. | |
1319 | ||
1320 | The RI format uses RX and IMM8. | |
1321 | ||
1322 | The RR format uses RX, and RY. | |
1323 | ||
1324 | The RRI format uses RX, RY, and IMM5. | |
1325 | ||
1326 | The RRR format uses RX, RY, and RZ. | |
1327 | ||
1328 | The RRI_A format uses RX, RY, and IMM4. | |
1329 | ||
1330 | The SHIFT format uses RX, RY, and SHAMT. | |
1331 | ||
1332 | The I8 format uses IMM8. | |
1333 | ||
1334 | The I8_MOVR32 format uses RY and REGR32. | |
1335 | ||
1336 | The IR_MOV32R format uses REG32R and MOV32Z. | |
1337 | ||
1338 | The I64 format uses IMM8. | |
1339 | ||
1340 | The RI64 format uses RY and IMM5. | |
1341 | */ | |
1342 | ||
1343 | #define MIPS16OP_MASK_OP 0x1f | |
1344 | #define MIPS16OP_SH_OP 11 | |
1345 | #define MIPS16OP_MASK_IMM11 0x7ff | |
1346 | #define MIPS16OP_SH_IMM11 0 | |
1347 | #define MIPS16OP_MASK_RX 0x7 | |
1348 | #define MIPS16OP_SH_RX 8 | |
1349 | #define MIPS16OP_MASK_IMM8 0xff | |
1350 | #define MIPS16OP_SH_IMM8 0 | |
1351 | #define MIPS16OP_MASK_RY 0x7 | |
1352 | #define MIPS16OP_SH_RY 5 | |
1353 | #define MIPS16OP_MASK_IMM5 0x1f | |
1354 | #define MIPS16OP_SH_IMM5 0 | |
1355 | #define MIPS16OP_MASK_RZ 0x7 | |
1356 | #define MIPS16OP_SH_RZ 2 | |
1357 | #define MIPS16OP_MASK_IMM4 0xf | |
1358 | #define MIPS16OP_SH_IMM4 0 | |
1359 | #define MIPS16OP_MASK_REGR32 0x1f | |
1360 | #define MIPS16OP_SH_REGR32 0 | |
1361 | #define MIPS16OP_MASK_REG32R 0x1f | |
1362 | #define MIPS16OP_SH_REG32R 3 | |
1363 | #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) | |
1364 | #define MIPS16OP_MASK_MOVE32Z 0x7 | |
1365 | #define MIPS16OP_SH_MOVE32Z 0 | |
1366 | #define MIPS16OP_MASK_IMM6 0x3f | |
1367 | #define MIPS16OP_SH_IMM6 5 | |
1368 | ||
bb35fb24 NC |
1369 | /* These are the characters which may appears in the args field of a MIPS16 |
1370 | instruction. They appear in the order in which the fields appear when the | |
1371 | instruction is used. Commas and parentheses in the args string are ignored | |
1372 | when assembling, and written into the output when disassembling. | |
252b5132 RH |
1373 | |
1374 | "y" 3 bit register (MIPS16OP_*_RY) | |
1375 | "x" 3 bit register (MIPS16OP_*_RX) | |
1376 | "z" 3 bit register (MIPS16OP_*_RZ) | |
1377 | "Z" 3 bit register (MIPS16OP_*_MOVE32Z) | |
1378 | "v" 3 bit same register as source and destination (MIPS16OP_*_RX) | |
1379 | "w" 3 bit same register as source and destination (MIPS16OP_*_RY) | |
1380 | "0" zero register ($0) | |
1381 | "S" stack pointer ($sp or $29) | |
1382 | "P" program counter | |
1383 | "R" return address register ($ra or $31) | |
1384 | "X" 5 bit MIPS register (MIPS16OP_*_REGR32) | |
1385 | "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) | |
1386 | "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) | |
1387 | "a" 26 bit jump address | |
1388 | "e" 11 bit extension value | |
1389 | "l" register list for entry instruction | |
1390 | "L" register list for exit instruction | |
1391 | ||
1392 | The remaining codes may be extended. Except as otherwise noted, | |
1393 | the full extended operand is a 16 bit signed value. | |
1394 | "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) | |
1395 | ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) | |
1396 | "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) | |
1397 | "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) | |
1398 | "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) | |
1399 | "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) | |
1400 | "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) | |
1401 | "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) | |
1402 | "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) | |
1403 | "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) | |
1404 | "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) | |
1405 | "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) | |
1406 | "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) | |
1407 | "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) | |
1408 | "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) | |
1409 | "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) | |
1410 | "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) | |
1411 | "q" 11 bit branch address (MIPS16OP_*_IMM11) | |
1412 | "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) | |
1413 | "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) | |
1414 | "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) | |
0499d65b TS |
1415 | "m" 7 bit register list for save instruction (18 bit extended) |
1416 | "M" 7 bit register list for restore instruction (18 bit extended) | |
1417 | */ | |
1418 | ||
1419 | /* Save/restore encoding for the args field when all 4 registers are | |
1420 | either saved as arguments or saved/restored as statics. */ | |
1421 | #define MIPS16_ALL_ARGS 0xe | |
1422 | #define MIPS16_ALL_STATICS 0xb | |
252b5132 RH |
1423 | |
1424 | /* For the mips16, we use the same opcode table format and a few of | |
1425 | the same flags. However, most of the flags are different. */ | |
1426 | ||
1427 | /* Modifies the register in MIPS16OP_*_RX. */ | |
1428 | #define MIPS16_INSN_WRITE_X 0x00000001 | |
1429 | /* Modifies the register in MIPS16OP_*_RY. */ | |
1430 | #define MIPS16_INSN_WRITE_Y 0x00000002 | |
1431 | /* Modifies the register in MIPS16OP_*_RZ. */ | |
1432 | #define MIPS16_INSN_WRITE_Z 0x00000004 | |
1433 | /* Modifies the T ($24) register. */ | |
1434 | #define MIPS16_INSN_WRITE_T 0x00000008 | |
1435 | /* Modifies the SP ($29) register. */ | |
1436 | #define MIPS16_INSN_WRITE_SP 0x00000010 | |
1437 | /* Modifies the RA ($31) register. */ | |
1438 | #define MIPS16_INSN_WRITE_31 0x00000020 | |
1439 | /* Modifies the general purpose register in MIPS16OP_*_REG32R. */ | |
1440 | #define MIPS16_INSN_WRITE_GPR_Y 0x00000040 | |
1441 | /* Reads the register in MIPS16OP_*_RX. */ | |
1442 | #define MIPS16_INSN_READ_X 0x00000080 | |
1443 | /* Reads the register in MIPS16OP_*_RY. */ | |
1444 | #define MIPS16_INSN_READ_Y 0x00000100 | |
1445 | /* Reads the register in MIPS16OP_*_MOVE32Z. */ | |
1446 | #define MIPS16_INSN_READ_Z 0x00000200 | |
1447 | /* Reads the T ($24) register. */ | |
1448 | #define MIPS16_INSN_READ_T 0x00000400 | |
1449 | /* Reads the SP ($29) register. */ | |
1450 | #define MIPS16_INSN_READ_SP 0x00000800 | |
1451 | /* Reads the RA ($31) register. */ | |
1452 | #define MIPS16_INSN_READ_31 0x00001000 | |
1453 | /* Reads the program counter. */ | |
1454 | #define MIPS16_INSN_READ_PC 0x00002000 | |
1455 | /* Reads the general purpose register in MIPS16OP_*_REGR32. */ | |
1456 | #define MIPS16_INSN_READ_GPR_X 0x00004000 | |
9a2c7088 MR |
1457 | /* Is an unconditional branch insn. */ |
1458 | #define MIPS16_INSN_UNCOND_BRANCH 0x00008000 | |
1459 | /* Is a conditional branch insn. */ | |
1460 | #define MIPS16_INSN_COND_BRANCH 0x00010000 | |
252b5132 RH |
1461 | |
1462 | /* The following flags have the same value for the mips16 opcode | |
1463 | table: | |
7c176fa8 MR |
1464 | |
1465 | INSN_ISA3 | |
1466 | ||
252b5132 RH |
1467 | INSN_UNCOND_BRANCH_DELAY |
1468 | INSN_COND_BRANCH_DELAY | |
1469 | INSN_COND_BRANCH_LIKELY (never used) | |
1470 | INSN_READ_HI | |
1471 | INSN_READ_LO | |
1472 | INSN_WRITE_HI | |
1473 | INSN_WRITE_LO | |
1474 | INSN_TRAP | |
7c176fa8 | 1475 | FP_D (never used) |
252b5132 RH |
1476 | */ |
1477 | ||
1478 | extern const struct mips_opcode mips16_opcodes[]; | |
1479 | extern const int bfd_mips16_num_opcodes; | |
1480 | ||
2309ddf2 MR |
1481 | /* These are the bit masks and shift counts used for the different fields |
1482 | in the microMIPS instruction formats. No masks are provided for the | |
1483 | fixed portions of an instruction, since they are not needed. */ | |
df58fc94 | 1484 | |
df58fc94 RS |
1485 | #define MICROMIPSOP_MASK_IMMEDIATE 0xffff |
1486 | #define MICROMIPSOP_SH_IMMEDIATE 0 | |
1487 | #define MICROMIPSOP_MASK_DELTA 0xffff | |
1488 | #define MICROMIPSOP_SH_DELTA 0 | |
1489 | #define MICROMIPSOP_MASK_CODE10 0x3ff | |
1490 | #define MICROMIPSOP_SH_CODE10 16 /* 10-bit wait code. */ | |
1491 | #define MICROMIPSOP_MASK_TRAP 0xf | |
1492 | #define MICROMIPSOP_SH_TRAP 12 /* 4-bit trap code. */ | |
1493 | #define MICROMIPSOP_MASK_SHAMT 0x1f | |
1494 | #define MICROMIPSOP_SH_SHAMT 11 | |
1495 | #define MICROMIPSOP_MASK_TARGET 0x3ffffff | |
1496 | #define MICROMIPSOP_SH_TARGET 0 | |
1497 | #define MICROMIPSOP_MASK_EXTLSB 0x1f /* "ext" LSB. */ | |
1498 | #define MICROMIPSOP_SH_EXTLSB 6 | |
1499 | #define MICROMIPSOP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ | |
1500 | #define MICROMIPSOP_SH_EXTMSBD 11 | |
1501 | #define MICROMIPSOP_MASK_INSMSB 0x1f /* "ins" MSB. */ | |
1502 | #define MICROMIPSOP_SH_INSMSB 11 | |
1503 | #define MICROMIPSOP_MASK_CODE 0x3ff | |
1504 | #define MICROMIPSOP_SH_CODE 16 /* 10-bit higher break code. */ | |
1505 | #define MICROMIPSOP_MASK_CODE2 0x3ff | |
1506 | #define MICROMIPSOP_SH_CODE2 6 /* 10-bit lower break code. */ | |
1507 | #define MICROMIPSOP_MASK_CACHE 0x1f | |
1508 | #define MICROMIPSOP_SH_CACHE 21 /* 5-bit cache op. */ | |
1509 | #define MICROMIPSOP_MASK_SEL 0x7 | |
1510 | #define MICROMIPSOP_SH_SEL 11 | |
1511 | #define MICROMIPSOP_MASK_OFFSET12 0xfff | |
1512 | #define MICROMIPSOP_SH_OFFSET12 0 | |
dec0624d MR |
1513 | #define MICROMIPSOP_MASK_3BITPOS 0x7 |
1514 | #define MICROMIPSOP_SH_3BITPOS 21 | |
df58fc94 RS |
1515 | #define MICROMIPSOP_MASK_STYPE 0x1f |
1516 | #define MICROMIPSOP_SH_STYPE 16 | |
1517 | #define MICROMIPSOP_MASK_OFFSET10 0x3ff | |
1518 | #define MICROMIPSOP_SH_OFFSET10 6 | |
1519 | #define MICROMIPSOP_MASK_RS 0x1f | |
1520 | #define MICROMIPSOP_SH_RS 16 | |
1521 | #define MICROMIPSOP_MASK_RT 0x1f | |
1522 | #define MICROMIPSOP_SH_RT 21 | |
1523 | #define MICROMIPSOP_MASK_RD 0x1f | |
1524 | #define MICROMIPSOP_SH_RD 11 | |
1525 | #define MICROMIPSOP_MASK_FS 0x1f | |
1526 | #define MICROMIPSOP_SH_FS 16 | |
1527 | #define MICROMIPSOP_MASK_FT 0x1f | |
1528 | #define MICROMIPSOP_SH_FT 21 | |
1529 | #define MICROMIPSOP_MASK_FD 0x1f | |
1530 | #define MICROMIPSOP_SH_FD 11 | |
1531 | #define MICROMIPSOP_MASK_FR 0x1f | |
1532 | #define MICROMIPSOP_SH_FR 6 | |
1533 | #define MICROMIPSOP_MASK_RS3 0x1f | |
1534 | #define MICROMIPSOP_SH_RS3 6 | |
1535 | #define MICROMIPSOP_MASK_PREFX 0x1f | |
1536 | #define MICROMIPSOP_SH_PREFX 11 | |
1537 | #define MICROMIPSOP_MASK_BCC 0x7 | |
1538 | #define MICROMIPSOP_SH_BCC 18 | |
1539 | #define MICROMIPSOP_MASK_CCC 0x7 | |
1540 | #define MICROMIPSOP_SH_CCC 13 | |
1541 | #define MICROMIPSOP_MASK_COPZ 0x7fffff | |
1542 | #define MICROMIPSOP_SH_COPZ 3 | |
1543 | ||
1544 | #define MICROMIPSOP_MASK_MB 0x7 | |
1545 | #define MICROMIPSOP_SH_MB 23 | |
1546 | #define MICROMIPSOP_MASK_MC 0x7 | |
1547 | #define MICROMIPSOP_SH_MC 4 | |
1548 | #define MICROMIPSOP_MASK_MD 0x7 | |
1549 | #define MICROMIPSOP_SH_MD 7 | |
1550 | #define MICROMIPSOP_MASK_ME 0x7 | |
1551 | #define MICROMIPSOP_SH_ME 1 | |
1552 | #define MICROMIPSOP_MASK_MF 0x7 | |
1553 | #define MICROMIPSOP_SH_MF 3 | |
1554 | #define MICROMIPSOP_MASK_MG 0x7 | |
1555 | #define MICROMIPSOP_SH_MG 0 | |
1556 | #define MICROMIPSOP_MASK_MH 0x7 | |
1557 | #define MICROMIPSOP_SH_MH 7 | |
1558 | #define MICROMIPSOP_MASK_MI 0x7 | |
1559 | #define MICROMIPSOP_SH_MI 7 | |
1560 | #define MICROMIPSOP_MASK_MJ 0x1f | |
1561 | #define MICROMIPSOP_SH_MJ 0 | |
1562 | #define MICROMIPSOP_MASK_ML 0x7 | |
1563 | #define MICROMIPSOP_SH_ML 4 | |
1564 | #define MICROMIPSOP_MASK_MM 0x7 | |
1565 | #define MICROMIPSOP_SH_MM 1 | |
1566 | #define MICROMIPSOP_MASK_MN 0x7 | |
1567 | #define MICROMIPSOP_SH_MN 4 | |
1568 | #define MICROMIPSOP_MASK_MP 0x1f | |
1569 | #define MICROMIPSOP_SH_MP 5 | |
1570 | #define MICROMIPSOP_MASK_MQ 0x7 | |
1571 | #define MICROMIPSOP_SH_MQ 7 | |
1572 | ||
1573 | #define MICROMIPSOP_MASK_IMMA 0x7f | |
1574 | #define MICROMIPSOP_SH_IMMA 0 | |
1575 | #define MICROMIPSOP_MASK_IMMB 0x7 | |
1576 | #define MICROMIPSOP_SH_IMMB 1 | |
1577 | #define MICROMIPSOP_MASK_IMMC 0xf | |
1578 | #define MICROMIPSOP_SH_IMMC 0 | |
1579 | #define MICROMIPSOP_MASK_IMMD 0x3ff | |
1580 | #define MICROMIPSOP_SH_IMMD 0 | |
1581 | #define MICROMIPSOP_MASK_IMME 0x7f | |
1582 | #define MICROMIPSOP_SH_IMME 0 | |
1583 | #define MICROMIPSOP_MASK_IMMF 0xf | |
1584 | #define MICROMIPSOP_SH_IMMF 0 | |
1585 | #define MICROMIPSOP_MASK_IMMG 0xf | |
1586 | #define MICROMIPSOP_SH_IMMG 0 | |
1587 | #define MICROMIPSOP_MASK_IMMH 0xf | |
1588 | #define MICROMIPSOP_SH_IMMH 0 | |
1589 | #define MICROMIPSOP_MASK_IMMI 0x7f | |
1590 | #define MICROMIPSOP_SH_IMMI 0 | |
1591 | #define MICROMIPSOP_MASK_IMMJ 0xf | |
1592 | #define MICROMIPSOP_SH_IMMJ 0 | |
1593 | #define MICROMIPSOP_MASK_IMML 0xf | |
1594 | #define MICROMIPSOP_SH_IMML 0 | |
1595 | #define MICROMIPSOP_MASK_IMMM 0x7 | |
1596 | #define MICROMIPSOP_SH_IMMM 1 | |
1597 | #define MICROMIPSOP_MASK_IMMN 0x3 | |
1598 | #define MICROMIPSOP_SH_IMMN 4 | |
1599 | #define MICROMIPSOP_MASK_IMMO 0xf | |
1600 | #define MICROMIPSOP_SH_IMMO 0 | |
1601 | #define MICROMIPSOP_MASK_IMMP 0x1f | |
1602 | #define MICROMIPSOP_SH_IMMP 0 | |
1603 | #define MICROMIPSOP_MASK_IMMQ 0x7fffff | |
1604 | #define MICROMIPSOP_SH_IMMQ 0 | |
1605 | #define MICROMIPSOP_MASK_IMMU 0x1f | |
1606 | #define MICROMIPSOP_SH_IMMU 0 | |
1607 | #define MICROMIPSOP_MASK_IMMW 0x3f | |
1608 | #define MICROMIPSOP_SH_IMMW 1 | |
1609 | #define MICROMIPSOP_MASK_IMMX 0xf | |
1610 | #define MICROMIPSOP_SH_IMMX 1 | |
1611 | #define MICROMIPSOP_MASK_IMMY 0x1ff | |
1612 | #define MICROMIPSOP_SH_IMMY 1 | |
1613 | ||
03f66e8a MR |
1614 | /* MIPS DSP ASE */ |
1615 | #define MICROMIPSOP_MASK_DSPACC 0x3 | |
1616 | #define MICROMIPSOP_SH_DSPACC 14 | |
1617 | #define MICROMIPSOP_MASK_DSPSFT 0x3f | |
1618 | #define MICROMIPSOP_SH_DSPSFT 16 | |
1619 | #define MICROMIPSOP_MASK_SA3 0x7 | |
1620 | #define MICROMIPSOP_SH_SA3 13 | |
1621 | #define MICROMIPSOP_MASK_SA4 0xf | |
1622 | #define MICROMIPSOP_SH_SA4 12 | |
1623 | #define MICROMIPSOP_MASK_IMM8 0xff | |
1624 | #define MICROMIPSOP_SH_IMM8 13 | |
1625 | #define MICROMIPSOP_MASK_IMM10 0x3ff | |
1626 | #define MICROMIPSOP_SH_IMM10 16 | |
1627 | #define MICROMIPSOP_MASK_WRDSP 0x3f | |
1628 | #define MICROMIPSOP_SH_WRDSP 14 | |
1629 | #define MICROMIPSOP_MASK_BP 0x3 | |
1630 | #define MICROMIPSOP_SH_BP 14 | |
1631 | ||
df58fc94 RS |
1632 | /* Placeholders for fields that only exist in the traditional 32-bit |
1633 | instruction encoding; see the comment above for details. */ | |
1634 | #define MICROMIPSOP_MASK_CODE20 0 | |
1635 | #define MICROMIPSOP_SH_CODE20 0 | |
1636 | #define MICROMIPSOP_MASK_PERFREG 0 | |
1637 | #define MICROMIPSOP_SH_PERFREG 0 | |
1638 | #define MICROMIPSOP_MASK_CODE19 0 | |
1639 | #define MICROMIPSOP_SH_CODE19 0 | |
1640 | #define MICROMIPSOP_MASK_ALN 0 | |
1641 | #define MICROMIPSOP_SH_ALN 0 | |
1642 | #define MICROMIPSOP_MASK_VECBYTE 0 | |
1643 | #define MICROMIPSOP_SH_VECBYTE 0 | |
1644 | #define MICROMIPSOP_MASK_VECALIGN 0 | |
1645 | #define MICROMIPSOP_SH_VECALIGN 0 | |
df58fc94 RS |
1646 | #define MICROMIPSOP_MASK_DSPACC_S 0 |
1647 | #define MICROMIPSOP_SH_DSPACC_S 0 | |
df58fc94 RS |
1648 | #define MICROMIPSOP_MASK_DSPSFT_7 0 |
1649 | #define MICROMIPSOP_SH_DSPSFT_7 0 | |
df58fc94 RS |
1650 | #define MICROMIPSOP_MASK_RDDSP 0 |
1651 | #define MICROMIPSOP_SH_RDDSP 0 | |
df58fc94 RS |
1652 | #define MICROMIPSOP_MASK_MT_U 0 |
1653 | #define MICROMIPSOP_SH_MT_U 0 | |
1654 | #define MICROMIPSOP_MASK_MT_H 0 | |
1655 | #define MICROMIPSOP_SH_MT_H 0 | |
1656 | #define MICROMIPSOP_MASK_MTACC_T 0 | |
1657 | #define MICROMIPSOP_SH_MTACC_T 0 | |
1658 | #define MICROMIPSOP_MASK_MTACC_D 0 | |
1659 | #define MICROMIPSOP_SH_MTACC_D 0 | |
1660 | #define MICROMIPSOP_MASK_BBITIND 0 | |
1661 | #define MICROMIPSOP_SH_BBITIND 0 | |
1662 | #define MICROMIPSOP_MASK_CINSPOS 0 | |
1663 | #define MICROMIPSOP_SH_CINSPOS 0 | |
1664 | #define MICROMIPSOP_MASK_CINSLM1 0 | |
1665 | #define MICROMIPSOP_SH_CINSLM1 0 | |
1666 | #define MICROMIPSOP_MASK_SEQI 0 | |
1667 | #define MICROMIPSOP_SH_SEQI 0 | |
1668 | #define MICROMIPSOP_SH_OFFSET_A 0 | |
1669 | #define MICROMIPSOP_MASK_OFFSET_A 0 | |
1670 | #define MICROMIPSOP_SH_OFFSET_B 0 | |
1671 | #define MICROMIPSOP_MASK_OFFSET_B 0 | |
1672 | #define MICROMIPSOP_SH_OFFSET_C 0 | |
1673 | #define MICROMIPSOP_MASK_OFFSET_C 0 | |
1674 | #define MICROMIPSOP_SH_RZ 0 | |
1675 | #define MICROMIPSOP_MASK_RZ 0 | |
1676 | #define MICROMIPSOP_SH_FZ 0 | |
1677 | #define MICROMIPSOP_MASK_FZ 0 | |
1678 | ||
7f3c4072 CM |
1679 | /* microMIPS Enhanced VA Scheme */ |
1680 | #define MICROMIPSOP_SH_EVAOFFSET 0 | |
1681 | #define MICROMIPSOP_MASK_EVAOFFSET 0x1ff | |
1682 | ||
df58fc94 RS |
1683 | /* These are the characters which may appears in the args field of a microMIPS |
1684 | instruction. They appear in the order in which the fields appear | |
1685 | when the instruction is used. Commas and parentheses in the args | |
1686 | string are ignored when assembling, and written into the output | |
1687 | when disassembling. | |
1688 | ||
1689 | The followings are for 16-bit microMIPS instructions. | |
1690 | ||
1691 | "ma" must be $28 | |
1692 | "mc" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MC) at bit 4 | |
1693 | The same register used as both source and target. | |
1694 | "md" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MD) at bit 7 | |
1695 | "me" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ME) at bit 1 | |
1696 | The same register used as both source and target. | |
1697 | "mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3 | |
1698 | "mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0 | |
1699 | "mh" MIPS registers 4, 5, 6 (MICROMIPSOP_*_MH) at bit 7 | |
1700 | "mi" MIPS registers 5, 6, 7, 21, 22 (MICROMIPSOP_*_MI) at bit 7 | |
1701 | ("mh" and "mi" form a valid 3-bit register pair) | |
1702 | "mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0 | |
1703 | "ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4 | |
1704 | "mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1 | |
1705 | "mn" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MN) at bit 4 | |
1706 | "mp" 5-bit MIPS registers (MICROMIPSOP_*_MP) at bit 5 | |
1707 | "mq" 3-bit MIPS registers 0, 2-7, 17 (MICROMIPSOP_*_MQ) at bit 7 | |
1708 | "mr" must be program counter | |
1709 | "ms" must be $29 | |
1710 | "mt" must be the same as the previous register | |
1711 | "mx" must be the same as the destination register | |
1712 | "my" must be $31 | |
1713 | "mz" must be $0 | |
1714 | ||
1715 | "mA" 7-bit immediate (-64 .. 63) << 2 (MICROMIPSOP_*_IMMA) | |
1716 | "mB" 3-bit immediate (-1, 1, 4, 8, 12, 16, 20, 24) (MICROMIPSOP_*_IMMB) | |
1717 | "mC" 4-bit immediate (1, 2, 3, 4, 7, 8, 15, 16, 31, 32, 63, 64, 128, 255, | |
1718 | 32768, 65535) (MICROMIPSOP_*_IMMC) | |
1719 | "mD" 10-bit branch address (-512 .. 511) << 1 (MICROMIPSOP_*_IMMD) | |
1720 | "mE" 7-bit branch address (-64 .. 63) << 1 (MICROMIPSOP_*_IMME) | |
1721 | "mF" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMMF) | |
1722 | "mG" 4-bit immediate (-1 .. 14) (MICROMIPSOP_*_IMMG) | |
1723 | "mH" 4-bit immediate (0 .. 15) << 1 (MICROMIPSOP_*_IMMH) | |
1724 | "mI" 7-bit immediate (-1 .. 126) (MICROMIPSOP_*_IMMI) | |
1725 | "mJ" 4-bit immediate (0 .. 15) << 2 (MICROMIPSOP_*_IMMJ) | |
1726 | "mL" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) | |
1727 | "mM" 3-bit immediate (1 .. 8) (MICROMIPSOP_*_IMMM) | |
1728 | "mN" 2-bit immediate (0 .. 3) for register list (MICROMIPSOP_*_IMMN) | |
1729 | "mO" 4-bit immediate (0 .. 15) (MICROMIPSOP_*_IMML) | |
1730 | "mP" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMP) | |
1731 | "mU" 5-bit immediate (0 .. 31) << 2 (MICROMIPSOP_*_IMMU) | |
1732 | "mW" 6-bit immediate (0 .. 63) << 2 (MICROMIPSOP_*_IMMW) | |
1733 | "mX" 4-bit immediate (-8 .. 7) (MICROMIPSOP_*_IMMX) | |
1734 | "mY" 9-bit immediate (-258 .. -3, 2 .. 257) << 2 (MICROMIPSOP_*_IMMY) | |
1735 | "mZ" must be zero | |
1736 | ||
1737 | In most cases 32-bit microMIPS instructions use the same characters | |
1738 | as MIPS (with ADDIUPC being a notable exception, but there are some | |
1739 | others too). | |
1740 | ||
1741 | "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10) | |
1742 | "1" 5-bit sync type (MICROMIPSOP_*_SHAMT) | |
1743 | "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT) | |
1744 | ">" shift amount between 32 and 63, stored after subtracting 32 | |
1745 | (MICROMIPSOP_*_SHAMT) | |
dec0624d | 1746 | "\" 3-bit position for ASET and ACLR (MICROMIPSOP_*_3BITPOS) |
df58fc94 RS |
1747 | "|" 4-bit trap code (MICROMIPSOP_*_TRAP) |
1748 | "~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12) | |
1749 | "a" 26-bit target address (MICROMIPSOP_*_TARGET) | |
1750 | "b" 5-bit base register (MICROMIPSOP_*_RS) | |
1751 | "c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE) | |
1752 | "d" 5-bit destination register specifier (MICROMIPSOP_*_RD) | |
1753 | "h" 5-bit PREFX hint (MICROMIPSOP_*_PREFX) | |
26f85d7a | 1754 | "i" 16-bit unsigned immediate (MICROMIPSOP_*_IMMEDIATE) |
df58fc94 RS |
1755 | "j" 16-bit signed immediate (MICROMIPSOP_*_DELTA) |
1756 | "k" 5-bit cache opcode in target register position (MICROMIPSOP_*_CACHE) | |
1757 | "n" register list for 32-bit LWM/SWM instruction (MICROMIPSOP_*_RT) | |
1758 | "o" 16-bit signed offset (MICROMIPSOP_*_DELTA) | |
1759 | "p" 16-bit PC-relative branch target address (MICROMIPSOP_*_DELTA) | |
1760 | "q" 10-bit lower breakpoint code (MICROMIPSOP_*_CODE2) | |
1761 | "r" 5-bit same register used as both source and target (MICROMIPSOP_*_RS) | |
1762 | "s" 5-bit source register specifier (MICROMIPSOP_*_RS) | |
1763 | "t" 5-bit target register (MICROMIPSOP_*_RT) | |
1764 | "u" 16-bit upper 16 bits of address (MICROMIPSOP_*_IMMEDIATE) | |
1765 | "v" 5-bit same register used as both source and destination | |
1766 | (MICROMIPSOP_*_RS) | |
1767 | "w" 5-bit same register used as both target and destination | |
1768 | (MICROMIPSOP_*_RT) | |
1769 | "y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3) | |
1770 | "z" must be zero register | |
1771 | "C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ) | |
9d7b4c23 | 1772 | "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10) |
df58fc94 RS |
1773 | "K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS) |
1774 | ||
1775 | "+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes | |
1776 | LSB (MICROMIPSOP_*_EXTLSB). | |
1777 | Enforces: 0 <= pos < 32. | |
1778 | "+B" 5-bit INS/DINS size, which becomes MSB (MICROMIPSOP_*_INSMSB). | |
1779 | Requires that "+A" or "+E" occur first to set position. | |
1780 | Enforces: 0 < (pos+size) <= 32. | |
1781 | "+C" 5-bit EXT/DEXT size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). | |
1782 | Requires that "+A" or "+E" occur first to set position. | |
1783 | Enforces: 0 < (pos+size) <= 32. | |
1784 | (Also used by DEXT w/ different limits, but limits for | |
1785 | that are checked by the M_DEXT macro.) | |
1786 | "+E" 5-bit DINSU/DEXTU position, which becomes LSB-32 (MICROMIPSOP_*_EXTLSB). | |
1787 | Enforces: 32 <= pos < 64. | |
1788 | "+F" 5-bit DINSM/DINSU size, which becomes MSB-32 (MICROMIPSOP_*_INSMSB). | |
1789 | Requires that "+A" or "+E" occur first to set position. | |
1790 | Enforces: 32 < (pos+size) <= 64. | |
1791 | "+G" 5-bit DEXTM size, which becomes MSBD-32 (MICROMIPSOP_*_EXTMSBD). | |
1792 | Requires that "+A" or "+E" occur first to set position. | |
1793 | Enforces: 32 < (pos+size) <= 64. | |
1794 | "+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD). | |
1795 | Requires that "+A" or "+E" occur first to set position. | |
1796 | Enforces: 32 < (pos+size) <= 64. | |
1797 | ||
1798 | PC-relative addition (ADDIUPC) instruction: | |
1799 | "mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ) | |
1800 | "mb" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MB) at bit 23 | |
1801 | ||
1802 | Floating point instructions: | |
1803 | "D" 5-bit destination register (MICROMIPSOP_*_FD) | |
1804 | "M" 3-bit compare condition code (MICROMIPSOP_*_CCC) | |
1805 | "N" 3-bit branch condition code (MICROMIPSOP_*_BCC) | |
1806 | "R" 5-bit fr source 3 register (MICROMIPSOP_*_FR) | |
1807 | "S" 5-bit fs source 1 register (MICROMIPSOP_*_FS) | |
1808 | "T" 5-bit ft source 2 register (MICROMIPSOP_*_FT) | |
1809 | "V" 5-bit same register used as floating source and destination or target | |
1810 | (MICROMIPSOP_*_FS) | |
1811 | ||
1812 | Coprocessor instructions: | |
1813 | "E" 5-bit target register (MICROMIPSOP_*_RT) | |
c3678916 | 1814 | "G" 5-bit destination register (MICROMIPSOP_*_RS) |
df58fc94 RS |
1815 | "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) |
1816 | "+D" combined destination register ("G") and sel ("H") for CP0 ops, | |
1817 | for pretty-printing in disassembly only | |
1818 | ||
1819 | Macro instructions: | |
1820 | "A" general 32 bit expression | |
1821 | "I" 32-bit immediate (value placed in imm_expr). | |
1822 | "+I" 32-bit immediate (value placed in imm2_expr). | |
1823 | "F" 64-bit floating point constant in .rdata | |
1824 | "L" 64-bit floating point constant in .lit8 | |
1825 | "f" 32-bit floating point constant | |
1826 | "l" 32-bit floating point constant in .lit4 | |
1827 | ||
03f66e8a MR |
1828 | DSP ASE usage: |
1829 | "2" 2-bit unsigned immediate for byte align (MICROMIPSOP_*_BP) | |
1830 | "3" 3-bit unsigned immediate (MICROMIPSOP_*_SA3) | |
1831 | "4" 4-bit unsigned immediate (MICROMIPSOP_*_SA4) | |
1832 | "5" 8-bit unsigned immediate (MICROMIPSOP_*_IMM8) | |
1833 | "6" 5-bit unsigned immediate (MICROMIPSOP_*_RS) | |
1834 | "7" 2-bit DSP accumulator register (MICROMIPSOP_*_DSPACC) | |
1835 | "8" 6-bit unsigned immediate (MICROMIPSOP_*_WRDSP) | |
1836 | "0" 6-bit signed immediate (MICROMIPSOP_*_DSPSFT) | |
1837 | "@" 10-bit signed immediate (MICROMIPSOP_*_IMM10) | |
1838 | "^" 5-bit unsigned immediate (MICROMIPSOP_*_RD) | |
1839 | ||
7f3c4072 CM |
1840 | microMIPS Enhanced VA Scheme: |
1841 | "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET) | |
1842 | ||
df58fc94 RS |
1843 | Other: |
1844 | "()" parens surrounding optional value | |
1845 | "," separates operands | |
1846 | "+" start of extension sequence | |
1847 | "m" start of microMIPS extension sequence | |
1848 | ||
1849 | Characters used so far, for quick reference when adding more: | |
03f66e8a MR |
1850 | "12345678 0" |
1851 | "<>(),+.@\^|~" | |
df58fc94 RS |
1852 | "ABCDEFGHI KLMN RST V " |
1853 | "abcd f hijklmnopqrstuvw yz" | |
1854 | ||
1855 | Extension character sequences used so far ("+" followed by the | |
1856 | following), for quick reference when adding more: | |
7f3c4072 | 1857 | "j" |
df58fc94 RS |
1858 | "" |
1859 | "ABCDEFGHI" | |
1860 | "" | |
1861 | ||
1862 | Extension character sequences used so far ("m" followed by the | |
1863 | following), for quick reference when adding more: | |
1864 | "" | |
1865 | "" | |
1866 | " BCDEFGHIJ LMNOPQ U WXYZ" | |
1867 | " bcdefghij lmn pq st xyz" | |
1868 | */ | |
1869 | ||
1870 | extern const struct mips_opcode micromips_opcodes[]; | |
1871 | extern const int bfd_micromips_num_opcodes; | |
1872 | ||
c67a084a NC |
1873 | /* A NOP insn impemented as "or at,at,zero". |
1874 | Used to implement -mfix-loongson2f. */ | |
1875 | #define LOONGSON2F_NOP_INSN 0x00200825 | |
1876 | ||
252b5132 | 1877 | #endif /* _MIPS_H_ */ |