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35c08157 | 1 | /* nds32.h -- Header file for nds32 opcode table |
2571583a | 2 | Copyright (C) 2012-2017 Free Software Foundation, Inc. |
35c08157 KLC |
3 | Contributed by Andes Technology Corporation. |
4 | ||
5 | This program is free software; you can redistribute it and/or modify | |
6 | it under the terms of the GNU General Public License as published by | |
7 | the Free Software Foundation; either version 3, or (at your option) | |
8 | any later version. | |
9 | ||
10 | This program is distributed in the hope that it will be useful, | |
11 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | GNU General Public License for more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License | |
16 | along with this program; if not, write to the Free Software | |
17 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA | |
18 | 02110-1301, USA. */ | |
19 | ||
20 | #ifndef OPCODE_NDS32_H | |
21 | #define OPCODE_NDS32_H | |
22 | ||
23 | /* Registers. */ | |
24 | #define REG_R5 5 | |
25 | #define REG_R8 8 | |
26 | #define REG_R10 10 | |
27 | #define REG_R12 12 | |
28 | #define REG_R15 15 | |
29 | #define REG_R16 16 | |
30 | #define REG_R20 20 | |
31 | #define REG_TA 15 | |
40c7a7cb | 32 | #define REG_TP 27 |
35c08157 KLC |
33 | #define REG_FP 28 |
34 | #define REG_GP 29 | |
35 | #define REG_LP 30 | |
36 | #define REG_SP 31 | |
37 | \f | |
38 | /* Macros for extracting fields or making an instruction. */ | |
609332f1 | 39 | static const int nds32_r45map[] ATTRIBUTE_UNUSED = |
35c08157 KLC |
40 | { |
41 | 0, 1, 2, 3, 4, 5, 6, 7, | |
42 | 8, 9, 10, 11, 16, 17, 18, 19 | |
43 | }; | |
44 | ||
609332f1 | 45 | static const int nds32_r54map[] ATTRIBUTE_UNUSED = |
35c08157 KLC |
46 | { |
47 | 0, 1, 2, 3, 4, 5, 6, 7, | |
48 | 8, 9, 10, 11, -1, -1, -1, -1, | |
49 | 12, 13, 14, 15, -1, -1, -1, -1, | |
50 | -1, -1, -1, -1, -1, -1, -1, -1 | |
51 | }; | |
52 | ||
4ec521f2 KLC |
53 | #define N32_BIT(n) (1 << (n)) |
54 | #define __MASK(n) (N32_BIT (n) - 1) | |
35c08157 KLC |
55 | #define __MF(v, off, bs) (((v) & __MASK (bs)) << (off)) |
56 | #define __GF(v, off, bs) (((v) >> off) & __MASK (bs)) | |
57 | #define __SEXT(v, bs) ((((v) & ((1 << (bs)) - 1)) ^ (1 << ((bs) - 1))) - (1 << ((bs) - 1))) | |
58 | ||
59 | /* Make nds32 instructions. */ | |
60 | ||
61 | #define N32_TYPE4(op6, rt5, ra5, rb5, rd5, sub5) \ | |
62 | (__MF (N32_OP6_##op6, 25, 6) | __MF (rt5, 20, 5) \ | |
63 | | __MF (ra5, 15, 5) | __MF (rb5, 10, 5) \ | |
64 | | __MF (rd5, 5, 5) | __MF (sub5, 0, 5)) | |
65 | #define N32_TYPE3(op6, rt5, ra5, rb5, sub10) \ | |
66 | (N32_TYPE4 (op6, rt5, ra5, rb5, 0, 0) \ | |
67 | | __MF (sub10, 0, 10)) | |
68 | #define N32_TYPE2(op6, rt5, ra5, imm15) \ | |
69 | (N32_TYPE3 (op6, rt5, ra5, 0, 0) | __MF (imm15, 0, 15)) | |
70 | #define N32_TYPE1(op6, rt5, imm20) \ | |
71 | (N32_TYPE2 (op6, rt5, 0, 0) | __MF (imm20, 0, 20)) | |
72 | #define N32_TYPE0(op6, imm25) \ | |
73 | (N32_TYPE1 (op6, 0, 0) | __MF (imm25, 0, 25)) | |
74 | #define N32_ALU1(sub, rt, ra, rb) \ | |
75 | N32_TYPE4 (ALU1, rt, ra, rb, 0, N32_ALU1_##sub) | |
76 | #define N32_ALU1_SH(sub, rt, ra, rb, rd) \ | |
77 | N32_TYPE4 (ALU1, rt, ra, rb, rd, N32_ALU1_##sub) | |
78 | #define N32_ALU2(sub, rt, ra, rb) \ | |
79 | N32_TYPE3 (ALU2, rt, ra, rb, N32_ALU2_##sub) | |
80 | #define N32_BR1(sub, rt, ra, imm14s) \ | |
81 | N32_TYPE2 (BR1, rt, ra, (N32_BR1_##sub << 14) | (imm14s & __MASK (14))) | |
82 | #define N32_BR2(sub, rt, imm16s) \ | |
83 | N32_TYPE1 (BR2, rt, (N32_BR2_##sub << 16) | (imm16s & __MASK (16))) | |
84 | #define N32_BR3(sub, rt, imm11s, imm8s) \ | |
85 | N32_TYPE1 (BR3, rt, (N32_BR3_##sub << 19) \ | |
86 | | ((imm11s & __MASK (11)) << 8) \ | |
87 | | (imm8s & __MASK (8))) | |
88 | #define N32_JI(sub, imm24s) \ | |
89 | N32_TYPE0 (JI, (N32_JI_##sub << 24) | (imm24s & __MASK (24))) | |
90 | #define N32_JREG(sub, rt, rb, dtit, hint) \ | |
91 | N32_TYPE4(JREG, rt, 0, rb, (dtit << 3) | (hint & 7), N32_JREG_##sub) | |
92 | #define N32_MEM(sub, rt, ra, rb, sv) \ | |
93 | N32_TYPE3 (MEM, rt, ra, rb, (sv << 8) | N32_MEM_##sub) | |
94 | ||
95 | #define N16_TYPE55(op5, rt5, ra5) \ | |
96 | (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \ | |
97 | | __MF (ra5, 0, 5)) | |
98 | #define N16_TYPE45(op6, rt4, ra5) \ | |
99 | (0x8000 | __MF (N16_T45_##op6, 9, 6) | __MF (rt4, 5, 4) \ | |
100 | | __MF (ra5, 0, 5)) | |
101 | #define N16_TYPE333(op6, rt3, ra3, rb3) \ | |
102 | (0x8000 | __MF (N16_T333_##op6, 9, 6) | __MF (rt3, 6, 3) \ | |
103 | | __MF (ra3, 3, 3) | __MF (rb3, 0, 3)) | |
104 | #define N16_TYPE36(op6, rt3, imm6) \ | |
105 | (0x8000 | __MF (N16_T36_##op6, 9, 6) | __MF (rt3, 6, 3) \ | |
106 | | __MF (imm6, 0, 6)) | |
107 | #define N16_TYPE38(op4, rt3, imm8) \ | |
108 | (0x8000 | __MF (N16_T38_##op4, 11, 4) | __MF (rt3, 8, 3) \ | |
109 | | __MF (imm8, 0, 8)) | |
110 | #define N16_TYPE37(op4, rt3, ls, imm7) \ | |
111 | (0x8000 | __MF (N16_T37_##op4, 11, 4) | __MF (rt3, 8, 3) \ | |
112 | | __MF (imm7, 0, 7) | __MF (ls, 7, 1)) | |
113 | #define N16_TYPE5(op10, imm5) \ | |
114 | (0x8000 | __MF (N16_T5_##op10, 5, 10) | __MF (imm5, 0, 5)) | |
115 | #define N16_TYPE8(op7, imm8) \ | |
116 | (0x8000 | __MF (N16_T8_##op7, 8, 7) | __MF (imm8, 0, 8)) | |
117 | #define N16_TYPE9(op6, imm9) \ | |
118 | (0x8000 | __MF (N16_T9_##op6, 9, 6) | __MF (imm9, 0, 9)) | |
119 | #define N16_TYPE10(op5, imm10) \ | |
120 | (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10)) | |
121 | #define N16_TYPE25(op8, re, imm5) \ | |
122 | (0x8000 | __MF (N16_T25_##op8, 7, 8) | __MF (re, 5, 2) \ | |
123 | | __MF (imm5, 0, 5)) | |
124 | ||
125 | #define N16_MISC33(sub, rt, ra) \ | |
126 | N16_TYPE333 (MISC33, rt, ra, N16_MISC33_##sub) | |
127 | #define N16_BFMI333(sub, rt, ra) \ | |
128 | N16_TYPE333 (BFMI333, rt, ra, N16_BFMI333_##sub) | |
129 | ||
130 | /* Get instruction fields. | |
131 | ||
132 | Macros used for handling 32-bit and 16-bit instructions are | |
133 | prefixed with N32_ and N16_ respectively. */ | |
134 | ||
135 | #define N32_OP6(insn) (((insn) >> 25) & 0x3f) | |
136 | #define N32_RT5(insn) (((insn) >> 20) & 0x1f) | |
137 | #define N32_RT53(insn) (N32_RT5 (insn) & 0x7) | |
138 | #define N32_RT54(insn) nds32_r54map[N32_RT5 (insn)] | |
139 | #define N32_RA5(insn) (((insn) >> 15) & 0x1f) | |
140 | #define N32_RA53(insn) (N32_RA5 (insn) & 0x7) | |
141 | #define N32_RA54(insn) nds32_r54map[N32_RA5 (insn)] | |
142 | #define N32_RB5(insn) (((insn) >> 10) & 0x1f) | |
143 | #define N32_UB5(insn) (((insn) >> 10) & 0x1f) | |
144 | #define N32_RB53(insn) (N32_RB5 (insn) & 0x7) | |
145 | #define N32_RB54(insn) nds32_r54map[N32_RB5 (insn)] | |
146 | #define N32_RD5(insn) (((insn) >> 5) & 0x1f) | |
147 | #define N32_SH5(insn) (((insn) >> 5) & 0x1f) | |
148 | #define N32_SUB5(insn) (((insn) >> 0) & 0x1f) | |
149 | #define N32_SWID(insn) (((insn) >> 5) & 0x3ff) | |
150 | #define N32_IMMU(insn, bs) ((insn) & __MASK (bs)) | |
151 | #define N32_IMMS(insn, bs) ((signed) __SEXT (((insn) & __MASK (bs)), bs)) | |
152 | #define N32_IMM5U(insn) N32_IMMU (insn, 5) | |
153 | #define N32_IMM12S(insn) N32_IMMS (insn, 12) | |
154 | #define N32_IMM14S(insn) N32_IMMS (insn, 14) | |
155 | #define N32_IMM15U(insn) N32_IMMU (insn, 15) | |
156 | #define N32_IMM15S(insn) N32_IMMS (insn, 15) | |
157 | #define N32_IMM16S(insn) N32_IMMS (insn, 16) | |
158 | #define N32_IMM17S(insn) N32_IMMS (insn, 17) | |
159 | #define N32_IMM20S(insn) N32_IMMS (insn, 20) | |
160 | #define N32_IMM20U(insn) N32_IMMU (insn, 20) | |
161 | #define N32_IMM24S(insn) N32_IMMS (insn, 24) | |
162 | ||
163 | #define N16_RT5(insn) (((insn) >> 5) & 0x1f) | |
164 | #define N16_RT4(insn) nds32_r45map[(((insn) >> 5) & 0xf)] | |
165 | #define N16_RT3(insn) (((insn) >> 6) & 0x7) | |
166 | #define N16_RT38(insn) (((insn) >> 8) & 0x7) | |
167 | #define N16_RT8(insn) (((insn) >> 8) & 0x7) | |
168 | #define N16_RA5(insn) ((insn) & 0x1f) | |
169 | #define N16_RA3(insn) (((insn) >> 3) & 0x7) | |
170 | #define N16_RB3(insn) ((insn) & 0x7) | |
171 | #define N16_IMM3U(insn) N32_IMMU (insn, 3) | |
172 | #define N16_IMM5U(insn) N32_IMMU (insn, 5) | |
173 | #define N16_IMM5S(insn) N32_IMMS (insn, 5) | |
174 | #define N16_IMM6U(insn) N32_IMMU (insn, 6) | |
175 | #define N16_IMM7U(insn) N32_IMMU (insn, 7) | |
176 | #define N16_IMM8S(insn) N32_IMMS (insn, 8) | |
177 | #define N16_IMM9U(insn) N32_IMMU (insn, 9) | |
178 | #define N16_IMM10S(insn) N32_IMMS (insn, 10) | |
179 | ||
180 | #define IS_WITHIN_U(v, n) (((v) >> n) == 0) | |
181 | #define IS_WITHIN_S(v, n) IS_WITHIN_U ((v) + (1 << ((n) - 1)), n) | |
182 | ||
183 | /* Get fields for specific instruction. */ | |
184 | #define N32_JREG_T(insn) (((insn) >> 8) & 0x3) | |
185 | #define N32_JREG_HINT(insn) (((insn) >> 5) & 0x7) | |
186 | #define N32_BR2_SUB(insn) (((insn) >> 16) & 0xf) | |
187 | #define N32_COP_SUB(insn) ((insn) & 0xf) | |
188 | #define N32_COP_CP(insn) (((insn) >> 4) & 0x3) | |
189 | ||
190 | /* Check fields. */ | |
191 | #define N32_IS_RT3(insn) (N32_RT5 (insn) < 8) | |
192 | #define N32_IS_RA3(insn) (N32_RA5 (insn) < 8) | |
193 | #define N32_IS_RB3(insn) (N32_RB5 (insn) < 8) | |
194 | #define N32_IS_RT4(insn) (nds32_r54map[N32_RT5 (insn)] != -1) | |
195 | #define N32_IS_RA4(insn) (nds32_r54map[N32_RA5 (insn)] != -1) | |
196 | #define N32_IS_RB4(insn) (nds32_r54map[N32_RB5 (insn)] != -1) | |
197 | ||
198 | ||
199 | /* These are opcodes for Nxx_TYPE macros. | |
200 | They are prefixed by corresponding TYPE to avoid misusing. */ | |
201 | ||
202 | enum n32_opcodes | |
203 | { | |
204 | /* Main opcodes (OP6). */ | |
205 | ||
206 | N32_OP6_LBI = 0x0, | |
207 | N32_OP6_LHI, | |
208 | N32_OP6_LWI, | |
209 | N32_OP6_LDI, | |
210 | N32_OP6_LBI_BI, | |
211 | N32_OP6_LHI_BI, | |
212 | N32_OP6_LWI_BI, | |
213 | N32_OP6_LDI_BI, | |
214 | ||
215 | N32_OP6_SBI = 0x8, | |
216 | N32_OP6_SHI, | |
217 | N32_OP6_SWI, | |
218 | N32_OP6_SDI, | |
219 | N32_OP6_SBI_BI, | |
220 | N32_OP6_SHI_BI, | |
221 | N32_OP6_SWI_BI, | |
222 | N32_OP6_SDI_BI, | |
223 | ||
224 | N32_OP6_LBSI = 0x10, | |
225 | N32_OP6_LHSI, | |
226 | N32_OP6_LWSI, | |
227 | N32_OP6_DPREFI, | |
228 | N32_OP6_LBSI_BI, | |
229 | N32_OP6_LHSI_BI, | |
230 | N32_OP6_LWSI_BI, | |
231 | N32_OP6_LBGP, | |
232 | ||
233 | N32_OP6_LWC = 0x18, | |
234 | N32_OP6_SWC, | |
235 | N32_OP6_LDC, | |
236 | N32_OP6_SDC, | |
237 | N32_OP6_MEM, | |
238 | N32_OP6_LSMW, | |
239 | N32_OP6_HWGP, | |
240 | N32_OP6_SBGP, | |
241 | ||
242 | N32_OP6_ALU1 = 0x20, | |
243 | N32_OP6_ALU2, | |
244 | N32_OP6_MOVI, | |
245 | N32_OP6_SETHI, | |
246 | N32_OP6_JI, | |
247 | N32_OP6_JREG, | |
248 | N32_OP6_BR1, | |
249 | N32_OP6_BR2, | |
250 | ||
251 | N32_OP6_ADDI = 0x28, | |
252 | N32_OP6_SUBRI, | |
253 | N32_OP6_ANDI, | |
254 | N32_OP6_XORI, | |
255 | N32_OP6_ORI, | |
256 | N32_OP6_BR3, | |
257 | N32_OP6_SLTI, | |
258 | N32_OP6_SLTSI, | |
259 | ||
260 | N32_OP6_AEXT = 0x30, | |
261 | N32_OP6_CEXT, | |
262 | N32_OP6_MISC, | |
263 | N32_OP6_BITCI, | |
264 | N32_OP6_0x34, | |
265 | N32_OP6_COP, | |
266 | N32_OP6_0x36, | |
267 | N32_OP6_0x37, | |
268 | ||
269 | N32_OP6_SIMD = 0x38, | |
270 | ||
271 | /* Sub-opcodes of specific opcode. */ | |
272 | ||
273 | /* bit-24 */ | |
274 | N32_BR1_BEQ = 0, | |
275 | N32_BR1_BNE = 1, | |
276 | ||
277 | /* bit[16:19] */ | |
278 | N32_BR2_IFCALL = 0, | |
279 | N32_BR2_BEQZ = 2, | |
280 | N32_BR2_BNEZ = 3, | |
281 | N32_BR2_BGEZ = 4, | |
282 | N32_BR2_BLTZ = 5, | |
283 | N32_BR2_BGTZ = 6, | |
284 | N32_BR2_BLEZ = 7, | |
285 | N32_BR2_BGEZAL = 0xc, | |
286 | N32_BR2_BLTZAL = 0xd, | |
287 | ||
288 | /* bit-19 */ | |
289 | N32_BR3_BEQC = 0, | |
290 | N32_BR3_BNEC = 1, | |
291 | ||
292 | /* bit-24 */ | |
293 | N32_JI_J = 0, | |
294 | N32_JI_JAL = 1, | |
295 | ||
296 | /* bit[0:4] */ | |
297 | N32_JREG_JR = 0, | |
298 | N32_JREG_JRAL = 1, | |
299 | N32_JREG_JRNEZ = 2, | |
300 | N32_JREG_JRALNEZ = 3, | |
301 | ||
302 | /* bit[0:4] */ | |
303 | N32_ALU1_ADD_SLLI = 0x0, | |
304 | N32_ALU1_SUB_SLLI, | |
305 | N32_ALU1_AND_SLLI, | |
306 | N32_ALU1_XOR_SLLI, | |
307 | N32_ALU1_OR_SLLI, | |
308 | N32_ALU1_ADD = 0x0, | |
309 | N32_ALU1_SUB, | |
310 | N32_ALU1_AND, | |
311 | N32_ALU1_XOR, | |
312 | N32_ALU1_OR, | |
313 | N32_ALU1_NOR, | |
314 | N32_ALU1_SLT, | |
315 | N32_ALU1_SLTS, | |
316 | N32_ALU1_SLLI = 0x8, | |
317 | N32_ALU1_SRLI, | |
318 | N32_ALU1_SRAI, | |
319 | N32_ALU1_ROTRI, | |
320 | N32_ALU1_SLL, | |
321 | N32_ALU1_SRL, | |
322 | N32_ALU1_SRA, | |
323 | N32_ALU1_ROTR, | |
324 | N32_ALU1_SEB = 0x10, | |
325 | N32_ALU1_SEH, | |
326 | N32_ALU1_BITC, | |
327 | N32_ALU1_ZEH, | |
328 | N32_ALU1_WSBH, | |
329 | N32_ALU1_OR_SRLI, | |
330 | N32_ALU1_DIVSR, | |
331 | N32_ALU1_DIVR, | |
332 | N32_ALU1_SVA = 0x18, | |
333 | N32_ALU1_SVS, | |
334 | N32_ALU1_CMOVZ, | |
335 | N32_ALU1_CMOVN, | |
336 | N32_ALU1_ADD_SRLI, | |
337 | N32_ALU1_SUB_SRLI, | |
338 | N32_ALU1_AND_SRLI, | |
339 | N32_ALU1_XOR_SRLI, | |
340 | ||
341 | /* bit[0:5], where bit[6:9] == 0 */ | |
342 | N32_ALU2_MAX = 0, | |
343 | N32_ALU2_MIN, | |
344 | N32_ALU2_AVE, | |
345 | N32_ALU2_ABS, | |
346 | N32_ALU2_CLIPS, | |
347 | N32_ALU2_CLIP, | |
348 | N32_ALU2_CLO, | |
349 | N32_ALU2_CLZ, | |
350 | N32_ALU2_BSET = 0x8, | |
351 | N32_ALU2_BCLR, | |
352 | N32_ALU2_BTGL, | |
353 | N32_ALU2_BTST, | |
354 | N32_ALU2_BSE, | |
355 | N32_ALU2_BSP, | |
356 | N32_ALU2_FFB, | |
357 | N32_ALU2_FFMISM, | |
358 | N32_ALU2_ADD_SC = 0x10, | |
359 | N32_ALU2_SUB_SC, | |
360 | N32_ALU2_ADD_WC, | |
361 | N32_ALU2_SUB_WC, | |
40c7a7cb | 362 | N32_ALU2_KMxy, |
35c08157 KLC |
363 | N32_ALU2_0x15, |
364 | N32_ALU2_0x16, | |
365 | N32_ALU2_FFZMISM, | |
40c7a7cb KLC |
366 | N32_ALU2_KADD = 0x18, |
367 | N32_ALU2_KSUB, | |
368 | N32_ALU2_KSLRA, | |
35c08157 KLC |
369 | N32_ALU2_MFUSR = 0x20, |
370 | N32_ALU2_MTUSR, | |
371 | N32_ALU2_0x22, | |
372 | N32_ALU2_0x23, | |
373 | N32_ALU2_MUL, | |
374 | N32_ALU2_0x25, | |
375 | N32_ALU2_0x26, | |
376 | N32_ALU2_MULTS64 = 0x28, | |
377 | N32_ALU2_MULT64, | |
378 | N32_ALU2_MADDS64, | |
379 | N32_ALU2_MADD64, | |
380 | N32_ALU2_MSUBS64, | |
381 | N32_ALU2_MSUB64, | |
382 | N32_ALU2_DIVS, | |
383 | N32_ALU2_DIV, | |
384 | N32_ALU2_0x30 = 0x30, | |
385 | N32_ALU2_MULT32, | |
386 | N32_ALU2_0x32, | |
387 | N32_ALU2_MADD32, | |
388 | N32_ALU2_0x34, | |
389 | N32_ALU2_MSUB32, | |
390 | ||
391 | /* bit[0:5], where bit[6:9] != 0 */ | |
392 | N32_ALU2_FFBI = 0xe, | |
393 | N32_ALU2_FLMISM = 0xf, | |
394 | N32_ALU2_MULSR64 = 0x28, | |
395 | N32_ALU2_MULR64 = 0x29, | |
396 | N32_ALU2_MADDR32 = 0x33, | |
397 | N32_ALU2_MSUBR32 = 0x35, | |
398 | ||
399 | /* bit[0:5] */ | |
400 | N32_MEM_LB = 0, | |
401 | N32_MEM_LH, | |
402 | N32_MEM_LW, | |
403 | N32_MEM_LD, | |
404 | N32_MEM_LB_BI, | |
405 | N32_MEM_LH_BI, | |
406 | N32_MEM_LW_BI, | |
407 | N32_MEM_LD_BI, | |
408 | N32_MEM_SB, | |
409 | N32_MEM_SH, | |
410 | N32_MEM_SW, | |
411 | N32_MEM_SD, | |
412 | N32_MEM_SB_BI, | |
413 | N32_MEM_SH_BI, | |
414 | N32_MEM_SW_BI, | |
415 | N32_MEM_SD_BI, | |
416 | N32_MEM_LBS, | |
417 | N32_MEM_LHS, | |
418 | N32_MEM_LWS, /* Not used. */ | |
419 | N32_MEM_DPREF, | |
420 | N32_MEM_LBS_BI, | |
421 | N32_MEM_LHS_BI, | |
422 | N32_MEM_LWS_BI, /* Not used. */ | |
423 | N32_MEM_0x17, /* Not used. */ | |
424 | N32_MEM_LLW, | |
425 | N32_MEM_SCW, | |
426 | N32_MEM_LBUP = 0x20, | |
427 | N32_MEM_LWUP = 0x22, | |
428 | N32_MEM_SBUP = 0x28, | |
429 | N32_MEM_SWUP = 0x2a, | |
430 | ||
431 | /* bit[0:1] */ | |
432 | N32_LSMW_LSMW = 0, | |
433 | N32_LSMW_LSMWA, | |
434 | N32_LSMW_LSMWZB, | |
435 | ||
436 | /* bit[2:4] */ | |
437 | N32_LSMW_BI = 0, | |
438 | N32_LSMW_BIM, | |
439 | N32_LSMW_BD, | |
440 | N32_LSMW_BDM, | |
441 | N32_LSMW_AI, | |
442 | N32_LSMW_AIM, | |
443 | N32_LSMW_AD, | |
444 | N32_LSMW_ADM, | |
445 | ||
446 | /* bit[0:4] */ | |
447 | N32_MISC_STANDBY = 0, | |
448 | N32_MISC_CCTL, | |
449 | N32_MISC_MFSR, | |
450 | N32_MISC_MTSR, | |
451 | N32_MISC_IRET, | |
452 | N32_MISC_TRAP, | |
453 | N32_MISC_TEQZ, | |
454 | N32_MISC_TNEZ, | |
455 | N32_MISC_DSB = 0x8, | |
456 | N32_MISC_ISB, | |
457 | N32_MISC_BREAK, | |
458 | N32_MISC_SYSCALL, | |
459 | N32_MISC_MSYNC, | |
460 | N32_MISC_ISYNC, | |
461 | N32_MISC_TLBOP, | |
462 | N32_MISC_0xf, | |
463 | ||
40c7a7cb | 464 | /* bit[0:4] */ |
35c08157 KLC |
465 | N32_SIMD_PBSAD = 0, |
466 | N32_SIMD_PBSADA = 1, | |
467 | ||
468 | /* bit[0:3] */ | |
469 | N32_COP_CPE1 = 0, | |
470 | N32_COP_MFCP, | |
471 | N32_COP_CPLW, | |
472 | N32_COP_CPLD, | |
473 | N32_COP_CPE2, | |
474 | N32_COP_CPE3 = 8, | |
475 | N32_COP_MTCP, | |
476 | N32_COP_CPSW, | |
477 | N32_COP_CPSD, | |
478 | N32_COP_CPE4, | |
479 | ||
480 | /* cop/0 b[3:0] */ | |
481 | N32_FPU_FS1 = 0, | |
482 | N32_FPU_MFCP, | |
483 | N32_FPU_FLS, | |
484 | N32_FPU_FLD, | |
485 | N32_FPU_FS2, | |
486 | N32_FPU_FD1 = 8, | |
487 | N32_FPU_MTCP, | |
488 | N32_FPU_FSS, | |
489 | N32_FPU_FSD, | |
490 | N32_FPU_FD2, | |
491 | ||
492 | /* FS1 b[9:6] */ | |
493 | N32_FPU_FS1_FADDS = 0, | |
494 | N32_FPU_FS1_FSUBS, | |
495 | N32_FPU_FS1_FCPYNSS, | |
496 | N32_FPU_FS1_FCPYSS, | |
497 | N32_FPU_FS1_FMADDS, | |
498 | N32_FPU_FS1_FMSUBS, | |
499 | N32_FPU_FS1_FCMOVNS, | |
500 | N32_FPU_FS1_FCMOVZS, | |
501 | N32_FPU_FS1_FNMADDS, | |
502 | N32_FPU_FS1_FNMSUBS, | |
503 | N32_FPU_FS1_10, | |
504 | N32_FPU_FS1_11, | |
505 | N32_FPU_FS1_FMULS = 12, | |
506 | N32_FPU_FS1_FDIVS, | |
507 | N32_FPU_FS1_14, | |
508 | N32_FPU_FS1_F2OP = 15, | |
509 | ||
510 | /* FS1/F2OP b[14:10] */ | |
511 | N32_FPU_FS1_F2OP_FS2D = 0x00, | |
512 | N32_FPU_FS1_F2OP_FSQRTS = 0x01, | |
513 | N32_FPU_FS1_F2OP_FABSS = 0x05, | |
514 | N32_FPU_FS1_F2OP_FUI2S = 0x08, | |
515 | N32_FPU_FS1_F2OP_FSI2S = 0x0c, | |
516 | N32_FPU_FS1_F2OP_FS2UI = 0x10, | |
517 | N32_FPU_FS1_F2OP_FS2UI_Z = 0x14, | |
518 | N32_FPU_FS1_F2OP_FS2SI = 0x18, | |
519 | N32_FPU_FS1_F2OP_FS2SI_Z = 0x1c, | |
520 | ||
521 | /* FS2 b[9:6] */ | |
522 | N32_FPU_FS2_FCMPEQS = 0x0, | |
523 | N32_FPU_FS2_FCMPLTS = 0x2, | |
524 | N32_FPU_FS2_FCMPLES = 0x4, | |
525 | N32_FPU_FS2_FCMPUNS = 0x6, | |
526 | N32_FPU_FS2_FCMPEQS_E = 0x1, | |
527 | N32_FPU_FS2_FCMPLTS_E = 0x3, | |
528 | N32_FPU_FS2_FCMPLES_E = 0x5, | |
529 | N32_FPU_FS2_FCMPUNS_E = 0x7, | |
530 | ||
531 | /* FD1 b[9:6] */ | |
532 | N32_FPU_FD1_FADDD = 0, | |
533 | N32_FPU_FD1_FSUBD, | |
534 | N32_FPU_FD1_FCPYNSD, | |
535 | N32_FPU_FD1_FCPYSD, | |
536 | N32_FPU_FD1_FMADDD, | |
537 | N32_FPU_FD1_FMSUBD, | |
538 | N32_FPU_FD1_FCMOVND, | |
539 | N32_FPU_FD1_FCMOVZD, | |
540 | N32_FPU_FD1_FNMADDD, | |
541 | N32_FPU_FD1_FNMSUBD, | |
542 | N32_FPU_FD1_10, | |
543 | N32_FPU_FD1_11, | |
544 | N32_FPU_FD1_FMULD = 12, | |
545 | N32_FPU_FD1_FDIVD, | |
546 | N32_FPU_FD1_14, | |
547 | N32_FPU_FD1_F2OP = 15, | |
548 | ||
549 | /* FD1/F2OP b[14:10] */ | |
550 | N32_FPU_FD1_F2OP_FD2S = 0x00, | |
551 | N32_FPU_FD1_F2OP_FSQRTD = 0x01, | |
552 | N32_FPU_FD1_F2OP_FABSD = 0x05, | |
553 | N32_FPU_FD1_F2OP_FUI2D = 0x08, | |
554 | N32_FPU_FD1_F2OP_FSI2D = 0x0c, | |
555 | N32_FPU_FD1_F2OP_FD2UI = 0x10, | |
556 | N32_FPU_FD1_F2OP_FD2UI_Z = 0x14, | |
557 | N32_FPU_FD1_F2OP_FD2SI = 0x18, | |
558 | N32_FPU_FD1_F2OP_FD2SI_Z = 0x1c, | |
559 | ||
560 | /* FD2 b[9:6] */ | |
561 | N32_FPU_FD2_FCMPEQD = 0x0, | |
562 | N32_FPU_FD2_FCMPLTD = 0x2, | |
563 | N32_FPU_FD2_FCMPLED = 0x4, | |
564 | N32_FPU_FD2_FCMPUND = 0x6, | |
565 | N32_FPU_FD2_FCMPEQD_E = 0x1, | |
566 | N32_FPU_FD2_FCMPLTD_E = 0x3, | |
567 | N32_FPU_FD2_FCMPLED_E = 0x5, | |
568 | N32_FPU_FD2_FCMPUND_E = 0x7, | |
569 | ||
570 | /* MFCP b[9:6] */ | |
571 | N32_FPU_MFCP_FMFSR = 0x0, | |
572 | N32_FPU_MFCP_FMFDR = 0x1, | |
573 | N32_FPU_MFCP_XR = 0xc, | |
574 | ||
575 | /* MFCP/XR b[14:10] */ | |
576 | N32_FPU_MFCP_XR_FMFCFG = 0x0, | |
577 | N32_FPU_MFCP_XR_FMFCSR = 0x1, | |
578 | ||
579 | /* MTCP b[9:6] */ | |
580 | N32_FPU_MTCP_FMTSR = 0x0, | |
581 | N32_FPU_MTCP_FMTDR = 0x1, | |
582 | N32_FPU_MTCP_XR = 0xc, | |
583 | ||
584 | /* MTCP/XR b[14:10] */ | |
585 | N32_FPU_MTCP_XR_FMTCSR = 0x1 | |
586 | }; | |
587 | ||
588 | enum n16_opcodes | |
589 | { | |
590 | N16_T55_MOV55 = 0x0, | |
591 | N16_T55_MOVI55 = 0x1, | |
592 | ||
593 | N16_T45_0 = 0, | |
594 | N16_T45_ADD45 = 0x4, | |
595 | N16_T45_SUB45 = 0x5, | |
596 | N16_T45_ADDI45 = 0x6, | |
597 | N16_T45_SUBI45 = 0x7, | |
598 | N16_T45_SRAI45 = 0x8, | |
599 | N16_T45_SRLI45 = 0x9, | |
600 | N16_T45_LWI45_FE = 0x19, | |
601 | N16_T45_LWI450 = 0x1a, | |
602 | N16_T45_SWI450 = 0x1b, | |
603 | N16_T45_SLTS45 = 0x30, | |
604 | N16_T45_SLT45 = 0x31, | |
605 | N16_T45_SLTSI45 = 0x32, | |
606 | N16_T45_SLTI45 = 0x33, | |
607 | N16_T45_MOVPI45 = 0x3d, | |
608 | ||
609 | N15_T44_MOVD44 = 0x7d, | |
610 | ||
611 | N16_T333_0 = 0, | |
612 | N16_T333_SLLI333 = 0xa, | |
613 | N16_T333_BFMI333 = 0xb, | |
614 | N16_T333_ADD333 = 0xc, | |
615 | N16_T333_SUB333 = 0xd, | |
616 | N16_T333_ADDI333 = 0xe, | |
617 | N16_T333_SUBI333 = 0xf, | |
618 | N16_T333_LWI333 = 0x10, | |
619 | N16_T333_LWI333_BI = 0x11, | |
620 | N16_T333_LHI333 = 0x12, | |
621 | N16_T333_LBI333 = 0x13, | |
622 | N16_T333_SWI333 = 0x14, | |
623 | N16_T333_SWI333_BI = 0x15, | |
624 | N16_T333_SHI333 = 0x16, | |
625 | N16_T333_SBI333 = 0x17, | |
626 | N16_T333_MISC33 = 0x3f, | |
627 | ||
628 | N16_T36_ADDRI36_SP = 0x18, | |
629 | ||
630 | N16_T37_XWI37 = 0x7, | |
631 | N16_T37_XWI37SP = 0xe, | |
632 | ||
633 | N16_T38_BEQZ38 = 0x8, | |
634 | N16_T38_BNEZ38 = 0x9, | |
635 | N16_T38_BEQS38 = 0xa, | |
636 | N16_T38_BNES38 = 0xb, | |
637 | ||
638 | N16_T5_JR5 = 0x2e8, | |
639 | N16_T5_JRAL5 = 0x2e9, | |
640 | N16_T5_EX9IT = 0x2ea, | |
641 | /* 0x2eb reserved. */ | |
642 | N16_T5_RET5 = 0x2ec, | |
643 | N16_T5_ADD5PC = 0x2ed, | |
644 | /* 0x2e[ef] reserved. */ | |
645 | N16_T5_BREAK16 = 0x350, | |
646 | ||
647 | N16_T8_J8 = 0x55, | |
648 | N16_T8_BEQZS8 = 0x68, | |
649 | N16_T8_BNEZS8 = 0x69, | |
650 | ||
651 | /* N16_T9_BREAK16 = 0x35 | |
652 | Since v3, SWID of BREAK16 above 32 are used for encoding EX9.IT. */ | |
653 | N16_T9_EX9IT = 0x35, | |
654 | N16_T9_IFCALL9 = 0x3c, | |
655 | ||
656 | N16_T10_ADDI10S = 0x1b, | |
657 | ||
658 | N16_T25_PUSH25 = 0xf8, | |
659 | N16_T25_POP25 = 0xf9, | |
660 | ||
661 | /* Sub-opcodes. */ | |
662 | N16_MISC33_0 = 0, | |
663 | N16_MISC33_1 = 1, | |
664 | N16_MISC33_NEG33 = 2, | |
665 | N16_MISC33_NOT33 = 3, | |
666 | N16_MISC33_MUL33 = 4, | |
667 | N16_MISC33_XOR33 = 5, | |
668 | N16_MISC33_AND33 = 6, | |
669 | N16_MISC33_OR33 = 7, | |
670 | ||
671 | N16_BFMI333_ZEB33 = 0, | |
672 | N16_BFMI333_ZEH33 = 1, | |
673 | N16_BFMI333_SEB33 = 2, | |
674 | N16_BFMI333_SEH33 = 3, | |
675 | N16_BFMI333_XLSB33 = 4, | |
676 | N16_BFMI333_X11B33 = 5, | |
677 | N16_BFMI333_BMSKI33 = 6, | |
678 | N16_BFMI333_FEXTI33 = 7 | |
679 | }; | |
680 | \f | |
681 | /* These macros a deprecated. DO NOT use them anymore. | |
682 | And please help rewrite code used them. */ | |
683 | ||
684 | /* 32-bit instructions without operands. */ | |
685 | #define INSN_SETHI 0x46000000 | |
686 | #define INSN_ORI 0x58000000 | |
687 | #define INSN_JR 0x4a000000 | |
688 | #define INSN_RET 0x4a000020 | |
689 | #define INSN_JAL 0x49000000 | |
690 | #define INSN_J 0x48000000 | |
691 | #define INSN_JRAL 0x4a000001 | |
692 | #define INSN_BGEZAL 0x4e0c0000 | |
693 | #define INSN_BLTZAL 0x4e0d0000 | |
694 | #define INSN_BEQ 0x4c000000 | |
695 | #define INSN_BNE 0x4c004000 | |
696 | #define INSN_BEQZ 0x4e020000 | |
697 | #define INSN_BNEZ 0x4e030000 | |
698 | #define INSN_BGEZ 0x4e040000 | |
699 | #define INSN_BLTZ 0x4e050000 | |
700 | #define INSN_BGTZ 0x4e060000 | |
701 | #define INSN_BLEZ 0x4e070000 | |
702 | #define INSN_MOVI 0x44000000 | |
703 | #define INSN_ADDI 0x50000000 | |
704 | #define INSN_ANDI 0x54000000 | |
705 | #define INSN_LDI 0x06000000 | |
706 | #define INSN_SDI 0x16000000 | |
707 | #define INSN_LWI 0x04000000 | |
708 | #define INSN_LWSI 0x24000000 | |
709 | #define INSN_LWIP 0x0c000000 | |
710 | #define INSN_LHI 0x02000000 | |
711 | #define INSN_LHSI 0x22000000 | |
712 | #define INSN_LBI 0x00000000 | |
713 | #define INSN_LBSI 0x20000000 | |
714 | #define INSN_SWI 0x14000000 | |
715 | #define INSN_SWIP 0x1c000000 | |
716 | #define INSN_SHI 0x12000000 | |
717 | #define INSN_SBI 0x10000000 | |
718 | #define INSN_SLTI 0x5c000000 | |
719 | #define INSN_SLTSI 0x5e000000 | |
720 | #define INSN_ADD 0x40000000 | |
721 | #define INSN_SUB 0x40000001 | |
722 | #define INSN_SLT 0x40000006 | |
723 | #define INSN_SLTS 0x40000007 | |
724 | #define INSN_SLLI 0x40000008 | |
725 | #define INSN_SRLI 0x40000009 | |
726 | #define INSN_SRAI 0x4000000a | |
727 | #define INSN_SEB 0x40000010 | |
728 | #define INSN_SEH 0x40000011 | |
729 | #define INSN_ZEB INSN_ANDI + 0xFF | |
730 | #define INSN_ZEH 0x40000013 | |
731 | #define INSN_BREAK 0x6400000a | |
732 | #define INSN_NOP 0x40000009 | |
733 | #define INSN_FLSI 0x30000000 | |
734 | #define INSN_FSSI 0x32000000 | |
735 | #define INSN_FLDI 0x34000000 | |
736 | #define INSN_FSDI 0x36000000 | |
737 | #define INSN_BEQC 0x5a000000 | |
738 | #define INSN_BNEC 0x5a080000 | |
739 | #define INSN_DSB 0x64000008 | |
740 | #define INSN_IFCALL 0x4e000000 | |
741 | #define INSN_IFRET 0x4a000060 | |
742 | #define INSN_BR1 0x4c000000 | |
743 | #define INSN_BR2 0x4e000000 | |
744 | ||
745 | /* 16-bit instructions without operand. */ | |
746 | #define INSN_MOV55 0x8000 | |
747 | #define INSN_MOVI55 0x8400 | |
748 | #define INSN_ADD45 0x8800 | |
749 | #define INSN_SUB45 0x8a00 | |
750 | #define INSN_ADDI45 0x8c00 | |
751 | #define INSN_SUBI45 0x8e00 | |
752 | #define INSN_SRAI45 0x9000 | |
753 | #define INSN_SRLI45 0x9200 | |
754 | #define INSN_SLLI333 0x9400 | |
755 | #define INSN_BFMI333 0x9600 | |
756 | #define INSN_ADD333 0x9800 | |
757 | #define INSN_SUB333 0x9a00 | |
758 | #define INSN_ADDI333 0x9c00 | |
759 | #define INSN_SUBI333 0x9e00 | |
760 | #define INSN_LWI333 0xa000 | |
761 | #define INSN_LWI333P 0xa200 | |
762 | #define INSN_LHI333 0xa400 | |
763 | #define INSN_LBI333 0xa600 | |
764 | #define INSN_SWI333 0xa800 | |
765 | #define INSN_SWI333P 0xaa00 | |
766 | #define INSN_SHI333 0xac00 | |
767 | #define INSN_SBI333 0xae00 | |
768 | #define INSN_RSV01 0xb000 | |
769 | #define INSN_RSV02 0xb200 | |
770 | #define INSN_LWI450 0xb400 | |
771 | #define INSN_SWI450 0xb600 | |
772 | #define INSN_LWI37 0xb800 | |
773 | #define INSN_SWI37 0xb880 | |
774 | #define INSN_BEQZ38 0xc000 | |
775 | #define INSN_BNEZ38 0xc800 | |
776 | #define INSN_BEQS38 0xd000 | |
777 | #define INSN_J8 0xd500 | |
778 | #define INSN_BNES38 0xd800 | |
779 | #define INSN_JR5 0xdd00 | |
780 | #define INSN_RET5 0xdd80 | |
781 | #define INSN_JRAL5 0xdd20 | |
782 | #define INSN_EX9_IT_2 0xdd40 | |
783 | #define INSN_SLTS45 0xe000 | |
784 | #define INSN_SLT45 0xe200 | |
785 | #define INSN_SLTSI45 0xe400 | |
786 | #define INSN_SLTI45 0xe600 | |
787 | #define INSN_BEQZS8 0xe800 | |
788 | #define INSN_BNEZS8 0xe900 | |
789 | #define INSN_BREAK16 0xea00 | |
790 | #define INSN_EX9_IT_1 0xea00 | |
791 | #define INSN_NOP16 0x9200 | |
792 | /* 16-bit version 2. */ | |
793 | #define INSN_ADDI10_SP 0xec00 | |
794 | #define INSN_LWI37SP 0xf000 | |
795 | #define INSN_SWI37SP 0xf080 | |
796 | /* 16-bit version 3. */ | |
797 | #define INSN_IFRET16 0x83ff | |
798 | #define INSN_ADDRI36_SP 0xb000 | |
799 | #define INSN_LWI45_FE 0xb200 | |
800 | #define INSN_IFCALL9 0xf800 | |
801 | #define INSN_MISC33 0xfe00 | |
802 | ||
803 | /* Instruction with specific operands. */ | |
804 | #define INSN_ADDI_GP_TO_FP 0x51cd8000 /* BASELINE_V1. */ | |
805 | #define INSN_ADDIGP_TO_FP 0x3fc80000 /* BASELINE_V2. */ | |
806 | #define INSN_MOVI_TO_FP 0x45c00000 | |
807 | #define INSN_MFUSR_PC 0x420F8020 | |
808 | #define INSN_MFUSR_PC_MASK 0xFE0FFFFF | |
809 | ||
810 | /* Instructions use $ta register as operand. */ | |
811 | #define INSN_SETHI_TA (INSN_SETHI | (REG_TA << 20)) | |
812 | #define INSN_ORI_TA (INSN_ORI | (REG_TA << 20) | (REG_TA << 15)) | |
813 | #define INSN_ADD_TA (INSN_ADD | (REG_TA << 20)) | |
814 | #define INSN_ADD45_TA (INSN_ADD45 | (REG_TA << 5)) | |
815 | #define INSN_JR5_TA (INSN_JR5 | (REG_TA << 0)) | |
816 | #define INSN_RET5_TA (INSN_RET5 | (REG_TA << 0)) | |
817 | #define INSN_JR_TA (INSN_JR | (REG_TA << 10)) | |
818 | #define INSN_RET_TA (INSN_RET | (REG_TA << 10)) | |
819 | #define INSN_JRAL_TA (INSN_JRAL | (REG_LP << 20) | (REG_TA << 10)) | |
820 | #define INSN_JRAL5_TA (INSN_JRAL5 | (REG_TA << 0)) | |
821 | #define INSN_BEQZ_TA (INSN_BEQZ | (REG_TA << 20)) | |
822 | #define INSN_BNEZ_TA (INSN_BNEZ | (REG_TA << 20)) | |
823 | #define INSN_MOVI_TA (INSN_MOVI | (REG_TA << 20)) | |
824 | #define INSN_BEQ_TA (INSN_BEQ | (REG_TA << 15)) | |
825 | #define INSN_BNE_TA (INSN_BNE | (REG_TA << 15)) | |
826 | ||
827 | /* Instructions use $r5 register as operand. */ | |
828 | #define INSN_BNE_R5 (INSN_BNE | (REG_R5 << 15)) | |
829 | #define INSN_BEQ_R5 (INSN_BEQ | (REG_R5 << 15)) | |
830 | ||
831 | #endif |