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96ba4233 | 1 | /* Nios II R1 opcode list for GAS, the GNU assembler. |
219d1afa | 2 | Copyright (C) 2013-2018 Free Software Foundation, Inc. |
96ba4233 SL |
3 | Contributed by Mentor Graphics, Inc. |
4 | ||
a1aa5e81 | 5 | This file is part of the GNU opcodes library. |
96ba4233 SL |
6 | |
7 | GAS/GDB is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS/GDB is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS or GDB; see the file COPYING3. If not, write to | |
19 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, | |
20 | Boston, MA 02110-1301, USA. */ | |
21 | ||
22 | #ifndef _NIOS2R1_H_ | |
23 | #define _NIOS2R1_H_ | |
24 | ||
25 | /* R1 fields. */ | |
26 | #define IW_R1_OP_LSB 0 | |
27 | #define IW_R1_OP_SIZE 6 | |
28 | #define IW_R1_OP_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R1_OP_SIZE)) | |
29 | #define IW_R1_OP_SHIFTED_MASK (IW_R1_OP_UNSHIFTED_MASK << IW_R1_OP_LSB) | |
30 | #define GET_IW_R1_OP(W) (((W) >> IW_R1_OP_LSB) & IW_R1_OP_UNSHIFTED_MASK) | |
31 | #define SET_IW_R1_OP(V) (((V) & IW_R1_OP_UNSHIFTED_MASK) << IW_R1_OP_LSB) | |
32 | ||
33 | #define IW_I_A_LSB 27 | |
34 | #define IW_I_A_SIZE 5 | |
35 | #define IW_I_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I_A_SIZE)) | |
36 | #define IW_I_A_SHIFTED_MASK (IW_I_A_UNSHIFTED_MASK << IW_I_A_LSB) | |
37 | #define GET_IW_I_A(W) (((W) >> IW_I_A_LSB) & IW_I_A_UNSHIFTED_MASK) | |
38 | #define SET_IW_I_A(V) (((V) & IW_I_A_UNSHIFTED_MASK) << IW_I_A_LSB) | |
39 | ||
40 | #define IW_I_B_LSB 22 | |
41 | #define IW_I_B_SIZE 5 | |
42 | #define IW_I_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I_B_SIZE)) | |
43 | #define IW_I_B_SHIFTED_MASK (IW_I_B_UNSHIFTED_MASK << IW_I_B_LSB) | |
44 | #define GET_IW_I_B(W) (((W) >> IW_I_B_LSB) & IW_I_B_UNSHIFTED_MASK) | |
45 | #define SET_IW_I_B(V) (((V) & IW_I_B_UNSHIFTED_MASK) << IW_I_B_LSB) | |
46 | ||
47 | #define IW_I_IMM16_LSB 6 | |
48 | #define IW_I_IMM16_SIZE 16 | |
49 | #define IW_I_IMM16_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I_IMM16_SIZE)) | |
50 | #define IW_I_IMM16_SHIFTED_MASK (IW_I_IMM16_UNSHIFTED_MASK << IW_I_IMM16_LSB) | |
51 | #define GET_IW_I_IMM16(W) (((W) >> IW_I_IMM16_LSB) & IW_I_IMM16_UNSHIFTED_MASK) | |
52 | #define SET_IW_I_IMM16(V) (((V) & IW_I_IMM16_UNSHIFTED_MASK) << IW_I_IMM16_LSB) | |
53 | ||
54 | #define IW_R_A_LSB 27 | |
55 | #define IW_R_A_SIZE 5 | |
56 | #define IW_R_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_A_SIZE)) | |
57 | #define IW_R_A_SHIFTED_MASK (IW_R_A_UNSHIFTED_MASK << IW_R_A_LSB) | |
58 | #define GET_IW_R_A(W) (((W) >> IW_R_A_LSB) & IW_R_A_UNSHIFTED_MASK) | |
59 | #define SET_IW_R_A(V) (((V) & IW_R_A_UNSHIFTED_MASK) << IW_R_A_LSB) | |
60 | ||
61 | #define IW_R_B_LSB 22 | |
62 | #define IW_R_B_SIZE 5 | |
63 | #define IW_R_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_B_SIZE)) | |
64 | #define IW_R_B_SHIFTED_MASK (IW_R_B_UNSHIFTED_MASK << IW_R_B_LSB) | |
65 | #define GET_IW_R_B(W) (((W) >> IW_R_B_LSB) & IW_R_B_UNSHIFTED_MASK) | |
66 | #define SET_IW_R_B(V) (((V) & IW_R_B_UNSHIFTED_MASK) << IW_R_B_LSB) | |
67 | ||
68 | #define IW_R_C_LSB 17 | |
69 | #define IW_R_C_SIZE 5 | |
70 | #define IW_R_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_C_SIZE)) | |
71 | #define IW_R_C_SHIFTED_MASK (IW_R_C_UNSHIFTED_MASK << IW_R_C_LSB) | |
72 | #define GET_IW_R_C(W) (((W) >> IW_R_C_LSB) & IW_R_C_UNSHIFTED_MASK) | |
73 | #define SET_IW_R_C(V) (((V) & IW_R_C_UNSHIFTED_MASK) << IW_R_C_LSB) | |
74 | ||
75 | #define IW_R_OPX_LSB 11 | |
76 | #define IW_R_OPX_SIZE 6 | |
77 | #define IW_R_OPX_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_OPX_SIZE)) | |
78 | #define IW_R_OPX_SHIFTED_MASK (IW_R_OPX_UNSHIFTED_MASK << IW_R_OPX_LSB) | |
79 | #define GET_IW_R_OPX(W) (((W) >> IW_R_OPX_LSB) & IW_R_OPX_UNSHIFTED_MASK) | |
80 | #define SET_IW_R_OPX(V) (((V) & IW_R_OPX_UNSHIFTED_MASK) << IW_R_OPX_LSB) | |
81 | ||
82 | #define IW_R_IMM5_LSB 6 | |
83 | #define IW_R_IMM5_SIZE 5 | |
84 | #define IW_R_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_IMM5_SIZE)) | |
85 | #define IW_R_IMM5_SHIFTED_MASK (IW_R_IMM5_UNSHIFTED_MASK << IW_R_IMM5_LSB) | |
86 | #define GET_IW_R_IMM5(W) (((W) >> IW_R_IMM5_LSB) & IW_R_IMM5_UNSHIFTED_MASK) | |
87 | #define SET_IW_R_IMM5(V) (((V) & IW_R_IMM5_UNSHIFTED_MASK) << IW_R_IMM5_LSB) | |
88 | ||
89 | #define IW_J_IMM26_LSB 6 | |
90 | #define IW_J_IMM26_SIZE 26 | |
91 | #define IW_J_IMM26_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_J_IMM26_SIZE)) | |
92 | #define IW_J_IMM26_SHIFTED_MASK (IW_J_IMM26_UNSHIFTED_MASK << IW_J_IMM26_LSB) | |
93 | #define GET_IW_J_IMM26(W) (((W) >> IW_J_IMM26_LSB) & IW_J_IMM26_UNSHIFTED_MASK) | |
94 | #define SET_IW_J_IMM26(V) (((V) & IW_J_IMM26_UNSHIFTED_MASK) << IW_J_IMM26_LSB) | |
95 | ||
96 | #define IW_CUSTOM_A_LSB 27 | |
97 | #define IW_CUSTOM_A_SIZE 5 | |
98 | #define IW_CUSTOM_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_A_SIZE)) | |
99 | #define IW_CUSTOM_A_SHIFTED_MASK (IW_CUSTOM_A_UNSHIFTED_MASK << IW_CUSTOM_A_LSB) | |
100 | #define GET_IW_CUSTOM_A(W) (((W) >> IW_CUSTOM_A_LSB) & IW_CUSTOM_A_UNSHIFTED_MASK) | |
101 | #define SET_IW_CUSTOM_A(V) (((V) & IW_CUSTOM_A_UNSHIFTED_MASK) << IW_CUSTOM_A_LSB) | |
102 | ||
103 | #define IW_CUSTOM_B_LSB 22 | |
104 | #define IW_CUSTOM_B_SIZE 5 | |
105 | #define IW_CUSTOM_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_B_SIZE)) | |
106 | #define IW_CUSTOM_B_SHIFTED_MASK (IW_CUSTOM_B_UNSHIFTED_MASK << IW_CUSTOM_B_LSB) | |
107 | #define GET_IW_CUSTOM_B(W) (((W) >> IW_CUSTOM_B_LSB) & IW_CUSTOM_B_UNSHIFTED_MASK) | |
108 | #define SET_IW_CUSTOM_B(V) (((V) & IW_CUSTOM_B_UNSHIFTED_MASK) << IW_CUSTOM_B_LSB) | |
109 | ||
110 | #define IW_CUSTOM_C_LSB 17 | |
111 | #define IW_CUSTOM_C_SIZE 5 | |
112 | #define IW_CUSTOM_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_C_SIZE)) | |
113 | #define IW_CUSTOM_C_SHIFTED_MASK (IW_CUSTOM_C_UNSHIFTED_MASK << IW_CUSTOM_C_LSB) | |
114 | #define GET_IW_CUSTOM_C(W) (((W) >> IW_CUSTOM_C_LSB) & IW_CUSTOM_C_UNSHIFTED_MASK) | |
115 | #define SET_IW_CUSTOM_C(V) (((V) & IW_CUSTOM_C_UNSHIFTED_MASK) << IW_CUSTOM_C_LSB) | |
116 | ||
117 | #define IW_CUSTOM_READA_LSB 16 | |
118 | #define IW_CUSTOM_READA_SIZE 1 | |
119 | #define IW_CUSTOM_READA_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_READA_SIZE)) | |
120 | #define IW_CUSTOM_READA_SHIFTED_MASK (IW_CUSTOM_READA_UNSHIFTED_MASK << IW_CUSTOM_READA_LSB) | |
121 | #define GET_IW_CUSTOM_READA(W) (((W) >> IW_CUSTOM_READA_LSB) & IW_CUSTOM_READA_UNSHIFTED_MASK) | |
122 | #define SET_IW_CUSTOM_READA(V) (((V) & IW_CUSTOM_READA_UNSHIFTED_MASK) << IW_CUSTOM_READA_LSB) | |
123 | ||
124 | #define IW_CUSTOM_READB_LSB 15 | |
125 | #define IW_CUSTOM_READB_SIZE 1 | |
126 | #define IW_CUSTOM_READB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_READB_SIZE)) | |
127 | #define IW_CUSTOM_READB_SHIFTED_MASK (IW_CUSTOM_READB_UNSHIFTED_MASK << IW_CUSTOM_READB_LSB) | |
128 | #define GET_IW_CUSTOM_READB(W) (((W) >> IW_CUSTOM_READB_LSB) & IW_CUSTOM_READB_UNSHIFTED_MASK) | |
129 | #define SET_IW_CUSTOM_READB(V) (((V) & IW_CUSTOM_READB_UNSHIFTED_MASK) << IW_CUSTOM_READB_LSB) | |
130 | ||
131 | #define IW_CUSTOM_READC_LSB 14 | |
132 | #define IW_CUSTOM_READC_SIZE 1 | |
133 | #define IW_CUSTOM_READC_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_READC_SIZE)) | |
134 | #define IW_CUSTOM_READC_SHIFTED_MASK (IW_CUSTOM_READC_UNSHIFTED_MASK << IW_CUSTOM_READC_LSB) | |
135 | #define GET_IW_CUSTOM_READC(W) (((W) >> IW_CUSTOM_READC_LSB) & IW_CUSTOM_READC_UNSHIFTED_MASK) | |
136 | #define SET_IW_CUSTOM_READC(V) (((V) & IW_CUSTOM_READC_UNSHIFTED_MASK) << IW_CUSTOM_READC_LSB) | |
137 | ||
138 | #define IW_CUSTOM_N_LSB 6 | |
139 | #define IW_CUSTOM_N_SIZE 8 | |
140 | #define IW_CUSTOM_N_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_CUSTOM_N_SIZE)) | |
141 | #define IW_CUSTOM_N_SHIFTED_MASK (IW_CUSTOM_N_UNSHIFTED_MASK << IW_CUSTOM_N_LSB) | |
142 | #define GET_IW_CUSTOM_N(W) (((W) >> IW_CUSTOM_N_LSB) & IW_CUSTOM_N_UNSHIFTED_MASK) | |
143 | #define SET_IW_CUSTOM_N(V) (((V) & IW_CUSTOM_N_UNSHIFTED_MASK) << IW_CUSTOM_N_LSB) | |
144 | ||
145 | /* R1 opcodes. */ | |
146 | #define R1_OP_CALL 0 | |
147 | #define R1_OP_JMPI 1 | |
148 | #define R1_OP_LDBU 3 | |
149 | #define R1_OP_ADDI 4 | |
150 | #define R1_OP_STB 5 | |
151 | #define R1_OP_BR 6 | |
152 | #define R1_OP_LDB 7 | |
153 | #define R1_OP_CMPGEI 8 | |
154 | #define R1_OP_LDHU 11 | |
155 | #define R1_OP_ANDI 12 | |
156 | #define R1_OP_STH 13 | |
157 | #define R1_OP_BGE 14 | |
158 | #define R1_OP_LDH 15 | |
159 | #define R1_OP_CMPLTI 16 | |
160 | #define R1_OP_INITDA 19 | |
161 | #define R1_OP_ORI 20 | |
162 | #define R1_OP_STW 21 | |
163 | #define R1_OP_BLT 22 | |
164 | #define R1_OP_LDW 23 | |
165 | #define R1_OP_CMPNEI 24 | |
166 | #define R1_OP_FLUSHDA 27 | |
167 | #define R1_OP_XORI 28 | |
168 | #define R1_OP_BNE 30 | |
169 | #define R1_OP_CMPEQI 32 | |
170 | #define R1_OP_LDBUIO 35 | |
171 | #define R1_OP_MULI 36 | |
172 | #define R1_OP_STBIO 37 | |
173 | #define R1_OP_BEQ 38 | |
174 | #define R1_OP_LDBIO 39 | |
175 | #define R1_OP_CMPGEUI 40 | |
176 | #define R1_OP_LDHUIO 43 | |
177 | #define R1_OP_ANDHI 44 | |
178 | #define R1_OP_STHIO 45 | |
179 | #define R1_OP_BGEU 46 | |
180 | #define R1_OP_LDHIO 47 | |
181 | #define R1_OP_CMPLTUI 48 | |
182 | #define R1_OP_CUSTOM 50 | |
183 | #define R1_OP_INITD 51 | |
184 | #define R1_OP_ORHI 52 | |
185 | #define R1_OP_STWIO 53 | |
186 | #define R1_OP_BLTU 54 | |
187 | #define R1_OP_LDWIO 55 | |
188 | #define R1_OP_RDPRS 56 | |
189 | #define R1_OP_OPX 58 | |
190 | #define R1_OP_FLUSHD 59 | |
191 | #define R1_OP_XORHI 60 | |
192 | ||
193 | #define R1_OPX_ERET 1 | |
194 | #define R1_OPX_ROLI 2 | |
195 | #define R1_OPX_ROL 3 | |
196 | #define R1_OPX_FLUSHP 4 | |
197 | #define R1_OPX_RET 5 | |
198 | #define R1_OPX_NOR 6 | |
199 | #define R1_OPX_MULXUU 7 | |
200 | #define R1_OPX_CMPGE 8 | |
201 | #define R1_OPX_BRET 9 | |
202 | #define R1_OPX_ROR 11 | |
203 | #define R1_OPX_FLUSHI 12 | |
204 | #define R1_OPX_JMP 13 | |
205 | #define R1_OPX_AND 14 | |
206 | #define R1_OPX_CMPLT 16 | |
207 | #define R1_OPX_SLLI 18 | |
208 | #define R1_OPX_SLL 19 | |
209 | #define R1_OPX_WRPRS 20 | |
210 | #define R1_OPX_OR 22 | |
211 | #define R1_OPX_MULXSU 23 | |
212 | #define R1_OPX_CMPNE 24 | |
213 | #define R1_OPX_SRLI 26 | |
214 | #define R1_OPX_SRL 27 | |
215 | #define R1_OPX_NEXTPC 28 | |
216 | #define R1_OPX_CALLR 29 | |
217 | #define R1_OPX_XOR 30 | |
218 | #define R1_OPX_MULXSS 31 | |
219 | #define R1_OPX_CMPEQ 32 | |
220 | #define R1_OPX_DIVU 36 | |
221 | #define R1_OPX_DIV 37 | |
222 | #define R1_OPX_RDCTL 38 | |
223 | #define R1_OPX_MUL 39 | |
224 | #define R1_OPX_CMPGEU 40 | |
225 | #define R1_OPX_INITI 41 | |
226 | #define R1_OPX_TRAP 45 | |
227 | #define R1_OPX_WRCTL 46 | |
228 | #define R1_OPX_CMPLTU 48 | |
229 | #define R1_OPX_ADD 49 | |
230 | #define R1_OPX_BREAK 52 | |
231 | #define R1_OPX_SYNC 54 | |
232 | #define R1_OPX_SUB 57 | |
233 | #define R1_OPX_SRAI 58 | |
234 | #define R1_OPX_SRA 59 | |
235 | ||
236 | /* Some convenience macros for R1 encodings, for use in instruction tables. | |
237 | MATCH_R1_OPX0(NAME) and MASK_R1_OPX0 are used for R-type instructions | |
238 | with 3 register operands and constant 0 in the immediate field. | |
239 | The general forms are MATCH_R1_OPX(NAME, A, B, C) where the arguments specify | |
240 | constant values and MASK_R1_OPX(A, B, C, N) where the arguments are booleans | |
241 | that are true if the field should be included in the mask. | |
242 | */ | |
243 | #define MATCH_R1_OP(NAME) \ | |
244 | (SET_IW_R1_OP (R1_OP_##NAME)) | |
245 | #define MASK_R1_OP \ | |
246 | IW_R1_OP_SHIFTED_MASK | |
247 | ||
248 | #define MATCH_R1_OPX0(NAME) \ | |
249 | (SET_IW_R1_OP (R1_OP_OPX) | SET_IW_R_OPX (R1_OPX_##NAME)) | |
250 | #define MASK_R1_OPX0 \ | |
251 | (IW_R1_OP_SHIFTED_MASK | IW_R_OPX_SHIFTED_MASK | IW_R_IMM5_SHIFTED_MASK) | |
252 | ||
253 | #define MATCH_R1_OPX(NAME, A, B, C) \ | |
254 | (MATCH_R1_OPX0 (NAME) | SET_IW_R_A (A) | SET_IW_R_B (B) | SET_IW_R_C (C)) | |
255 | #define MASK_R1_OPX(A, B, C, N) \ | |
256 | (IW_R1_OP_SHIFTED_MASK | IW_R_OPX_SHIFTED_MASK \ | |
257 | | (A ? IW_R_A_SHIFTED_MASK : 0) \ | |
258 | | (B ? IW_R_B_SHIFTED_MASK : 0) \ | |
259 | | (C ? IW_R_C_SHIFTED_MASK : 0) \ | |
260 | | (N ? IW_R_IMM5_SHIFTED_MASK : 0)) | |
261 | ||
262 | /* And here's the match/mask macros for the R1 instruction set. */ | |
263 | #define MATCH_R1_ADD MATCH_R1_OPX0 (ADD) | |
264 | #define MASK_R1_ADD MASK_R1_OPX0 | |
265 | #define MATCH_R1_ADDI MATCH_R1_OP (ADDI) | |
266 | #define MASK_R1_ADDI MASK_R1_OP | |
267 | #define MATCH_R1_AND MATCH_R1_OPX0 (AND) | |
268 | #define MASK_R1_AND MASK_R1_OPX0 | |
269 | #define MATCH_R1_ANDHI MATCH_R1_OP (ANDHI) | |
270 | #define MASK_R1_ANDHI MASK_R1_OP | |
271 | #define MATCH_R1_ANDI MATCH_R1_OP (ANDI) | |
272 | #define MASK_R1_ANDI MASK_R1_OP | |
273 | #define MATCH_R1_BEQ MATCH_R1_OP (BEQ) | |
274 | #define MASK_R1_BEQ MASK_R1_OP | |
275 | #define MATCH_R1_BGE MATCH_R1_OP (BGE) | |
276 | #define MASK_R1_BGE MASK_R1_OP | |
277 | #define MATCH_R1_BGEU MATCH_R1_OP (BGEU) | |
278 | #define MASK_R1_BGEU MASK_R1_OP | |
279 | #define MATCH_R1_BGT MATCH_R1_OP (BLT) | |
280 | #define MASK_R1_BGT MASK_R1_OP | |
281 | #define MATCH_R1_BGTU MATCH_R1_OP (BLTU) | |
282 | #define MASK_R1_BGTU MASK_R1_OP | |
283 | #define MATCH_R1_BLE MATCH_R1_OP (BGE) | |
284 | #define MASK_R1_BLE MASK_R1_OP | |
285 | #define MATCH_R1_BLEU MATCH_R1_OP (BGEU) | |
286 | #define MASK_R1_BLEU MASK_R1_OP | |
287 | #define MATCH_R1_BLT MATCH_R1_OP (BLT) | |
288 | #define MASK_R1_BLT MASK_R1_OP | |
289 | #define MATCH_R1_BLTU MATCH_R1_OP (BLTU) | |
290 | #define MASK_R1_BLTU MASK_R1_OP | |
291 | #define MATCH_R1_BNE MATCH_R1_OP (BNE) | |
292 | #define MASK_R1_BNE MASK_R1_OP | |
293 | #define MATCH_R1_BR MATCH_R1_OP (BR) | |
294 | #define MASK_R1_BR MASK_R1_OP | IW_I_A_SHIFTED_MASK | IW_I_B_SHIFTED_MASK | |
295 | #define MATCH_R1_BREAK MATCH_R1_OPX (BREAK, 0, 0, 0x1e) | |
296 | #define MASK_R1_BREAK MASK_R1_OPX (1, 1, 1, 0) | |
297 | #define MATCH_R1_BRET MATCH_R1_OPX (BRET, 0x1e, 0, 0) | |
298 | #define MASK_R1_BRET MASK_R1_OPX (1, 1, 1, 1) | |
299 | #define MATCH_R1_CALL MATCH_R1_OP (CALL) | |
300 | #define MASK_R1_CALL MASK_R1_OP | |
301 | #define MATCH_R1_CALLR MATCH_R1_OPX (CALLR, 0, 0, 0x1f) | |
302 | #define MASK_R1_CALLR MASK_R1_OPX (0, 1, 1, 1) | |
303 | #define MATCH_R1_CMPEQ MATCH_R1_OPX0 (CMPEQ) | |
304 | #define MASK_R1_CMPEQ MASK_R1_OPX0 | |
305 | #define MATCH_R1_CMPEQI MATCH_R1_OP (CMPEQI) | |
306 | #define MASK_R1_CMPEQI MASK_R1_OP | |
307 | #define MATCH_R1_CMPGE MATCH_R1_OPX0 (CMPGE) | |
308 | #define MASK_R1_CMPGE MASK_R1_OPX0 | |
309 | #define MATCH_R1_CMPGEI MATCH_R1_OP (CMPGEI) | |
310 | #define MASK_R1_CMPGEI MASK_R1_OP | |
311 | #define MATCH_R1_CMPGEU MATCH_R1_OPX0 (CMPGEU) | |
312 | #define MASK_R1_CMPGEU MASK_R1_OPX0 | |
313 | #define MATCH_R1_CMPGEUI MATCH_R1_OP (CMPGEUI) | |
314 | #define MASK_R1_CMPGEUI MASK_R1_OP | |
315 | #define MATCH_R1_CMPGT MATCH_R1_OPX0 (CMPLT) | |
316 | #define MASK_R1_CMPGT MASK_R1_OPX0 | |
317 | #define MATCH_R1_CMPGTI MATCH_R1_OP (CMPGEI) | |
318 | #define MASK_R1_CMPGTI MASK_R1_OP | |
319 | #define MATCH_R1_CMPGTU MATCH_R1_OPX0 (CMPLTU) | |
320 | #define MASK_R1_CMPGTU MASK_R1_OPX0 | |
321 | #define MATCH_R1_CMPGTUI MATCH_R1_OP (CMPGEUI) | |
322 | #define MASK_R1_CMPGTUI MASK_R1_OP | |
323 | #define MATCH_R1_CMPLE MATCH_R1_OPX0 (CMPGE) | |
324 | #define MASK_R1_CMPLE MASK_R1_OPX0 | |
325 | #define MATCH_R1_CMPLEI MATCH_R1_OP (CMPLTI) | |
326 | #define MASK_R1_CMPLEI MASK_R1_OP | |
327 | #define MATCH_R1_CMPLEU MATCH_R1_OPX0 (CMPGEU) | |
328 | #define MASK_R1_CMPLEU MASK_R1_OPX0 | |
329 | #define MATCH_R1_CMPLEUI MATCH_R1_OP (CMPLTUI) | |
330 | #define MASK_R1_CMPLEUI MASK_R1_OP | |
331 | #define MATCH_R1_CMPLT MATCH_R1_OPX0 (CMPLT) | |
332 | #define MASK_R1_CMPLT MASK_R1_OPX0 | |
333 | #define MATCH_R1_CMPLTI MATCH_R1_OP (CMPLTI) | |
334 | #define MASK_R1_CMPLTI MASK_R1_OP | |
335 | #define MATCH_R1_CMPLTU MATCH_R1_OPX0 (CMPLTU) | |
336 | #define MASK_R1_CMPLTU MASK_R1_OPX0 | |
337 | #define MATCH_R1_CMPLTUI MATCH_R1_OP (CMPLTUI) | |
338 | #define MASK_R1_CMPLTUI MASK_R1_OP | |
339 | #define MATCH_R1_CMPNE MATCH_R1_OPX0 (CMPNE) | |
340 | #define MASK_R1_CMPNE MASK_R1_OPX0 | |
341 | #define MATCH_R1_CMPNEI MATCH_R1_OP (CMPNEI) | |
342 | #define MASK_R1_CMPNEI MASK_R1_OP | |
343 | #define MATCH_R1_CUSTOM MATCH_R1_OP (CUSTOM) | |
344 | #define MASK_R1_CUSTOM MASK_R1_OP | |
345 | #define MATCH_R1_DIV MATCH_R1_OPX0 (DIV) | |
346 | #define MASK_R1_DIV MASK_R1_OPX0 | |
347 | #define MATCH_R1_DIVU MATCH_R1_OPX0 (DIVU) | |
348 | #define MASK_R1_DIVU MASK_R1_OPX0 | |
349 | #define MATCH_R1_ERET MATCH_R1_OPX (ERET, 0x1d, 0x1e, 0) | |
350 | #define MASK_R1_ERET MASK_R1_OPX (1, 1, 1, 1) | |
351 | #define MATCH_R1_FLUSHD MATCH_R1_OP (FLUSHD) | SET_IW_I_B (0) | |
352 | #define MASK_R1_FLUSHD MASK_R1_OP | IW_I_B_SHIFTED_MASK | |
353 | #define MATCH_R1_FLUSHDA MATCH_R1_OP (FLUSHDA) | SET_IW_I_B (0) | |
354 | #define MASK_R1_FLUSHDA MASK_R1_OP | IW_I_B_SHIFTED_MASK | |
355 | #define MATCH_R1_FLUSHI MATCH_R1_OPX (FLUSHI, 0, 0, 0) | |
356 | #define MASK_R1_FLUSHI MASK_R1_OPX (0, 1, 1, 1) | |
357 | #define MATCH_R1_FLUSHP MATCH_R1_OPX (FLUSHP, 0, 0, 0) | |
358 | #define MASK_R1_FLUSHP MASK_R1_OPX (1, 1, 1, 1) | |
359 | #define MATCH_R1_INITD MATCH_R1_OP (INITD) | SET_IW_I_B (0) | |
360 | #define MASK_R1_INITD MASK_R1_OP | IW_I_B_SHIFTED_MASK | |
361 | #define MATCH_R1_INITDA MATCH_R1_OP (INITDA) | SET_IW_I_B (0) | |
362 | #define MASK_R1_INITDA MASK_R1_OP | IW_I_B_SHIFTED_MASK | |
363 | #define MATCH_R1_INITI MATCH_R1_OPX (INITI, 0, 0, 0) | |
364 | #define MASK_R1_INITI MASK_R1_OPX (0, 1, 1, 1) | |
365 | #define MATCH_R1_JMP MATCH_R1_OPX (JMP, 0, 0, 0) | |
366 | #define MASK_R1_JMP MASK_R1_OPX (0, 1, 1, 1) | |
367 | #define MATCH_R1_JMPI MATCH_R1_OP (JMPI) | |
368 | #define MASK_R1_JMPI MASK_R1_OP | |
369 | #define MATCH_R1_LDB MATCH_R1_OP (LDB) | |
370 | #define MASK_R1_LDB MASK_R1_OP | |
371 | #define MATCH_R1_LDBIO MATCH_R1_OP (LDBIO) | |
372 | #define MASK_R1_LDBIO MASK_R1_OP | |
373 | #define MATCH_R1_LDBU MATCH_R1_OP (LDBU) | |
374 | #define MASK_R1_LDBU MASK_R1_OP | |
375 | #define MATCH_R1_LDBUIO MATCH_R1_OP (LDBUIO) | |
376 | #define MASK_R1_LDBUIO MASK_R1_OP | |
377 | #define MATCH_R1_LDH MATCH_R1_OP (LDH) | |
378 | #define MASK_R1_LDH MASK_R1_OP | |
379 | #define MATCH_R1_LDHIO MATCH_R1_OP (LDHIO) | |
380 | #define MASK_R1_LDHIO MASK_R1_OP | |
381 | #define MATCH_R1_LDHU MATCH_R1_OP (LDHU) | |
382 | #define MASK_R1_LDHU MASK_R1_OP | |
383 | #define MATCH_R1_LDHUIO MATCH_R1_OP (LDHUIO) | |
384 | #define MASK_R1_LDHUIO MASK_R1_OP | |
385 | #define MATCH_R1_LDW MATCH_R1_OP (LDW) | |
386 | #define MASK_R1_LDW MASK_R1_OP | |
387 | #define MATCH_R1_LDWIO MATCH_R1_OP (LDWIO) | |
388 | #define MASK_R1_LDWIO MASK_R1_OP | |
389 | #define MATCH_R1_MOV MATCH_R1_OPX (ADD, 0, 0, 0) | |
390 | #define MASK_R1_MOV MASK_R1_OPX (0, 1, 0, 1) | |
391 | #define MATCH_R1_MOVHI MATCH_R1_OP (ORHI) | SET_IW_I_A (0) | |
392 | #define MASK_R1_MOVHI MASK_R1_OP | IW_I_A_SHIFTED_MASK | |
393 | #define MATCH_R1_MOVI MATCH_R1_OP (ADDI) | SET_IW_I_A (0) | |
394 | #define MASK_R1_MOVI MASK_R1_OP | IW_I_A_SHIFTED_MASK | |
395 | #define MATCH_R1_MOVUI MATCH_R1_OP (ORI) | SET_IW_I_A (0) | |
396 | #define MASK_R1_MOVUI MASK_R1_OP | IW_I_A_SHIFTED_MASK | |
397 | #define MATCH_R1_MUL MATCH_R1_OPX0 (MUL) | |
398 | #define MASK_R1_MUL MASK_R1_OPX0 | |
399 | #define MATCH_R1_MULI MATCH_R1_OP (MULI) | |
400 | #define MASK_R1_MULI MASK_R1_OP | |
401 | #define MATCH_R1_MULXSS MATCH_R1_OPX0 (MULXSS) | |
402 | #define MASK_R1_MULXSS MASK_R1_OPX0 | |
403 | #define MATCH_R1_MULXSU MATCH_R1_OPX0 (MULXSU) | |
404 | #define MASK_R1_MULXSU MASK_R1_OPX0 | |
405 | #define MATCH_R1_MULXUU MATCH_R1_OPX0 (MULXUU) | |
406 | #define MASK_R1_MULXUU MASK_R1_OPX0 | |
407 | #define MATCH_R1_NEXTPC MATCH_R1_OPX (NEXTPC, 0, 0, 0) | |
408 | #define MASK_R1_NEXTPC MASK_R1_OPX (1, 1, 0, 1) | |
409 | #define MATCH_R1_NOP MATCH_R1_OPX (ADD, 0, 0, 0) | |
410 | #define MASK_R1_NOP MASK_R1_OPX (1, 1, 1, 1) | |
411 | #define MATCH_R1_NOR MATCH_R1_OPX0 (NOR) | |
412 | #define MASK_R1_NOR MASK_R1_OPX0 | |
413 | #define MATCH_R1_OR MATCH_R1_OPX0 (OR) | |
414 | #define MASK_R1_OR MASK_R1_OPX0 | |
415 | #define MATCH_R1_ORHI MATCH_R1_OP (ORHI) | |
416 | #define MASK_R1_ORHI MASK_R1_OP | |
417 | #define MATCH_R1_ORI MATCH_R1_OP (ORI) | |
418 | #define MASK_R1_ORI MASK_R1_OP | |
419 | #define MATCH_R1_RDCTL MATCH_R1_OPX (RDCTL, 0, 0, 0) | |
420 | #define MASK_R1_RDCTL MASK_R1_OPX (1, 1, 0, 0) | |
421 | #define MATCH_R1_RDPRS MATCH_R1_OP (RDPRS) | |
422 | #define MASK_R1_RDPRS MASK_R1_OP | |
423 | #define MATCH_R1_RET MATCH_R1_OPX (RET, 0x1f, 0, 0) | |
424 | #define MASK_R1_RET MASK_R1_OPX (1, 1, 1, 1) | |
425 | #define MATCH_R1_ROL MATCH_R1_OPX0 (ROL) | |
426 | #define MASK_R1_ROL MASK_R1_OPX0 | |
427 | #define MATCH_R1_ROLI MATCH_R1_OPX (ROLI, 0, 0, 0) | |
428 | #define MASK_R1_ROLI MASK_R1_OPX (0, 1, 0, 0) | |
429 | #define MATCH_R1_ROR MATCH_R1_OPX0 (ROR) | |
430 | #define MASK_R1_ROR MASK_R1_OPX0 | |
431 | #define MATCH_R1_SLL MATCH_R1_OPX0 (SLL) | |
432 | #define MASK_R1_SLL MASK_R1_OPX0 | |
433 | #define MATCH_R1_SLLI MATCH_R1_OPX (SLLI, 0, 0, 0) | |
434 | #define MASK_R1_SLLI MASK_R1_OPX (0, 1, 0, 0) | |
435 | #define MATCH_R1_SRA MATCH_R1_OPX0 (SRA) | |
436 | #define MASK_R1_SRA MASK_R1_OPX0 | |
437 | #define MATCH_R1_SRAI MATCH_R1_OPX (SRAI, 0, 0, 0) | |
438 | #define MASK_R1_SRAI MASK_R1_OPX (0, 1, 0, 0) | |
439 | #define MATCH_R1_SRL MATCH_R1_OPX0 (SRL) | |
440 | #define MASK_R1_SRL MASK_R1_OPX0 | |
441 | #define MATCH_R1_SRLI MATCH_R1_OPX (SRLI, 0, 0, 0) | |
442 | #define MASK_R1_SRLI MASK_R1_OPX (0, 1, 0, 0) | |
443 | #define MATCH_R1_STB MATCH_R1_OP (STB) | |
444 | #define MASK_R1_STB MASK_R1_OP | |
445 | #define MATCH_R1_STBIO MATCH_R1_OP (STBIO) | |
446 | #define MASK_R1_STBIO MASK_R1_OP | |
447 | #define MATCH_R1_STH MATCH_R1_OP (STH) | |
448 | #define MASK_R1_STH MASK_R1_OP | |
449 | #define MATCH_R1_STHIO MATCH_R1_OP (STHIO) | |
450 | #define MASK_R1_STHIO MASK_R1_OP | |
451 | #define MATCH_R1_STW MATCH_R1_OP (STW) | |
452 | #define MASK_R1_STW MASK_R1_OP | |
453 | #define MATCH_R1_STWIO MATCH_R1_OP (STWIO) | |
454 | #define MASK_R1_STWIO MASK_R1_OP | |
455 | #define MATCH_R1_SUB MATCH_R1_OPX0 (SUB) | |
456 | #define MASK_R1_SUB MASK_R1_OPX0 | |
457 | #define MATCH_R1_SUBI MATCH_R1_OP (ADDI) | |
458 | #define MASK_R1_SUBI MASK_R1_OP | |
459 | #define MATCH_R1_SYNC MATCH_R1_OPX (SYNC, 0, 0, 0) | |
460 | #define MASK_R1_SYNC MASK_R1_OPX (1, 1, 1, 1) | |
461 | #define MATCH_R1_TRAP MATCH_R1_OPX (TRAP, 0, 0, 0x1d) | |
462 | #define MASK_R1_TRAP MASK_R1_OPX (1, 1, 1, 0) | |
463 | #define MATCH_R1_WRCTL MATCH_R1_OPX (WRCTL, 0, 0, 0) | |
464 | #define MASK_R1_WRCTL MASK_R1_OPX (0, 1, 1, 0) | |
465 | #define MATCH_R1_WRPRS MATCH_R1_OPX (WRPRS, 0, 0, 0) | |
466 | #define MASK_R1_WRPRS MASK_R1_OPX (0, 1, 0, 1) | |
467 | #define MATCH_R1_XOR MATCH_R1_OPX0 (XOR) | |
468 | #define MASK_R1_XOR MASK_R1_OPX0 | |
469 | #define MATCH_R1_XORHI MATCH_R1_OP (XORHI) | |
470 | #define MASK_R1_XORHI MASK_R1_OP | |
471 | #define MATCH_R1_XORI MATCH_R1_OP (XORI) | |
472 | #define MASK_R1_XORI MASK_R1_OP | |
473 | ||
474 | #endif /* _NIOS2R1_H */ |