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252b5132 | 1 | /* ppc.h -- Header file for PowerPC opcode table |
4b95cf5c | 2 | Copyright (C) 1994-2014 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support |
4 | ||
e4e42b45 NC |
5 | This file is part of GDB, GAS, and the GNU binutils. |
6 | ||
7 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
8 | them and/or modify them under the terms of the GNU General Public | |
9 | License as published by the Free Software Foundation; either version 3, | |
10 | or (at your option) any later version. | |
11 | ||
12 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
15 | the GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this file; see the file COPYING3. If not, write to the Free | |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
20 | MA 02110-1301, USA. */ | |
252b5132 RH |
21 | |
22 | #ifndef PPC_H | |
23 | #define PPC_H | |
24 | ||
b961e85b AM |
25 | #include "bfd_stdint.h" |
26 | ||
27 | typedef uint64_t ppc_cpu_t; | |
fa452fa6 | 28 | |
252b5132 RH |
29 | /* The opcode table is an array of struct powerpc_opcode. */ |
30 | ||
31 | struct powerpc_opcode | |
32 | { | |
33 | /* The opcode name. */ | |
34 | const char *name; | |
35 | ||
36 | /* The opcode itself. Those bits which will be filled in with | |
37 | operands are zeroes. */ | |
38 | unsigned long opcode; | |
39 | ||
40 | /* The opcode mask. This is used by the disassembler. This is a | |
41 | mask containing ones indicating those bits which must match the | |
42 | opcode field, and zeroes indicating those bits which need not | |
43 | match (and are presumably filled in by operands). */ | |
44 | unsigned long mask; | |
45 | ||
46 | /* One bit flags for the opcode. These are used to indicate which | |
47 | specific processors support the instructions. The defined values | |
48 | are listed below. */ | |
fa452fa6 | 49 | ppc_cpu_t flags; |
252b5132 | 50 | |
1cb0a767 PB |
51 | /* One bit flags for the opcode. These are used to indicate which |
52 | specific processors no longer support the instructions. The defined | |
53 | values are listed below. */ | |
54 | ppc_cpu_t deprecated; | |
55 | ||
252b5132 RH |
56 | /* An array of operand codes. Each code is an index into the |
57 | operand table. They appear in the order which the operands must | |
58 | appear in assembly code, and are terminated by a zero. */ | |
59 | unsigned char operands[8]; | |
60 | }; | |
61 | ||
62 | /* The table itself is sorted by major opcode number, and is otherwise | |
63 | in the order in which the disassembler should consider | |
64 | instructions. */ | |
65 | extern const struct powerpc_opcode powerpc_opcodes[]; | |
66 | extern const int powerpc_num_opcodes; | |
b9c361e0 JL |
67 | extern const struct powerpc_opcode vle_opcodes[]; |
68 | extern const int vle_num_opcodes; | |
252b5132 RH |
69 | |
70 | /* Values defined for the flags field of a struct powerpc_opcode. */ | |
71 | ||
72 | /* Opcode is defined for the PowerPC architecture. */ | |
68d23d21 | 73 | #define PPC_OPCODE_PPC 1 |
252b5132 RH |
74 | |
75 | /* Opcode is defined for the POWER (RS/6000) architecture. */ | |
68d23d21 | 76 | #define PPC_OPCODE_POWER 2 |
252b5132 RH |
77 | |
78 | /* Opcode is defined for the POWER2 (Rios 2) architecture. */ | |
68d23d21 | 79 | #define PPC_OPCODE_POWER2 4 |
252b5132 | 80 | |
252b5132 RH |
81 | /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 |
82 | is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, | |
83 | but it also supports many additional POWER instructions. */ | |
bdc70b4a | 84 | #define PPC_OPCODE_601 8 |
252b5132 RH |
85 | |
86 | /* Opcode is supported in both the Power and PowerPC architectures | |
f2bae120 AM |
87 | (ie, compiler's -mcpu=common or assembler's -mcom). More than just |
88 | the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER | |
89 | and PPC_OPCODE_POWER2 because many instructions changed mnemonics | |
90 | between POWER and POWERPC. */ | |
bdc70b4a | 91 | #define PPC_OPCODE_COMMON 0x10 |
252b5132 RH |
92 | |
93 | /* Opcode is supported for any Power or PowerPC platform (this is | |
94 | for the assembler's -many option, and it eliminates duplicates). */ | |
bdc70b4a AM |
95 | #define PPC_OPCODE_ANY 0x20 |
96 | ||
97 | /* Opcode is only defined on 64 bit architectures. */ | |
98 | #define PPC_OPCODE_64 0x40 | |
252b5132 | 99 | |
45c18104 | 100 | /* Opcode is supported as part of the 64-bit bridge. */ |
bdc70b4a | 101 | #define PPC_OPCODE_64_BRIDGE 0x80 |
45c18104 | 102 | |
966f959b | 103 | /* Opcode is supported by Altivec Vector Unit */ |
bdc70b4a | 104 | #define PPC_OPCODE_ALTIVEC 0x100 |
418c1742 MG |
105 | |
106 | /* Opcode is supported by PowerPC 403 processor. */ | |
bdc70b4a | 107 | #define PPC_OPCODE_403 0x200 |
418c1742 | 108 | |
a09cf9bd | 109 | /* Opcode is supported by PowerPC BookE processor. */ |
bdc70b4a | 110 | #define PPC_OPCODE_BOOKE 0x400 |
68d23d21 AM |
111 | |
112 | /* Opcode is supported by PowerPC 440 processor. */ | |
bdc70b4a | 113 | #define PPC_OPCODE_440 0x800 |
966f959b | 114 | |
fc1e7121 | 115 | /* Opcode is only supported by Power4 architecture. */ |
bdc70b4a | 116 | #define PPC_OPCODE_POWER4 0x1000 |
fc1e7121 | 117 | |
066be9f7 | 118 | /* Opcode is only supported by Power7 architecture. */ |
bdc70b4a | 119 | #define PPC_OPCODE_POWER7 0x2000 |
0449635d EZ |
120 | |
121 | /* Opcode is only supported by e500x2 Core. */ | |
bdc70b4a | 122 | #define PPC_OPCODE_SPE 0x4000 |
0449635d EZ |
123 | |
124 | /* Opcode is supported by e500x2 Integer select APU. */ | |
bdc70b4a | 125 | #define PPC_OPCODE_ISEL 0x8000 |
0449635d EZ |
126 | |
127 | /* Opcode is an e500 SPE floating point instruction. */ | |
bdc70b4a | 128 | #define PPC_OPCODE_EFS 0x10000 |
0449635d EZ |
129 | |
130 | /* Opcode is supported by branch locking APU. */ | |
bdc70b4a | 131 | #define PPC_OPCODE_BRLOCK 0x20000 |
0449635d EZ |
132 | |
133 | /* Opcode is supported by performance monitor APU. */ | |
bdc70b4a | 134 | #define PPC_OPCODE_PMR 0x40000 |
0449635d EZ |
135 | |
136 | /* Opcode is supported by cache locking APU. */ | |
bdc70b4a | 137 | #define PPC_OPCODE_CACHELCK 0x80000 |
0449635d EZ |
138 | |
139 | /* Opcode is supported by machine check APU. */ | |
bdc70b4a | 140 | #define PPC_OPCODE_RFMCI 0x100000 |
0449635d | 141 | |
f4411256 | 142 | /* Opcode is only supported by Power5 architecture. */ |
bdc70b4a | 143 | #define PPC_OPCODE_POWER5 0x200000 |
f4411256 | 144 | |
36ae0db3 | 145 | /* Opcode is supported by PowerPC e300 family. */ |
bdc70b4a | 146 | #define PPC_OPCODE_E300 0x400000 |
9622b051 AM |
147 | |
148 | /* Opcode is only supported by Power6 architecture. */ | |
bdc70b4a | 149 | #define PPC_OPCODE_POWER6 0x800000 |
9622b051 | 150 | |
ede602d7 | 151 | /* Opcode is only supported by PowerPC Cell family. */ |
bdc70b4a | 152 | #define PPC_OPCODE_CELL 0x1000000 |
36ae0db3 | 153 | |
c3d65c1c | 154 | /* Opcode is supported by CPUs with paired singles support. */ |
bdc70b4a | 155 | #define PPC_OPCODE_PPCPS 0x2000000 |
c3d65c1c | 156 | |
19a6653c | 157 | /* Opcode is supported by Power E500MC */ |
bdc70b4a | 158 | #define PPC_OPCODE_E500MC 0x4000000 |
19a6653c | 159 | |
081ba1b3 | 160 | /* Opcode is supported by PowerPC 405 processor. */ |
bdc70b4a | 161 | #define PPC_OPCODE_405 0x8000000 |
081ba1b3 | 162 | |
9b4e5766 | 163 | /* Opcode is supported by Vector-Scalar (VSX) Unit */ |
bdc70b4a | 164 | #define PPC_OPCODE_VSX 0x10000000 |
9b4e5766 | 165 | |
e0d602ec | 166 | /* Opcode is supported by A2. */ |
bdc70b4a | 167 | #define PPC_OPCODE_A2 0x20000000 |
e0d602ec | 168 | |
9fe54b1c | 169 | /* Opcode is supported by PowerPC 476 processor. */ |
bdc70b4a | 170 | #define PPC_OPCODE_476 0x40000000 |
9fe54b1c | 171 | |
ce3d2015 | 172 | /* Opcode is supported by AppliedMicro Titan core */ |
bdc70b4a | 173 | #define PPC_OPCODE_TITAN 0x80000000 |
ce3d2015 | 174 | |
e01d869a | 175 | /* Opcode which is supported by the e500 family */ |
bdc70b4a | 176 | #define PPC_OPCODE_E500 0x100000000ull |
e01d869a | 177 | |
aea77599 AM |
178 | /* Opcode is supported by Extended Altivec Vector Unit */ |
179 | #define PPC_OPCODE_ALTIVEC2 0x200000000ull | |
180 | ||
181 | /* Opcode is supported by Power E6500 */ | |
182 | #define PPC_OPCODE_E6500 0x400000000ull | |
183 | ||
184 | /* Opcode is supported by Thread management APU */ | |
185 | #define PPC_OPCODE_TMR 0x800000000ull | |
186 | ||
b9c361e0 JL |
187 | /* Opcode which is supported by the VLE extension. */ |
188 | #define PPC_OPCODE_VLE 0x1000000000ull | |
189 | ||
5817ffd1 PB |
190 | /* Opcode is only supported by Power8 architecture. */ |
191 | #define PPC_OPCODE_POWER8 0x2000000000ull | |
192 | ||
193 | /* Opcode which is supported by the Hardware Transactional Memory extension. */ | |
194 | /* Currently, this is the same as the POWER8 mask. If another cpu comes out | |
195 | that isn't a superset of POWER8, we can define this to its own mask. */ | |
196 | #define PPC_OPCODE_HTM PPC_OPCODE_POWER8 | |
197 | ||
252b5132 RH |
198 | /* A macro to extract the major opcode from an instruction. */ |
199 | #define PPC_OP(i) (((i) >> 26) & 0x3f) | |
b9c361e0 JL |
200 | |
201 | /* A macro to determine if the instruction is a 2-byte VLE insn. */ | |
202 | #define PPC_OP_SE_VLE(m) ((m) <= 0xffff) | |
203 | ||
204 | /* A macro to extract the major opcode from a VLE instruction. */ | |
205 | #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f) | |
206 | ||
207 | /* A macro to convert a VLE opcode to a VLE opcode segment. */ | |
208 | #define VLE_OP_TO_SEG(i) ((i) >> 1) | |
252b5132 RH |
209 | \f |
210 | /* The operands table is an array of struct powerpc_operand. */ | |
211 | ||
212 | struct powerpc_operand | |
213 | { | |
b84bf58a AM |
214 | /* A bitmask of bits in the operand. */ |
215 | unsigned int bitm; | |
252b5132 | 216 | |
b9c361e0 JL |
217 | /* The shift operation to be applied to the operand. No shift |
218 | is made if this is zero. For positive values, the operand | |
219 | is shifted left by SHIFT. For negative values, the operand | |
220 | is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate | |
221 | that BITM and SHIFT cannot be used to determine where the | |
222 | operand goes in the insn. */ | |
252b5132 RH |
223 | int shift; |
224 | ||
225 | /* Insertion function. This is used by the assembler. To insert an | |
226 | operand value into an instruction, check this field. | |
227 | ||
228 | If it is NULL, execute | |
b9c361e0 JL |
229 | if (o->shift >= 0) |
230 | i |= (op & o->bitm) << o->shift; | |
231 | else | |
232 | i |= (op & o->bitm) >> -o->shift; | |
252b5132 | 233 | (i is the instruction which we are filling in, o is a pointer to |
b84bf58a | 234 | this structure, and op is the operand value). |
252b5132 RH |
235 | |
236 | If this field is not NULL, then simply call it with the | |
237 | instruction and the operand value. It will return the new value | |
238 | of the instruction. If the ERRMSG argument is not NULL, then if | |
239 | the operand value is illegal, *ERRMSG will be set to a warning | |
240 | string (the operand will be inserted in any case). If the | |
241 | operand value is legal, *ERRMSG will be unchanged (most operands | |
242 | can accept any value). */ | |
8cf3f354 | 243 | unsigned long (*insert) |
fa452fa6 | 244 | (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg); |
252b5132 RH |
245 | |
246 | /* Extraction function. This is used by the disassembler. To | |
247 | extract this operand type from an instruction, check this field. | |
248 | ||
249 | If it is NULL, compute | |
b9c361e0 JL |
250 | if (o->shift >= 0) |
251 | op = (i >> o->shift) & o->bitm; | |
252 | else | |
253 | op = (i << -o->shift) & o->bitm; | |
b84bf58a AM |
254 | if ((o->flags & PPC_OPERAND_SIGNED) != 0) |
255 | sign_extend (op); | |
252b5132 | 256 | (i is the instruction, o is a pointer to this structure, and op |
b84bf58a | 257 | is the result). |
252b5132 RH |
258 | |
259 | If this field is not NULL, then simply call it with the | |
260 | instruction value. It will return the value of the operand. If | |
261 | the INVALID argument is not NULL, *INVALID will be set to | |
262 | non-zero if this operand type can not actually be extracted from | |
263 | this operand (i.e., the instruction does not match). If the | |
264 | operand is valid, *INVALID will not be changed. */ | |
fa452fa6 | 265 | long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid); |
252b5132 RH |
266 | |
267 | /* One bit syntax flags. */ | |
268 | unsigned long flags; | |
269 | }; | |
270 | ||
271 | /* Elements in the table are retrieved by indexing with values from | |
272 | the operands field of the powerpc_opcodes table. */ | |
273 | ||
274 | extern const struct powerpc_operand powerpc_operands[]; | |
b84bf58a | 275 | extern const unsigned int num_powerpc_operands; |
252b5132 | 276 | |
b9c361e0 JL |
277 | /* Use with the shift field of a struct powerpc_operand to indicate |
278 | that BITM and SHIFT cannot be used to determine where the operand | |
279 | goes in the insn. */ | |
280 | #define PPC_OPSHIFT_INV (-1 << 31) | |
281 | ||
252b5132 RH |
282 | /* Values defined for the flags field of a struct powerpc_operand. */ |
283 | ||
284 | /* This operand takes signed values. */ | |
b84bf58a | 285 | #define PPC_OPERAND_SIGNED (0x1) |
252b5132 RH |
286 | |
287 | /* This operand takes signed values, but also accepts a full positive | |
288 | range of values when running in 32 bit mode. That is, if bits is | |
289 | 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, | |
290 | this flag is ignored. */ | |
b84bf58a | 291 | #define PPC_OPERAND_SIGNOPT (0x2) |
252b5132 RH |
292 | |
293 | /* This operand does not actually exist in the assembler input. This | |
294 | is used to support extended mnemonics such as mr, for which two | |
295 | operands fields are identical. The assembler should call the | |
296 | insert function with any op value. The disassembler should call | |
297 | the extract function, ignore the return value, and check the value | |
298 | placed in the valid argument. */ | |
b84bf58a | 299 | #define PPC_OPERAND_FAKE (0x4) |
252b5132 RH |
300 | |
301 | /* The next operand should be wrapped in parentheses rather than | |
302 | separated from this one by a comma. This is used for the load and | |
303 | store instructions which want their operands to look like | |
304 | reg,displacement(reg) | |
305 | */ | |
b84bf58a | 306 | #define PPC_OPERAND_PARENS (0x8) |
252b5132 RH |
307 | |
308 | /* This operand may use the symbolic names for the CR fields, which | |
309 | are | |
310 | lt 0 gt 1 eq 2 so 3 un 3 | |
311 | cr0 0 cr1 1 cr2 2 cr3 3 | |
312 | cr4 4 cr5 5 cr6 6 cr7 7 | |
313 | These may be combined arithmetically, as in cr2*4+gt. These are | |
314 | only supported on the PowerPC, not the POWER. */ | |
b9c361e0 | 315 | #define PPC_OPERAND_CR_BIT (0x10) |
252b5132 RH |
316 | |
317 | /* This operand names a register. The disassembler uses this to print | |
318 | register names with a leading 'r'. */ | |
b84bf58a | 319 | #define PPC_OPERAND_GPR (0x20) |
252b5132 | 320 | |
fdd12ef3 | 321 | /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ |
b84bf58a | 322 | #define PPC_OPERAND_GPR_0 (0x40) |
fdd12ef3 | 323 | |
252b5132 RH |
324 | /* This operand names a floating point register. The disassembler |
325 | prints these with a leading 'f'. */ | |
b84bf58a | 326 | #define PPC_OPERAND_FPR (0x80) |
252b5132 RH |
327 | |
328 | /* This operand is a relative branch displacement. The disassembler | |
329 | prints these symbolically if possible. */ | |
b84bf58a | 330 | #define PPC_OPERAND_RELATIVE (0x100) |
252b5132 RH |
331 | |
332 | /* This operand is an absolute branch address. The disassembler | |
333 | prints these symbolically if possible. */ | |
b84bf58a | 334 | #define PPC_OPERAND_ABSOLUTE (0x200) |
252b5132 RH |
335 | |
336 | /* This operand is optional, and is zero if omitted. This is used for | |
2a309db0 | 337 | example, in the optional BF field in the comparison instructions. The |
252b5132 RH |
338 | assembler must count the number of operands remaining on the line, |
339 | and the number of operands remaining for the opcode, and decide | |
340 | whether this operand is present or not. The disassembler should | |
341 | print this operand out only if it is not zero. */ | |
b84bf58a | 342 | #define PPC_OPERAND_OPTIONAL (0x400) |
252b5132 RH |
343 | |
344 | /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand | |
345 | is omitted, then for the next operand use this operand value plus | |
346 | 1, ignoring the next operand field for the opcode. This wretched | |
347 | hack is needed because the Power rotate instructions can take | |
348 | either 4 or 5 operands. The disassembler should print this operand | |
349 | out regardless of the PPC_OPERAND_OPTIONAL field. */ | |
b84bf58a | 350 | #define PPC_OPERAND_NEXT (0x800) |
252b5132 RH |
351 | |
352 | /* This operand should be regarded as a negative number for the | |
353 | purposes of overflow checking (i.e., the normal most negative | |
354 | number is disallowed and one more than the normal most positive | |
355 | number is allowed). This flag will only be set for a signed | |
356 | operand. */ | |
b84bf58a | 357 | #define PPC_OPERAND_NEGATIVE (0x1000) |
966f959b C |
358 | |
359 | /* This operand names a vector unit register. The disassembler | |
360 | prints these with a leading 'v'. */ | |
b84bf58a | 361 | #define PPC_OPERAND_VR (0x2000) |
966f959b | 362 | |
a6959011 | 363 | /* This operand is for the DS field in a DS form instruction. */ |
b84bf58a | 364 | #define PPC_OPERAND_DS (0x4000) |
adadcc0c AM |
365 | |
366 | /* This operand is for the DQ field in a DQ form instruction. */ | |
b84bf58a AM |
367 | #define PPC_OPERAND_DQ (0x8000) |
368 | ||
3896c469 | 369 | /* Valid range of operand is 0..n rather than 0..n-1. */ |
b84bf58a | 370 | #define PPC_OPERAND_PLUS1 (0x10000) |
081ba1b3 AM |
371 | |
372 | /* Xilinx APU and FSL related operands */ | |
373 | #define PPC_OPERAND_FSL (0x20000) | |
374 | #define PPC_OPERAND_FCR (0x40000) | |
375 | #define PPC_OPERAND_UDI (0x80000) | |
9b4e5766 PB |
376 | |
377 | /* This operand names a vector-scalar unit register. The disassembler | |
378 | prints these with a leading 'vs'. */ | |
379 | #define PPC_OPERAND_VSR (0x100000) | |
b9c361e0 JL |
380 | |
381 | /* This is a CR FIELD that does not use symbolic names. */ | |
382 | #define PPC_OPERAND_CR_REG (0x200000) | |
252b5132 RH |
383 | \f |
384 | /* The POWER and PowerPC assemblers use a few macros. We keep them | |
385 | with the operands table for simplicity. The macro table is an | |
386 | array of struct powerpc_macro. */ | |
387 | ||
388 | struct powerpc_macro | |
389 | { | |
390 | /* The macro name. */ | |
391 | const char *name; | |
392 | ||
393 | /* The number of operands the macro takes. */ | |
394 | unsigned int operands; | |
395 | ||
396 | /* One bit flags for the opcode. These are used to indicate which | |
397 | specific processors support the instructions. The values are the | |
398 | same as those for the struct powerpc_opcode flags field. */ | |
fa452fa6 | 399 | ppc_cpu_t flags; |
252b5132 RH |
400 | |
401 | /* A format string to turn the macro into a normal instruction. | |
402 | Each %N in the string is replaced with operand number N (zero | |
403 | based). */ | |
404 | const char *format; | |
405 | }; | |
406 | ||
407 | extern const struct powerpc_macro powerpc_macros[]; | |
408 | extern const int powerpc_num_macros; | |
409 | ||
776fc418 | 410 | extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); |
69fe9ce5 | 411 | |
252b5132 | 412 | #endif /* PPC_H */ |