Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* ppc.h -- Header file for PowerPC opcode table |
b3adc24a | 2 | Copyright (C) 1994-2020 Free Software Foundation, Inc. |
252b5132 RH |
3 | Written by Ian Lance Taylor, Cygnus Support |
4 | ||
e4e42b45 NC |
5 | This file is part of GDB, GAS, and the GNU binutils. |
6 | ||
7 | GDB, GAS, and the GNU binutils are free software; you can redistribute | |
8 | them and/or modify them under the terms of the GNU General Public | |
9 | License as published by the Free Software Foundation; either version 3, | |
10 | or (at your option) any later version. | |
11 | ||
12 | GDB, GAS, and the GNU binutils are distributed in the hope that they | |
13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied | |
14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See | |
15 | the GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with this file; see the file COPYING3. If not, write to the Free | |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, | |
20 | MA 02110-1301, USA. */ | |
252b5132 RH |
21 | |
22 | #ifndef PPC_H | |
23 | #define PPC_H | |
24 | ||
b961e85b AM |
25 | #include "bfd_stdint.h" |
26 | ||
1fe0971e TS |
27 | #ifdef __cplusplus |
28 | extern "C" { | |
29 | #endif | |
30 | ||
b961e85b | 31 | typedef uint64_t ppc_cpu_t; |
fa452fa6 | 32 | |
252b5132 RH |
33 | /* The opcode table is an array of struct powerpc_opcode. */ |
34 | ||
35 | struct powerpc_opcode | |
36 | { | |
37 | /* The opcode name. */ | |
38 | const char *name; | |
39 | ||
40 | /* The opcode itself. Those bits which will be filled in with | |
41 | operands are zeroes. */ | |
0f873fd5 | 42 | uint64_t opcode; |
252b5132 RH |
43 | |
44 | /* The opcode mask. This is used by the disassembler. This is a | |
45 | mask containing ones indicating those bits which must match the | |
46 | opcode field, and zeroes indicating those bits which need not | |
47 | match (and are presumably filled in by operands). */ | |
0f873fd5 | 48 | uint64_t mask; |
252b5132 RH |
49 | |
50 | /* One bit flags for the opcode. These are used to indicate which | |
51 | specific processors support the instructions. The defined values | |
52 | are listed below. */ | |
fa452fa6 | 53 | ppc_cpu_t flags; |
252b5132 | 54 | |
1cb0a767 PB |
55 | /* One bit flags for the opcode. These are used to indicate which |
56 | specific processors no longer support the instructions. The defined | |
57 | values are listed below. */ | |
58 | ppc_cpu_t deprecated; | |
59 | ||
252b5132 RH |
60 | /* An array of operand codes. Each code is an index into the |
61 | operand table. They appear in the order which the operands must | |
62 | appear in assembly code, and are terminated by a zero. */ | |
63 | unsigned char operands[8]; | |
64 | }; | |
65 | ||
66 | /* The table itself is sorted by major opcode number, and is otherwise | |
67 | in the order in which the disassembler should consider | |
68 | instructions. */ | |
69 | extern const struct powerpc_opcode powerpc_opcodes[]; | |
2ceb7719 | 70 | extern const unsigned int powerpc_num_opcodes; |
dd7efa79 PB |
71 | extern const struct powerpc_opcode prefix_opcodes[]; |
72 | extern const unsigned int prefix_num_opcodes; | |
b9c361e0 | 73 | extern const struct powerpc_opcode vle_opcodes[]; |
2ceb7719 | 74 | extern const unsigned int vle_num_opcodes; |
74081948 | 75 | extern const struct powerpc_opcode spe2_opcodes[]; |
2ceb7719 | 76 | extern const unsigned int spe2_num_opcodes; |
252b5132 RH |
77 | |
78 | /* Values defined for the flags field of a struct powerpc_opcode. */ | |
79 | ||
80 | /* Opcode is defined for the PowerPC architecture. */ | |
52be03fd | 81 | #define PPC_OPCODE_PPC 0x1ull |
252b5132 RH |
82 | |
83 | /* Opcode is defined for the POWER (RS/6000) architecture. */ | |
52be03fd | 84 | #define PPC_OPCODE_POWER 0x2ull |
252b5132 RH |
85 | |
86 | /* Opcode is defined for the POWER2 (Rios 2) architecture. */ | |
52be03fd | 87 | #define PPC_OPCODE_POWER2 0x4ull |
252b5132 | 88 | |
c03dc33b AM |
89 | /* Opcode is only defined on 64 bit architectures. */ |
90 | #define PPC_OPCODE_64 0x8ull | |
91 | ||
252b5132 RH |
92 | /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 |
93 | is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, | |
94 | but it also supports many additional POWER instructions. */ | |
c03dc33b | 95 | #define PPC_OPCODE_601 0x10ull |
252b5132 RH |
96 | |
97 | /* Opcode is supported in both the Power and PowerPC architectures | |
f2bae120 AM |
98 | (ie, compiler's -mcpu=common or assembler's -mcom). More than just |
99 | the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER | |
100 | and PPC_OPCODE_POWER2 because many instructions changed mnemonics | |
101 | between POWER and POWERPC. */ | |
c03dc33b | 102 | #define PPC_OPCODE_COMMON 0x20ull |
252b5132 RH |
103 | |
104 | /* Opcode is supported for any Power or PowerPC platform (this is | |
105 | for the assembler's -many option, and it eliminates duplicates). */ | |
c03dc33b | 106 | #define PPC_OPCODE_ANY 0x40ull |
252b5132 | 107 | |
45c18104 | 108 | /* Opcode is supported as part of the 64-bit bridge. */ |
52be03fd | 109 | #define PPC_OPCODE_64_BRIDGE 0x80ull |
45c18104 | 110 | |
966f959b | 111 | /* Opcode is supported by Altivec Vector Unit */ |
52be03fd | 112 | #define PPC_OPCODE_ALTIVEC 0x100ull |
418c1742 MG |
113 | |
114 | /* Opcode is supported by PowerPC 403 processor. */ | |
52be03fd | 115 | #define PPC_OPCODE_403 0x200ull |
418c1742 | 116 | |
a09cf9bd | 117 | /* Opcode is supported by PowerPC BookE processor. */ |
52be03fd | 118 | #define PPC_OPCODE_BOOKE 0x400ull |
68d23d21 | 119 | |
fc1e7121 | 120 | /* Opcode is only supported by Power4 architecture. */ |
c03dc33b | 121 | #define PPC_OPCODE_POWER4 0x800ull |
fc1e7121 | 122 | |
c03dc33b AM |
123 | /* Opcode is only supported by e500x2 Core. |
124 | This bit, PPC_OPCODE_EFS, PPC_OPCODE_VLE, and all those with APU in | |
125 | their comment mark opcodes so that when those instructions are used | |
126 | an APUinfo entry can be generated. */ | |
127 | #define PPC_OPCODE_SPE 0x1000ull | |
0449635d | 128 | |
c03dc33b AM |
129 | /* Opcode is supported by Integer select APU. */ |
130 | #define PPC_OPCODE_ISEL 0x2000ull | |
0449635d EZ |
131 | |
132 | /* Opcode is an e500 SPE floating point instruction. */ | |
c03dc33b | 133 | #define PPC_OPCODE_EFS 0x4000ull |
0449635d EZ |
134 | |
135 | /* Opcode is supported by branch locking APU. */ | |
c03dc33b | 136 | #define PPC_OPCODE_BRLOCK 0x8000ull |
0449635d EZ |
137 | |
138 | /* Opcode is supported by performance monitor APU. */ | |
c03dc33b | 139 | #define PPC_OPCODE_PMR 0x10000ull |
0449635d EZ |
140 | |
141 | /* Opcode is supported by cache locking APU. */ | |
c03dc33b | 142 | #define PPC_OPCODE_CACHELCK 0x20000ull |
0449635d EZ |
143 | |
144 | /* Opcode is supported by machine check APU. */ | |
c03dc33b AM |
145 | #define PPC_OPCODE_RFMCI 0x40000ull |
146 | ||
147 | /* Opcode is supported by PowerPC 440 processor. */ | |
148 | #define PPC_OPCODE_440 0x80000ull | |
0449635d | 149 | |
f4411256 | 150 | /* Opcode is only supported by Power5 architecture. */ |
c03dc33b | 151 | #define PPC_OPCODE_POWER5 0x100000ull |
f4411256 | 152 | |
36ae0db3 | 153 | /* Opcode is supported by PowerPC e300 family. */ |
c03dc33b | 154 | #define PPC_OPCODE_E300 0x200000ull |
9622b051 AM |
155 | |
156 | /* Opcode is only supported by Power6 architecture. */ | |
c03dc33b | 157 | #define PPC_OPCODE_POWER6 0x400000ull |
9622b051 | 158 | |
ede602d7 | 159 | /* Opcode is only supported by PowerPC Cell family. */ |
c03dc33b | 160 | #define PPC_OPCODE_CELL 0x800000ull |
36ae0db3 | 161 | |
c3d65c1c | 162 | /* Opcode is supported by CPUs with paired singles support. */ |
c03dc33b | 163 | #define PPC_OPCODE_PPCPS 0x1000000ull |
c3d65c1c | 164 | |
19a6653c | 165 | /* Opcode is supported by Power E500MC */ |
c03dc33b | 166 | #define PPC_OPCODE_E500MC 0x2000000ull |
19a6653c | 167 | |
081ba1b3 | 168 | /* Opcode is supported by PowerPC 405 processor. */ |
c03dc33b | 169 | #define PPC_OPCODE_405 0x4000000ull |
081ba1b3 | 170 | |
9b4e5766 | 171 | /* Opcode is supported by Vector-Scalar (VSX) Unit */ |
c03dc33b AM |
172 | #define PPC_OPCODE_VSX 0x8000000ull |
173 | ||
174 | /* Opcode is only supported by Power7 architecture. */ | |
175 | #define PPC_OPCODE_POWER7 0x10000000ull | |
9b4e5766 | 176 | |
e0d602ec | 177 | /* Opcode is supported by A2. */ |
c03dc33b | 178 | #define PPC_OPCODE_A2 0x20000000ull |
e0d602ec | 179 | |
9fe54b1c | 180 | /* Opcode is supported by PowerPC 476 processor. */ |
52be03fd | 181 | #define PPC_OPCODE_476 0x40000000ull |
9fe54b1c | 182 | |
ce3d2015 | 183 | /* Opcode is supported by AppliedMicro Titan core */ |
c03dc33b | 184 | #define PPC_OPCODE_TITAN 0x80000000ull |
ce3d2015 | 185 | |
e01d869a | 186 | /* Opcode which is supported by the e500 family */ |
c03dc33b | 187 | #define PPC_OPCODE_E500 0x100000000ull |
e01d869a | 188 | |
aea77599 | 189 | /* Opcode is supported by Power E6500 */ |
c03dc33b | 190 | #define PPC_OPCODE_E6500 0x200000000ull |
aea77599 AM |
191 | |
192 | /* Opcode is supported by Thread management APU */ | |
c03dc33b | 193 | #define PPC_OPCODE_TMR 0x400000000ull |
aea77599 | 194 | |
b9c361e0 | 195 | /* Opcode which is supported by the VLE extension. */ |
c03dc33b | 196 | #define PPC_OPCODE_VLE 0x800000000ull |
b9c361e0 | 197 | |
5817ffd1 | 198 | /* Opcode is only supported by Power8 architecture. */ |
c03dc33b | 199 | #define PPC_OPCODE_POWER8 0x1000000000ull |
5817ffd1 | 200 | |
fa758a70 | 201 | /* Opcode is supported by ppc750cl/Gekko/Broadway. */ |
c03dc33b | 202 | #define PPC_OPCODE_750 0x2000000000ull |
ef5a96d5 AM |
203 | |
204 | /* Opcode is supported by ppc7450. */ | |
c03dc33b | 205 | #define PPC_OPCODE_7450 0x4000000000ull |
ef5a96d5 AM |
206 | |
207 | /* Opcode is supported by ppc821/850/860. */ | |
c03dc33b | 208 | #define PPC_OPCODE_860 0x8000000000ull |
ef5a96d5 | 209 | |
a680de9a | 210 | /* Opcode is only supported by Power9 architecture. */ |
c03dc33b | 211 | #define PPC_OPCODE_POWER9 0x10000000000ull |
a680de9a | 212 | |
52be03fd | 213 | /* Opcode is supported by e200z4. */ |
c03dc33b | 214 | #define PPC_OPCODE_E200Z4 0x20000000000ull |
52be03fd AM |
215 | |
216 | /* Disassemble to instructions matching later in the opcode table | |
217 | with fewer "mask" bits set rather than the earlist match. Fewer | |
218 | "mask" bits set imply a more general form of the opcode, in fact | |
219 | the underlying machine instruction. */ | |
c03dc33b | 220 | #define PPC_OPCODE_RAW 0x40000000000ull |
dfdaec14 | 221 | |
e3c2f928 AF |
222 | /* Opcode is supported by PowerPC LSP */ |
223 | #define PPC_OPCODE_LSP 0x80000000000ull | |
224 | ||
74081948 AF |
225 | /* Opcode is only supported by Freescale SPE2 APU. */ |
226 | #define PPC_OPCODE_SPE2 0x100000000000ull | |
227 | ||
228 | /* Opcode is supported by EFS2. */ | |
229 | #define PPC_OPCODE_EFS2 0x200000000000ull | |
230 | ||
7c1f4227 AM |
231 | /* Opcode is only supported by power10 architecture. */ |
232 | #define PPC_OPCODE_POWER10 0x400000000000ull | |
dd7efa79 | 233 | |
252b5132 RH |
234 | /* A macro to extract the major opcode from an instruction. */ |
235 | #define PPC_OP(i) (((i) >> 26) & 0x3f) | |
b9c361e0 JL |
236 | |
237 | /* A macro to determine if the instruction is a 2-byte VLE insn. */ | |
238 | #define PPC_OP_SE_VLE(m) ((m) <= 0xffff) | |
239 | ||
240 | /* A macro to extract the major opcode from a VLE instruction. */ | |
241 | #define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f) | |
242 | ||
243 | /* A macro to convert a VLE opcode to a VLE opcode segment. */ | |
244 | #define VLE_OP_TO_SEG(i) ((i) >> 1) | |
74081948 AF |
245 | |
246 | /* A macro to extract the extended opcode from a SPE2 instruction. */ | |
247 | #define SPE2_XOP(i) ((i) & 0x7ff) | |
248 | ||
249 | /* A macro to convert a SPE2 extended opcode to a SPE2 xopcode segment. */ | |
250 | #define SPE2_XOP_TO_SEG(i) ((i) >> 7) | |
dd7efa79 PB |
251 | |
252 | /* A macro to extract the prefix word from an 8-byte PREFIX instruction. */ | |
253 | #define PPC_GET_PREFIX(i) (((i) >> 32) & ((1LL << 32) - 1)) | |
254 | ||
255 | /* A macro to extract the suffix word from an 8-byte PREFIX instruction. */ | |
256 | #define PPC_GET_SUFFIX(i) ((i) & ((1LL << 32) - 1)) | |
257 | ||
258 | /* A macro to determine whether insn I is an 8-byte prefix instruction. */ | |
259 | #define PPC_PREFIX_P(i) (PPC_OP (PPC_GET_PREFIX (i)) == 0x1) | |
260 | ||
261 | /* A macro used to hash 8-byte PREFIX instructions. */ | |
262 | #define PPC_PREFIX_SEG(i) (PPC_OP (i) >> 1) | |
263 | ||
252b5132 RH |
264 | \f |
265 | /* The operands table is an array of struct powerpc_operand. */ | |
266 | ||
267 | struct powerpc_operand | |
268 | { | |
b84bf58a | 269 | /* A bitmask of bits in the operand. */ |
0f873fd5 | 270 | uint64_t bitm; |
252b5132 | 271 | |
b9c361e0 JL |
272 | /* The shift operation to be applied to the operand. No shift |
273 | is made if this is zero. For positive values, the operand | |
274 | is shifted left by SHIFT. For negative values, the operand | |
275 | is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate | |
276 | that BITM and SHIFT cannot be used to determine where the | |
277 | operand goes in the insn. */ | |
252b5132 RH |
278 | int shift; |
279 | ||
280 | /* Insertion function. This is used by the assembler. To insert an | |
281 | operand value into an instruction, check this field. | |
282 | ||
283 | If it is NULL, execute | |
b9c361e0 JL |
284 | if (o->shift >= 0) |
285 | i |= (op & o->bitm) << o->shift; | |
286 | else | |
287 | i |= (op & o->bitm) >> -o->shift; | |
252b5132 | 288 | (i is the instruction which we are filling in, o is a pointer to |
b84bf58a | 289 | this structure, and op is the operand value). |
252b5132 RH |
290 | |
291 | If this field is not NULL, then simply call it with the | |
292 | instruction and the operand value. It will return the new value | |
9cf7e568 AM |
293 | of the instruction. If the operand value is illegal, *ERRMSG |
294 | will be set to a warning string (the operand will be inserted in | |
295 | any case). If the operand value is legal, *ERRMSG will be | |
296 | unchanged (most operands can accept any value). */ | |
0f873fd5 PB |
297 | uint64_t (*insert) |
298 | (uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg); | |
252b5132 RH |
299 | |
300 | /* Extraction function. This is used by the disassembler. To | |
301 | extract this operand type from an instruction, check this field. | |
302 | ||
303 | If it is NULL, compute | |
b9c361e0 JL |
304 | if (o->shift >= 0) |
305 | op = (i >> o->shift) & o->bitm; | |
306 | else | |
307 | op = (i << -o->shift) & o->bitm; | |
b84bf58a AM |
308 | if ((o->flags & PPC_OPERAND_SIGNED) != 0) |
309 | sign_extend (op); | |
252b5132 | 310 | (i is the instruction, o is a pointer to this structure, and op |
b84bf58a | 311 | is the result). |
252b5132 RH |
312 | |
313 | If this field is not NULL, then simply call it with the | |
9cf7e568 AM |
314 | instruction value. It will return the value of the operand. |
315 | *INVALID will be set to one by the extraction function if this | |
316 | operand type can not be extracted from this operand (i.e., the | |
317 | instruction does not match). If the operand is valid, *INVALID | |
318 | will not be changed. *INVALID will always be non-negative when | |
319 | used to extract a field from an instruction. | |
320 | ||
321 | The extraction function is also called by both the assembler and | |
322 | disassembler if an operand is optional, in which case the | |
323 | function should return the default value of the operand. | |
324 | *INVALID is negative in this case, and is the negative count of | |
325 | omitted optional operands up to and including this operand. */ | |
0f873fd5 | 326 | int64_t (*extract) (uint64_t instruction, ppc_cpu_t dialect, int *invalid); |
252b5132 RH |
327 | |
328 | /* One bit syntax flags. */ | |
329 | unsigned long flags; | |
330 | }; | |
331 | ||
332 | /* Elements in the table are retrieved by indexing with values from | |
333 | the operands field of the powerpc_opcodes table. */ | |
334 | ||
335 | extern const struct powerpc_operand powerpc_operands[]; | |
b84bf58a | 336 | extern const unsigned int num_powerpc_operands; |
252b5132 | 337 | |
b9c361e0 JL |
338 | /* Use with the shift field of a struct powerpc_operand to indicate |
339 | that BITM and SHIFT cannot be used to determine where the operand | |
340 | goes in the insn. */ | |
b6518b38 | 341 | #define PPC_OPSHIFT_INV (-1U << 31) |
b9c361e0 | 342 | |
7e0de605 AM |
343 | /* Values defined for the flags field of a struct powerpc_operand. |
344 | Keep the register bits low: They need to fit in an unsigned short. */ | |
252b5132 | 345 | |
7e0de605 AM |
346 | /* This operand names a register. The disassembler uses this to print |
347 | register names with a leading 'r'. */ | |
348 | #define PPC_OPERAND_GPR (0x1) | |
252b5132 | 349 | |
7e0de605 AM |
350 | /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ |
351 | #define PPC_OPERAND_GPR_0 (0x2) | |
252b5132 | 352 | |
7e0de605 AM |
353 | /* This operand names a floating point register. The disassembler |
354 | prints these with a leading 'f'. */ | |
355 | #define PPC_OPERAND_FPR (0x4) | |
252b5132 | 356 | |
7e0de605 AM |
357 | /* This operand names a vector unit register. The disassembler |
358 | prints these with a leading 'v'. */ | |
359 | #define PPC_OPERAND_VR (0x8) | |
252b5132 | 360 | |
7e0de605 AM |
361 | /* This operand names a vector-scalar unit register. The disassembler |
362 | prints these with a leading 'vs'. */ | |
363 | #define PPC_OPERAND_VSR (0x10) | |
364 | ||
365 | /* This operand may use the symbolic names for the CR fields (even | |
366 | without -mregnames), which are | |
252b5132 RH |
367 | lt 0 gt 1 eq 2 so 3 un 3 |
368 | cr0 0 cr1 1 cr2 2 cr3 3 | |
369 | cr4 4 cr5 5 cr6 6 cr7 7 | |
370 | These may be combined arithmetically, as in cr2*4+gt. These are | |
371 | only supported on the PowerPC, not the POWER. */ | |
7e0de605 | 372 | #define PPC_OPERAND_CR_BIT (0x20) |
252b5132 | 373 | |
7e0de605 | 374 | /* This is a CR FIELD that does not use symbolic names (unless |
96a86c01 AM |
375 | -mregnames is in effect). If both PPC_OPERAND_CR_BIT and |
376 | PPC_OPERAND_CR_REG are set then treat the field as per | |
377 | PPC_OPERAND_CR_BIT for assembly, but as if neither of these | |
378 | bits are set for disassembly. */ | |
7e0de605 | 379 | #define PPC_OPERAND_CR_REG (0x40) |
252b5132 | 380 | |
7e0de605 AM |
381 | /* This operand names a special purpose register. */ |
382 | #define PPC_OPERAND_SPR (0x80) | |
fdd12ef3 | 383 | |
7e0de605 AM |
384 | /* This operand names a paired-single graphics quantization register. */ |
385 | #define PPC_OPERAND_GQR (0x100) | |
252b5132 RH |
386 | |
387 | /* This operand is a relative branch displacement. The disassembler | |
388 | prints these symbolically if possible. */ | |
7e0de605 | 389 | #define PPC_OPERAND_RELATIVE (0x200) |
252b5132 RH |
390 | |
391 | /* This operand is an absolute branch address. The disassembler | |
392 | prints these symbolically if possible. */ | |
7e0de605 | 393 | #define PPC_OPERAND_ABSOLUTE (0x400) |
252b5132 | 394 | |
7e0de605 AM |
395 | /* This operand takes signed values. */ |
396 | #define PPC_OPERAND_SIGNED (0x800) | |
252b5132 | 397 | |
7e0de605 AM |
398 | /* This operand takes signed values, but also accepts a full positive |
399 | range of values when running in 32 bit mode. That is, if bits is | |
400 | 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, | |
401 | this flag is ignored. */ | |
402 | #define PPC_OPERAND_SIGNOPT (0x1000) | |
966f959b | 403 | |
7e0de605 AM |
404 | /* The next operand should be wrapped in parentheses rather than |
405 | separated from this one by a comma. This is used for the load and | |
406 | store instructions which want their operands to look like | |
407 | reg,displacement(reg) | |
408 | */ | |
409 | #define PPC_OPERAND_PARENS (0x2000) | |
966f959b | 410 | |
a6959011 | 411 | /* This operand is for the DS field in a DS form instruction. */ |
b84bf58a | 412 | #define PPC_OPERAND_DS (0x4000) |
adadcc0c AM |
413 | |
414 | /* This operand is for the DQ field in a DQ form instruction. */ | |
b84bf58a AM |
415 | #define PPC_OPERAND_DQ (0x8000) |
416 | ||
7e0de605 AM |
417 | /* This operand should be regarded as a negative number for the |
418 | purposes of overflow checking (i.e., the normal most negative | |
419 | number is disallowed and one more than the normal most positive | |
420 | number is allowed). This flag will only be set for a signed | |
421 | operand. */ | |
422 | #define PPC_OPERAND_NEGATIVE (0x10000) | |
423 | ||
3896c469 | 424 | /* Valid range of operand is 0..n rather than 0..n-1. */ |
7e0de605 | 425 | #define PPC_OPERAND_PLUS1 (0x20000) |
081ba1b3 | 426 | |
7e0de605 AM |
427 | /* This operand is optional, and is zero if omitted. This is used for |
428 | example, in the optional BF field in the comparison instructions. The | |
429 | assembler must count the number of operands remaining on the line, | |
430 | and the number of operands remaining for the opcode, and decide | |
431 | whether this operand is present or not. The disassembler should | |
432 | print this operand out only if it is not zero. */ | |
433 | #define PPC_OPERAND_OPTIONAL (0x80000) | |
b9c361e0 | 434 | |
7e0de605 AM |
435 | /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand |
436 | is omitted, then for the next operand use this operand value plus | |
437 | 1, ignoring the next operand field for the opcode. This wretched | |
438 | hack is needed because the Power rotate instructions can take | |
439 | either 4 or 5 operands. The disassembler should print this operand | |
440 | out regardless of the PPC_OPERAND_OPTIONAL field. */ | |
441 | #define PPC_OPERAND_NEXT (0x100000) | |
11a0cf2e | 442 | |
a5721ba2 AM |
443 | /* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is |
444 | only optional when generating 32-bit code. */ | |
7e0de605 AM |
445 | #define PPC_OPERAND_OPTIONAL32 (0x400000) |
446 | ||
447 | /* Xilinx APU and FSL related operands */ | |
448 | #define PPC_OPERAND_FSL (0x800000) | |
449 | #define PPC_OPERAND_FCR (0x1000000) | |
450 | #define PPC_OPERAND_UDI (0x2000000) | |
252b5132 RH |
451 | \f |
452 | /* The POWER and PowerPC assemblers use a few macros. We keep them | |
453 | with the operands table for simplicity. The macro table is an | |
454 | array of struct powerpc_macro. */ | |
455 | ||
456 | struct powerpc_macro | |
457 | { | |
458 | /* The macro name. */ | |
459 | const char *name; | |
460 | ||
461 | /* The number of operands the macro takes. */ | |
462 | unsigned int operands; | |
463 | ||
464 | /* One bit flags for the opcode. These are used to indicate which | |
465 | specific processors support the instructions. The values are the | |
466 | same as those for the struct powerpc_opcode flags field. */ | |
fa452fa6 | 467 | ppc_cpu_t flags; |
252b5132 RH |
468 | |
469 | /* A format string to turn the macro into a normal instruction. | |
470 | Each %N in the string is replaced with operand number N (zero | |
471 | based). */ | |
472 | const char *format; | |
473 | }; | |
474 | ||
475 | extern const struct powerpc_macro powerpc_macros[]; | |
476 | extern const int powerpc_num_macros; | |
477 | ||
776fc418 | 478 | extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *); |
69fe9ce5 | 479 | |
0f873fd5 | 480 | static inline int64_t |
9cf7e568 AM |
481 | ppc_optional_operand_value (const struct powerpc_operand *operand, |
482 | uint64_t insn, | |
483 | ppc_cpu_t dialect, | |
484 | int num_optional) | |
11a0cf2e | 485 | { |
9cf7e568 AM |
486 | if (operand->extract) |
487 | return (*operand->extract) (insn, dialect, &num_optional); | |
11a0cf2e PB |
488 | return 0; |
489 | } | |
490 | ||
08dc996f | 491 | /* PowerPC VLE insns. */ |
bb6bf75e AM |
492 | #define E_OPCODE_MASK 0xfc00f800 |
493 | ||
08dc996f AM |
494 | /* Form I16L, uses 16A relocs. */ |
495 | #define E_OR2I_INSN 0x7000C000 | |
496 | #define E_AND2I_DOT_INSN 0x7000C800 | |
497 | #define E_OR2IS_INSN 0x7000D000 | |
498 | #define E_LIS_INSN 0x7000E000 | |
499 | #define E_AND2IS_DOT_INSN 0x7000E800 | |
500 | ||
501 | /* Form I16A, uses 16D relocs. */ | |
502 | #define E_ADD2I_DOT_INSN 0x70008800 | |
503 | #define E_ADD2IS_INSN 0x70009000 | |
504 | #define E_CMP16I_INSN 0x70009800 | |
505 | #define E_MULL2I_INSN 0x7000A000 | |
506 | #define E_CMPL16I_INSN 0x7000A800 | |
507 | #define E_CMPH16I_INSN 0x7000B000 | |
508 | #define E_CMPHL16I_INSN 0x7000B800 | |
509 | ||
bb6bf75e AM |
510 | #define E_LI_INSN 0x70000000 |
511 | #define E_LI_MASK 0xfc008000 | |
512 | ||
1fe0971e TS |
513 | #ifdef __cplusplus |
514 | } | |
515 | #endif | |
516 | ||
252b5132 | 517 | #endif /* PPC_H */ |