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1 | /* Opcode decoder for the Renesas RL78 |
2 | Copyright 2011 | |
3 | Free Software Foundation, Inc. | |
4 | Written by DJ Delorie <dj@redhat.com> | |
5 | ||
6 | This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler. | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 3 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with this program; if not, write to the Free Software | |
20 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA | |
21 | 02110-1301, USA. */ | |
22 | ||
23 | /* The RL78 decoder in libopcodes is used by the simulator, gdb's | |
24 | analyzer, and the disassembler. Given an opcode data source, it | |
25 | decodes the next opcode into the following structures. */ | |
26 | ||
27 | #ifndef RL78_OPCODES_H_INCLUDED | |
28 | #define RL78_OPCODES_H_INCLUDED | |
29 | ||
30 | /* For the purposes of these structures, the RL78 registers are as | |
31 | follows, despite most of these being memory-mapped and | |
32 | bank-switched: */ | |
33 | typedef enum { | |
34 | RL78_Reg_None, | |
35 | /* The order of these matches the encodings. */ | |
36 | RL78_Reg_X, | |
37 | RL78_Reg_A, | |
38 | RL78_Reg_C, | |
39 | RL78_Reg_B, | |
40 | RL78_Reg_E, | |
41 | RL78_Reg_D, | |
42 | RL78_Reg_L, | |
43 | RL78_Reg_H, | |
44 | /* The order of these matches the encodings. */ | |
45 | RL78_Reg_AX, | |
46 | RL78_Reg_BC, | |
47 | RL78_Reg_DE, | |
48 | RL78_Reg_HL, | |
49 | /* Unordered. */ | |
50 | RL78_Reg_SP, | |
51 | RL78_Reg_PSW, | |
52 | RL78_Reg_CS, | |
53 | RL78_Reg_ES, | |
54 | RL78_Reg_PMC, | |
55 | RL78_Reg_MEM | |
56 | } RL78_Register; | |
57 | ||
58 | typedef enum | |
59 | { | |
60 | RL78_Byte = 0, | |
61 | RL78_Word | |
62 | } RL78_Size; | |
63 | ||
64 | typedef enum { | |
65 | RL78_Condition_T, | |
66 | RL78_Condition_F, | |
67 | RL78_Condition_C, | |
68 | RL78_Condition_NC, | |
69 | RL78_Condition_H, | |
70 | RL78_Condition_NH, | |
71 | RL78_Condition_Z, | |
72 | RL78_Condition_NZ | |
73 | } RL78_Condition; | |
74 | ||
75 | typedef enum { | |
76 | RL78_Operand_None = 0, | |
77 | RL78_Operand_Immediate, /* #addend */ | |
78 | RL78_Operand_Register, /* reg */ | |
79 | RL78_Operand_Indirect, /* [reg + reg2 + addend] */ | |
80 | RL78_Operand_Bit, /* reg.bit */ | |
81 | RL78_Operand_BitIndirect, /* [reg+reg2+addend].bit */ | |
82 | RL78_Operand_PreDec, /* [--reg] = push */ | |
83 | RL78_Operand_PostInc /* [reg++] = pop */ | |
84 | } RL78_Operand_Type; | |
85 | ||
86 | typedef enum | |
87 | { | |
88 | RLO_unknown, | |
89 | RLO_add, /* d += s */ | |
90 | RLO_addc, /* d += s + CY */ | |
91 | RLO_and, /* d &= s (byte, word, bit) */ | |
92 | RLO_branch, /* pc = d */ | |
93 | RLO_branch_cond, /* pc = d if cond(src) */ | |
94 | RLO_branch_cond_clear, /* pc = d if cond(src), and clear(src) */ | |
95 | RLO_break, /* BRK */ | |
96 | RLO_call, /* call */ | |
97 | RLO_cmp, /* cmp d, s */ | |
98 | RLO_divhu, /* DIVHU */ | |
99 | RLO_divwu, /* DIVWU */ | |
100 | RLO_halt, /* HALT */ | |
101 | RLO_mov, /* d = s */ | |
102 | RLO_mach, /* MACH */ | |
103 | RLO_machu, /* MACHU */ | |
104 | RLO_mulu, /* MULU */ | |
105 | RLO_mulh, /* MULH */ | |
106 | RLO_mulhu, /* MULHU */ | |
107 | RLO_nop, /* NOP */ | |
108 | RLO_or, /* d |= s */ | |
109 | RLO_ret, /* RET */ | |
110 | RLO_reti, /* RETI */ | |
111 | RLO_rol, /* d <<= s, MSB to LSB and CY */ | |
112 | RLO_rolc, /* d <<= s, MSB to CY, CY, to LSB */ | |
113 | RLO_ror, /* d >>= s, LSB to MSB and CY */ | |
114 | RLO_rorc, /* d >>= s, LSB to CY, CY, to MSB */ | |
115 | RLO_sar, /* d >>= s, signed */ | |
116 | RLO_sel, /* rb = s */ | |
117 | RLO_shr, /* d >>= s, unsigned */ | |
118 | RLO_shl, /* d <<= s */ | |
119 | RLO_skip, /* skip next insn is cond(s) */ | |
120 | RLO_stop, /* STOP */ | |
121 | RLO_sub, /* d -= s */ | |
122 | RLO_subc, /* d -= s - CY */ | |
123 | RLO_xch, /* swap d, s */ | |
124 | RLO_xor, /* d ^= s */ | |
125 | } RL78_Opcode_ID; | |
126 | ||
127 | typedef struct { | |
128 | RL78_Operand_Type type; | |
129 | int addend; | |
130 | RL78_Register reg : 8; | |
131 | RL78_Register reg2 : 8; | |
132 | unsigned char bit_number : 4; | |
133 | unsigned char condition : 3; | |
134 | unsigned char use_es : 1; | |
135 | } RL78_Opcode_Operand; | |
136 | ||
137 | /* PSW flag bits */ | |
138 | #define RL78_PSW_IE 0x80 | |
139 | #define RL78_PSW_Z 0x40 | |
140 | #define RL78_PSW_RBS1 0x20 | |
141 | #define RL78_PSW_AC 0x10 | |
142 | #define RL78_PSW_RBS0 0x08 | |
143 | #define RL78_PSW_ISP1 0x04 | |
144 | #define RL78_PSW_ISP0 0x02 | |
145 | #define RL78_PSW_CY 0x01 | |
146 | ||
147 | #define RL78_SFR_SP 0xffff8 | |
148 | #define RL78_SFR_PSW 0xffffa | |
149 | #define RL78_SFR_CS 0xffffc | |
150 | #define RL78_SFR_ES 0xffffd | |
151 | #define RL78_SFR_PMC 0xffffe | |
152 | #define RL78_SFR_MEM 0xfffff | |
153 | ||
154 | typedef struct | |
155 | { | |
156 | int lineno; | |
157 | RL78_Opcode_ID id:24; | |
158 | unsigned flags:8; /* PSW mask, for side effects only */ | |
159 | int n_bytes; | |
160 | char * syntax; | |
161 | RL78_Size size; | |
162 | /* By convention, these are destination, source. */ | |
163 | RL78_Opcode_Operand op[2]; | |
164 | } RL78_Opcode_Decoded; | |
165 | ||
166 | int rl78_decode_opcode (unsigned long, RL78_Opcode_Decoded *, int (*)(void *), void *); | |
167 | ||
168 | #endif |