[sim/rx]
[deliverable/binutils-gdb.git] / include / opcode / rx.h
CommitLineData
c7927a3c 1/* Opcode decoder for the Renesas RX
e4e42b45 2 Copyright 2008, 2009, 2010
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3 Free Software Foundation, Inc.
4 Written by DJ Delorie <dj@redhat.com>
5
6 This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
e4e42b45 10 the Free Software Foundation; either version 3 of the License, or
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11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23/* The RX decoder in libopcodes is used by the simulator, gdb's
24 analyzer, and the disassembler. Given an opcode data source,
25 it decodes the next opcode into the following structures. */
26
27typedef enum
28{
29 RX_AnySize = 0,
30 RX_Byte, /* undefined extension */
31 RX_UByte,
32 RX_SByte,
33 RX_Word, /* undefined extension */
34 RX_UWord,
35 RX_SWord,
36 RX_3Byte,
37 RX_Long,
38} RX_Size;
39
40typedef enum
41{
42 RX_Operand_None,
43 RX_Operand_Immediate, /* #addend */
44 RX_Operand_Register, /* Rn */
45 RX_Operand_Indirect, /* [Rn + addend] */
46 RX_Operand_Postinc, /* [Rn+] */
47 RX_Operand_Predec, /* [-Rn] */
48 RX_Operand_Condition, /* eq, gtu, etc */
49 RX_Operand_Flag, /* [UIOSZC] */
50} RX_Operand_Type;
51
52typedef enum
53{
54 RXO_unknown,
55 RXO_mov, /* d = s (signed) */
56 RXO_movbi, /* d = [s,s2] (signed) */
57 RXO_movbir, /* [s,s2] = d (signed) */
58 RXO_pushm, /* s..s2 */
59 RXO_popm, /* s..s2 */
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60 RXO_xchg, /* s <-> d */
61 RXO_stcc, /* d = s if cond(s2) */
62 RXO_rtsd, /* rtsd, 1=imm, 2-0 = reg if reg type */
63
64 /* These are all either d OP= s or, if s2 is set, d = s OP s2. Note
65 that d may be "None". */
66 RXO_and,
67 RXO_or,
68 RXO_xor,
69 RXO_add,
70 RXO_sub,
71 RXO_mul,
72 RXO_div,
73 RXO_divu,
74 RXO_shll,
75 RXO_shar,
76 RXO_shlr,
77
78 RXO_adc, /* d = d + s + carry */
79 RXO_sbb, /* d = d - s - ~carry */
80 RXO_abs, /* d = |s| */
81 RXO_max, /* d = max(d,s) */
82 RXO_min, /* d = min(d,s) */
83 RXO_emul, /* d:64 = d:32 * s */
84 RXO_emulu, /* d:64 = d:32 * s (unsigned) */
85 RXO_ediv, /* d:64 / s; d = quot, d+1 = rem */
86 RXO_edivu, /* d:64 / s; d = quot, d+1 = rem */
87
88 RXO_rolc, /* d <<= 1 through carry */
89 RXO_rorc, /* d >>= 1 through carry*/
90 RXO_rotl, /* d <<= #s without carry */
91 RXO_rotr, /* d >>= #s without carry*/
92 RXO_revw, /* d = revw(s) */
93 RXO_revl, /* d = revl(s) */
94 RXO_branch, /* pc = d if cond(s) */
95 RXO_branchrel,/* pc += d if cond(s) */
96 RXO_jsr, /* pc = d */
97 RXO_jsrrel, /* pc += d */
98 RXO_rts,
99 RXO_nop,
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100 RXO_nop2,
101 RXO_nop3,
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102
103 RXO_scmpu,
104 RXO_smovu,
105 RXO_smovb,
106 RXO_suntil,
107 RXO_swhile,
108 RXO_smovf,
109 RXO_sstr,
110
111 RXO_rmpa,
112 RXO_mulhi,
113 RXO_mullo,
114 RXO_machi,
115 RXO_maclo,
116 RXO_mvtachi,
117 RXO_mvtaclo,
118 RXO_mvfachi,
119 RXO_mvfacmi,
120 RXO_mvfaclo,
121 RXO_racw,
122
123 RXO_sat, /* sat(d) */
124 RXO_satr,
125
126 RXO_fadd, /* d op= s */
127 RXO_fcmp,
128 RXO_fsub,
129 RXO_ftoi,
130 RXO_fmul,
131 RXO_fdiv,
132 RXO_round,
133 RXO_itof,
134
135 RXO_bset, /* d |= (1<<s) */
136 RXO_bclr, /* d &= ~(1<<s) */
137 RXO_btst, /* s & (1<<s2) */
138 RXO_bnot, /* d ^= (1<<s) */
139 RXO_bmcc, /* d<s> = cond(s2) */
140
141 RXO_clrpsw, /* flag index in d */
142 RXO_setpsw, /* flag index in d */
0d734b5d 143 RXO_mvtipl, /* new IPL in s */
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144
145 RXO_rtfi,
146 RXO_rte,
147 RXO_rtd, /* undocumented */
148 RXO_brk,
149 RXO_dbt, /* undocumented */
150 RXO_int, /* vector id in s */
151 RXO_stop,
152 RXO_wait,
153
154 RXO_sccnd, /* d = cond(s) ? 1 : 0 */
155} RX_Opcode_ID;
156
157/* Condition bitpatterns, as registers. */
158#define RXC_eq 0
159#define RXC_z 0
160#define RXC_ne 1
161#define RXC_nz 1
162#define RXC_c 2
163#define RXC_nc 3
164#define RXC_gtu 4
165#define RXC_leu 5
166#define RXC_pz 6
167#define RXC_n 7
168#define RXC_ge 8
169#define RXC_lt 9
170#define RXC_gt 10
171#define RXC_le 11
172#define RXC_o 12
173#define RXC_no 13
174#define RXC_always 14
175#define RXC_never 15
176
177typedef struct
178{
179 RX_Operand_Type type;
180 int reg;
181 int addend;
182 RX_Size size;
183} RX_Opcode_Operand;
184
185typedef struct
186{
187 RX_Opcode_ID id;
188 int n_bytes;
189 int prefix;
190 char * syntax;
191 RX_Size size;
192 /* By convention, these are destination, source1, source2. */
193 RX_Opcode_Operand op[3];
194
195 /* The logic here is:
196 newflags = (oldflags & ~(int)flags_0) | flags_1 | (op_flags & flags_s)
197 Only the O, S, Z, and C flags are affected. */
198 char flags_0; /* This also clears out flags-to-be-set. */
199 char flags_1;
200 char flags_s;
201} RX_Opcode_Decoded;
202
203/* Within the syntax, %c-style format specifiers are as follows:
204
205 %% = '%' character
206 %0 = operand[0] (destination)
207 %1 = operand[1] (source)
208 %2 = operand[2] (2nd source)
209 %s = operation size (b/w/l)
210 %SN = operand size [N] (N=0,1,2)
211 %aN = op[N] as an address (N=0,1,2)
212
213 Register numbers 0..15 are general registers. 16..31 are control
214 registers. 32..47 are condition codes. */
215
216int rx_decode_opcode (unsigned long, RX_Opcode_Decoded *, int (*)(void *), void *);
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