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1 | /* score-datadep.h -- Score Instructions data dependency table |
2 | Copyright 2006 Free Software Foundation, Inc. | |
3 | Contributed by: | |
4 | Mei Ligang (ligang@sunnorth.com.cn) | |
5 | Pei-Lin Tsai (pltsai@sunplus.com) | |
6 | ||
7 | This file is part of GAS, the GNU Assembler. | |
8 | ||
9 | GAS is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2, or (at your option) | |
12 | any later version. | |
13 | ||
14 | GAS is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with GAS; see the file COPYING. If not, write to the Free | |
21 | Software Foundation, Inc., 51 Franklin Street - Fifth Floor, | |
22 | Boston, MA 02110-1301, USA. */ | |
23 | ||
24 | #ifndef SCORE_DATA_DEPENDENCY_H | |
25 | #define SCORE_DATA_DEPENDENCY_H | |
26 | ||
27 | #define INSN_NAME_LEN 16 | |
28 | ||
29 | enum insn_type_for_dependency | |
30 | { | |
31 | D_pce, | |
32 | D_cond_br, | |
33 | D_cond_mv, | |
34 | D_cached, | |
35 | D_cachei, | |
36 | D_ldst, | |
37 | D_ldcombine, | |
38 | D_mtcr, | |
39 | D_mfcr, | |
40 | D_mfsr, | |
41 | D_mftlb, | |
42 | D_mtptlb, | |
43 | D_mtrtlb, | |
44 | D_stlb, | |
45 | D_all_insn | |
46 | }; | |
47 | ||
48 | struct insn_to_dependency | |
49 | { | |
50 | char *insn_name; | |
51 | enum insn_type_for_dependency type; | |
52 | }; | |
53 | ||
54 | struct data_dependency | |
55 | { | |
56 | enum insn_type_for_dependency pre_insn_type; | |
57 | char pre_reg[6]; | |
58 | enum insn_type_for_dependency cur_insn_type; | |
59 | char cur_reg[6]; | |
60 | int bubblenum_7; | |
61 | int bubblenum_5; | |
62 | int warn_or_error; /* warning - 0; error - 1 */ | |
63 | }; | |
64 | ||
65 | static const struct insn_to_dependency insn_to_dependency_table[] = | |
66 | { | |
67 | /* pce instruction. */ | |
68 | {"pce", D_pce}, | |
69 | /* conditional branch instruction. */ | |
70 | {"bcs", D_cond_br}, | |
71 | {"bcc", D_cond_br}, | |
72 | {"bgtu", D_cond_br}, | |
73 | {"bleu", D_cond_br}, | |
74 | {"beq", D_cond_br}, | |
75 | {"bne", D_cond_br}, | |
76 | {"bgt", D_cond_br}, | |
77 | {"ble", D_cond_br}, | |
78 | {"bge", D_cond_br}, | |
79 | {"blt", D_cond_br}, | |
80 | {"bmi", D_cond_br}, | |
81 | {"bpl", D_cond_br}, | |
82 | {"bvs", D_cond_br}, | |
83 | {"bvc", D_cond_br}, | |
84 | {"bcsl", D_cond_br}, | |
85 | {"bccl", D_cond_br}, | |
86 | {"bgtul", D_cond_br}, | |
87 | {"bleul", D_cond_br}, | |
88 | {"beql", D_cond_br}, | |
89 | {"bnel", D_cond_br}, | |
90 | {"bgtl", D_cond_br}, | |
91 | {"blel", D_cond_br}, | |
92 | {"bgel", D_cond_br}, | |
93 | {"bltl", D_cond_br}, | |
94 | {"bmil", D_cond_br}, | |
95 | {"bpll", D_cond_br}, | |
96 | {"bvsl", D_cond_br}, | |
97 | {"bvcl", D_cond_br}, | |
98 | {"bcs!", D_cond_br}, | |
99 | {"bcc!", D_cond_br}, | |
100 | {"bgtu!", D_cond_br}, | |
101 | {"bleu!", D_cond_br}, | |
102 | {"beq!", D_cond_br}, | |
103 | {"bne!", D_cond_br}, | |
104 | {"bgt!", D_cond_br}, | |
105 | {"ble!", D_cond_br}, | |
106 | {"bge!", D_cond_br}, | |
107 | {"blt!", D_cond_br}, | |
108 | {"bmi!", D_cond_br}, | |
109 | {"bpl!", D_cond_br}, | |
110 | {"bvs!", D_cond_br}, | |
111 | {"bvc!", D_cond_br}, | |
112 | {"brcs", D_cond_br}, | |
113 | {"brcc", D_cond_br}, | |
114 | {"brgtu", D_cond_br}, | |
115 | {"brleu", D_cond_br}, | |
116 | {"breq", D_cond_br}, | |
117 | {"brne", D_cond_br}, | |
118 | {"brgt", D_cond_br}, | |
119 | {"brle", D_cond_br}, | |
120 | {"brge", D_cond_br}, | |
121 | {"brlt", D_cond_br}, | |
122 | {"brmi", D_cond_br}, | |
123 | {"brpl", D_cond_br}, | |
124 | {"brvs", D_cond_br}, | |
125 | {"brvc", D_cond_br}, | |
126 | {"brcsl", D_cond_br}, | |
127 | {"brccl", D_cond_br}, | |
128 | {"brgtul", D_cond_br}, | |
129 | {"brleul", D_cond_br}, | |
130 | {"breql", D_cond_br}, | |
131 | {"brnel", D_cond_br}, | |
132 | {"brgtl", D_cond_br}, | |
133 | {"brlel", D_cond_br}, | |
134 | {"brgel", D_cond_br}, | |
135 | {"brltl", D_cond_br}, | |
136 | {"brmil", D_cond_br}, | |
137 | {"brpll", D_cond_br}, | |
138 | {"brvsl", D_cond_br}, | |
139 | {"brvcl", D_cond_br}, | |
140 | {"brcs!", D_cond_br}, | |
141 | {"brcc!", D_cond_br}, | |
142 | {"brgtu!", D_cond_br}, | |
143 | {"brleu!", D_cond_br}, | |
144 | {"breq!", D_cond_br}, | |
145 | {"brne!", D_cond_br}, | |
146 | {"brgt!", D_cond_br}, | |
147 | {"brle!", D_cond_br}, | |
148 | {"brge!", D_cond_br}, | |
149 | {"brlt!", D_cond_br}, | |
150 | {"brmi!", D_cond_br}, | |
151 | {"brpl!", D_cond_br}, | |
152 | {"brvs!", D_cond_br}, | |
153 | {"brvc!", D_cond_br}, | |
154 | {"brcsl!", D_cond_br}, | |
155 | {"brccl!", D_cond_br}, | |
156 | {"brgtul!", D_cond_br}, | |
157 | {"brleul!", D_cond_br}, | |
158 | {"breql!", D_cond_br}, | |
159 | {"brnel!", D_cond_br}, | |
160 | {"brgtl!", D_cond_br}, | |
161 | {"brlel!", D_cond_br}, | |
162 | {"brgel!", D_cond_br}, | |
163 | {"brltl!", D_cond_br}, | |
164 | {"brmil!", D_cond_br}, | |
165 | {"brpll!", D_cond_br}, | |
166 | {"brvsl!", D_cond_br}, | |
167 | {"brvcl!", D_cond_br}, | |
168 | /* conditional move instruction. */ | |
169 | {"mvcs", D_cond_mv}, | |
170 | {"mvcc", D_cond_mv}, | |
171 | {"mvgtu", D_cond_mv}, | |
172 | {"mvleu", D_cond_mv}, | |
173 | {"mveq", D_cond_mv}, | |
174 | {"mvne", D_cond_mv}, | |
175 | {"mvgt", D_cond_mv}, | |
176 | {"mvle", D_cond_mv}, | |
177 | {"mvge", D_cond_mv}, | |
178 | {"mvlt", D_cond_mv}, | |
179 | {"mvmi", D_cond_mv}, | |
180 | {"mvpl", D_cond_mv}, | |
181 | {"mvvs", D_cond_mv}, | |
182 | {"mvvc", D_cond_mv}, | |
183 | /* move spectial instruction. */ | |
184 | {"mtcr", D_mtcr}, | |
185 | {"mftlb", D_mftlb}, | |
186 | {"mtptlb", D_mtptlb}, | |
187 | {"mtrtlb", D_mtrtlb}, | |
188 | {"stlb", D_stlb}, | |
189 | {"mfcr", D_mfcr}, | |
190 | {"mfsr", D_mfsr}, | |
191 | /* cache instruction. */ | |
192 | {"cache 8", D_cached}, | |
193 | {"cache 9", D_cached}, | |
194 | {"cache 10", D_cached}, | |
195 | {"cache 11", D_cached}, | |
196 | {"cache 12", D_cached}, | |
197 | {"cache 13", D_cached}, | |
198 | {"cache 14", D_cached}, | |
199 | {"cache 24", D_cached}, | |
200 | {"cache 26", D_cached}, | |
201 | {"cache 27", D_cached}, | |
202 | {"cache 29", D_cached}, | |
203 | {"cache 30", D_cached}, | |
204 | {"cache 31", D_cached}, | |
205 | {"cache 0", D_cachei}, | |
206 | {"cache 1", D_cachei}, | |
207 | {"cache 2", D_cachei}, | |
208 | {"cache 3", D_cachei}, | |
209 | {"cache 4", D_cachei}, | |
210 | {"cache 16", D_cachei}, | |
211 | {"cache 17", D_cachei}, | |
212 | /* load/store instruction. */ | |
213 | {"lb", D_ldst}, | |
214 | {"lbu", D_ldst}, | |
215 | {"lbu!", D_ldst}, | |
216 | {"lbup!", D_ldst}, | |
217 | {"lh", D_ldst}, | |
218 | {"lhu", D_ldst}, | |
219 | {"lh!", D_ldst}, | |
220 | {"lhp!", D_ldst}, | |
221 | {"lw", D_ldst}, | |
222 | {"lw!", D_ldst}, | |
223 | {"lwp!", D_ldst}, | |
224 | {"sb", D_ldst}, | |
225 | {"sb!", D_ldst}, | |
226 | {"sbp!", D_ldst}, | |
227 | {"sh", D_ldst}, | |
228 | {"sh!", D_ldst}, | |
229 | {"shp!", D_ldst}, | |
230 | {"sw", D_ldst}, | |
231 | {"sw!", D_ldst}, | |
232 | {"swp!", D_ldst}, | |
233 | {"alw", D_ldst}, | |
234 | {"asw", D_ldst}, | |
235 | {"push!", D_ldst}, | |
236 | {"pushhi!", D_ldst}, | |
237 | {"pop!", D_ldst}, | |
238 | {"pophi!", D_ldst}, | |
239 | {"ldc1", D_ldst}, | |
240 | {"ldc2", D_ldst}, | |
241 | {"ldc3", D_ldst}, | |
242 | {"stc1", D_ldst}, | |
243 | {"stc2", D_ldst}, | |
244 | {"stc3", D_ldst}, | |
245 | {"scb", D_ldst}, | |
246 | {"scw", D_ldst}, | |
247 | {"sce", D_ldst}, | |
248 | /* load combine instruction. */ | |
249 | {"lcb", D_ldcombine}, | |
250 | {"lcw", D_ldcombine}, | |
251 | {"lce", D_ldcombine}, | |
252 | }; | |
253 | ||
254 | static const struct data_dependency data_dependency_table[] = | |
255 | { | |
256 | /* Condition register. */ | |
257 | {D_mtcr, "cr1", D_pce, "", 2, 1, 1}, | |
258 | {D_mtcr, "cr1", D_cond_br, "", 1, 0, 1}, | |
259 | {D_mtcr, "cr1", D_cond_mv, "", 1, 0, 1}, | |
260 | /* Status regiser. */ | |
261 | {D_mtcr, "cr0", D_all_insn, "", 5, 4, 0}, | |
262 | /* CCR regiser. */ | |
263 | {D_mtcr, "cr4", D_all_insn, "", 6, 5, 0}, | |
264 | /* EntryHi/EntryLo register. */ | |
265 | {D_mftlb, "", D_mtptlb, "", 1, 1, 1}, | |
266 | {D_mftlb, "", D_mtrtlb, "", 1, 1, 1}, | |
267 | {D_mftlb, "", D_stlb, "", 1, 1,1}, | |
268 | {D_mftlb, "", D_mfcr, "cr11", 1, 1, 1}, | |
269 | {D_mftlb, "", D_mfcr, "cr12", 1, 1, 1}, | |
270 | /* Index register. */ | |
271 | {D_stlb, "", D_mtptlb, "", 1, 1, 1}, | |
272 | {D_stlb, "", D_mftlb, "", 1, 1, 1}, | |
273 | {D_stlb, "", D_mfcr, "cr8", 2, 2, 1}, | |
274 | /* Cache. */ | |
275 | {D_cached, "", D_ldst, "", 1, 1, 0}, | |
276 | {D_cached, "", D_ldcombine, "", 1, 1, 0}, | |
277 | {D_cachei, "", D_all_insn, "", 5, 4, 0}, | |
278 | /* Load combine. */ | |
279 | {D_ldcombine, "", D_mfsr, "sr1", 3, 3, 1}, | |
280 | }; | |
281 | ||
282 | #endif |