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7b22a53c | 1 | /* Definitions for opcode table for the sparc. |
5583be24 ILT |
2 | Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 1997 |
3 | Free Software Foundation, Inc. | |
47660bef KR |
4 | |
5 | This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and | |
6 | the GNU Binutils. | |
0227e918 | 7 | |
0227e918 SC |
8 | GAS/GDB is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2, or (at your option) | |
11 | any later version. | |
12 | ||
13 | GAS/GDB is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
17 | ||
18 | You should have received a copy of the GNU General Public License | |
19 | along with GAS or GDB; see the file COPYING. If not, write to | |
44292d2e DE |
20 | the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | Boston, MA 02111-1307, USA. */ | |
0227e918 | 22 | |
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23 | #include <ansidecl.h> |
24 | ||
7b22a53c | 25 | /* The SPARC opcode table (and other related data) is defined in |
f2c42ba4 | 26 | the opcodes library in sparc-opc.c. If you change anything here, make |
7b22a53c KR |
27 | sure you fix up that file, and vice versa. */ |
28 | ||
0227e918 SC |
29 | /* FIXME-someday: perhaps the ,a's and such should be embedded in the |
30 | instruction's name rather than the args. This would make gas faster, pinsn | |
31 | slower, but would mess up some macros a bit. xoxorich. */ | |
32 | ||
7484896b DE |
33 | /* List of instruction sets variations. |
34 | These values are such that each element is either a superset of a | |
803108ab | 35 | preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P |
7484896b DE |
36 | returns non-zero. |
37 | The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. | |
38 | Don't change this without updating sparc-opc.c. */ | |
39 | ||
40 | enum sparc_opcode_arch_val { | |
41 | SPARC_OPCODE_ARCH_V6 = 0, | |
42 | SPARC_OPCODE_ARCH_V7, | |
43 | SPARC_OPCODE_ARCH_V8, | |
8c3f315e | 44 | SPARC_OPCODE_ARCH_SPARCLET, |
7484896b DE |
45 | SPARC_OPCODE_ARCH_SPARCLITE, |
46 | /* v9 variants must appear last */ | |
47 | SPARC_OPCODE_ARCH_V9, | |
48 | SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */ | |
49 | SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */ | |
50 | }; | |
7b22a53c | 51 | |
7484896b DE |
52 | /* The highest architecture in the table. */ |
53 | #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) | |
54 | ||
4be1b313 DE |
55 | /* Given an enum sparc_opcode_arch_val, return the bitmask to use in |
56 | insn encoding/decoding. */ | |
57 | #define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch)) | |
58 | ||
5583be24 ILT |
59 | /* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */ |
60 | #define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9) | |
61 | ||
7484896b DE |
62 | /* Table of cpu variants. */ |
63 | ||
64 | struct sparc_opcode_arch { | |
65 | const char *name; | |
8c3f315e | 66 | /* Mask of sparc_opcode_arch_val's supported. |
4be1b313 DE |
67 | EG: For v7 this would be |
68 | (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)). | |
69 | These are short's because sparc_opcode.architecture is. */ | |
8c3f315e | 70 | short supported; |
0227e918 SC |
71 | }; |
72 | ||
7484896b DE |
73 | extern const struct sparc_opcode_arch sparc_opcode_archs[]; |
74 | ||
8c3f315e DE |
75 | /* Given architecture name, look up it's sparc_opcode_arch_val value. */ |
76 | extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (); | |
0227e918 | 77 | |
8c3f315e DE |
78 | /* Return the bitmask of supported architectures for ARCH. */ |
79 | #define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported) | |
47660bef | 80 | |
8c3f315e DE |
81 | /* Non-zero if ARCH1 conflicts with ARCH2. |
82 | IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */ | |
7484896b | 83 | #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ |
8c3f315e DE |
84 | (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ |
85 | != SPARC_OPCODE_SUPPORTED (ARCH1)) \ | |
86 | && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \ | |
87 | != SPARC_OPCODE_SUPPORTED (ARCH2))) | |
7484896b DE |
88 | |
89 | /* Structure of an opcode table entry. */ | |
47660bef | 90 | |
0227e918 | 91 | struct sparc_opcode { |
8c3f315e DE |
92 | const char *name; |
93 | unsigned long match; /* Bits that must be set. */ | |
94 | unsigned long lose; /* Bits that must not be set. */ | |
95 | const char *args; | |
96 | /* This was called "delayed" in versions before the flags. */ | |
97 | char flags; | |
98 | short architecture; /* Bitmask of sparc_opcode_arch_val's. */ | |
0227e918 SC |
99 | }; |
100 | ||
101 | #define F_DELAYED 1 /* Delayed branch */ | |
102 | #define F_ALIAS 2 /* Alias for a "real" instruction */ | |
f2c42ba4 KR |
103 | #define F_UNBR 4 /* Unconditional branch */ |
104 | #define F_CONDBR 8 /* Conditional branch */ | |
105 | #define F_JSR 16 /* Subroutine call */ | |
b21efdbe ILT |
106 | #define F_FLOAT 32 /* Floating point instruction (not a branch) */ |
107 | #define F_FBR 64 /* Floating point branch */ | |
f2c42ba4 | 108 | /* FIXME: Add F_ANACHRONISTIC flag for v9. */ |
0227e918 SC |
109 | |
110 | /* | |
111 | ||
112 | All sparc opcodes are 32 bits, except for the `set' instruction (really a | |
113 | macro), which is 64 bits. It is handled as a special case. | |
114 | ||
115 | The match component is a mask saying which bits must match a particular | |
116 | opcode in order for an instruction to be an instance of that opcode. | |
117 | ||
118 | The args component is a string containing one character for each operand of the | |
119 | instruction. | |
120 | ||
121 | Kinds of operands: | |
122 | # Number used by optimizer. It is ignored. | |
123 | 1 rs1 register. | |
124 | 2 rs2 register. | |
125 | d rd register. | |
126 | e frs1 floating point register. | |
127 | v frs1 floating point register (double/even). | |
128 | V frs1 floating point register (quad/multiple of 4). | |
129 | f frs2 floating point register. | |
130 | B frs2 floating point register (double/even). | |
131 | R frs2 floating point register (quad/multiple of 4). | |
0227e918 SC |
132 | g frsd floating point register. |
133 | H frsd floating point register (double/even). | |
134 | J frsd floating point register (quad/multiple of 4). | |
135 | b crs1 coprocessor register | |
136 | c crs2 coprocessor register | |
137 | D crsd coprocessor register | |
138 | m alternate space register (asr) in rd | |
139 | M alternate space register (asr) in rs1 | |
140 | h 22 high bits. | |
5583be24 ILT |
141 | X 5 bit unsigned immediate |
142 | Y 6 bit unsigned immediate | |
f2c42ba4 KR |
143 | K MEMBAR mask (7 bits). (v9) |
144 | j 10 bit Immediate. (v9) | |
0227e918 SC |
145 | I 11 bit Immediate. (v9) |
146 | i 13 bit Immediate. | |
cc35cb05 | 147 | n 22 bit immediate. |
0227e918 SC |
148 | k 2+14 bit PC relative immediate. (v9) |
149 | G 19 bit PC relative immediate. (v9) | |
150 | l 22 bit PC relative immediate. | |
151 | L 30 bit PC relative immediate. | |
152 | a Annul. The annul bit is set. | |
153 | A Alternate address space. Stored as 8 bits. | |
154 | C Coprocessor state register. | |
155 | F floating point state register. | |
156 | p Processor state register. | |
157 | N Branch predict clear ",pn" (v9) | |
158 | T Branch predict set ",pt" (v9) | |
f2c42ba4 KR |
159 | z %icc. (v9) |
160 | Z %xcc. (v9) | |
0227e918 | 161 | q Floating point queue. |
4be1b313 DE |
162 | r Single register that is both rs1 and rd. |
163 | O Single register that is both rs2 and rd. | |
0227e918 SC |
164 | Q Coprocessor queue. |
165 | S Special case. | |
166 | t Trap base register. | |
167 | w Window invalid mask register. | |
168 | y Y register. | |
8c3f315e DE |
169 | u sparclet coprocessor registers in rd position |
170 | U sparclet coprocessor registers in rs1 position | |
f2c42ba4 KR |
171 | E %ccr. (v9) |
172 | s %fprs. (v9) | |
0227e918 | 173 | P %pc. (v9) |
0227e918 | 174 | W %tick. (v9) |
47660bef | 175 | o %asi. (v9) |
f2c42ba4 KR |
176 | 6 %fcc0. (v9) |
177 | 7 %fcc1. (v9) | |
178 | 8 %fcc2. (v9) | |
179 | 9 %fcc3. (v9) | |
47660bef KR |
180 | ! Privileged Register in rd (v9) |
181 | ? Privileged Register in rs1 (v9) | |
f2c42ba4 KR |
182 | * Prefetch function constant. (v9) |
183 | x OPF field (v9 impdep). | |
5583be24 | 184 | 0 32/64 bit immediate for set or setx (v9) insns |
0227e918 SC |
185 | |
186 | The following chars are unused: (note: ,[] are used as punctuation) | |
5583be24 | 187 | [345] |
0227e918 SC |
188 | |
189 | */ | |
190 | ||
0227e918 SC |
191 | #define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */ |
192 | #define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */ | |
47660bef | 193 | #define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */ |
0227e918 | 194 | #define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */ |
f2c42ba4 | 195 | #define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */ |
0227e918 SC |
196 | #define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */ |
197 | #define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */ | |
198 | #define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */ | |
199 | #define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */ | |
200 | #define F1(x) (OP(x)) | |
201 | #define DISP30(x) ((x)&0x3fffffff) | |
202 | #define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */ | |
203 | #define RS2(x) ((x)&0x1f) /* rs2 field */ | |
204 | #define SIMM13(x) ((x)&0x1fff) /* simm13 field */ | |
205 | #define RD(x) (((x)&0x1f) << 25) /* destination register field */ | |
206 | #define RS1(x) (((x)&0x1f) << 14) /* rs1 field */ | |
207 | #define ASI_RS2(x) (SIMM13(x)) | |
22472179 | 208 | #define MEMBAR(x) ((x)&0x7f) |
5583be24 | 209 | #define SLCPOP(x) (((x)&0x7f) << 6) /* sparclet cpop */ |
0227e918 SC |
210 | |
211 | #define ANNUL (1<<29) | |
f59db855 | 212 | #define BPRED (1<<19) /* v9 */ |
0227e918 SC |
213 | #define IMMED F3I(1) |
214 | #define RD_G0 RD(~0) | |
215 | #define RS1_G0 RS1(~0) | |
216 | #define RS2_G0 RS2(~0) | |
217 | ||
7b22a53c | 218 | extern struct sparc_opcode sparc_opcodes[]; |
7484896b | 219 | extern const int sparc_num_opcodes; |
0227e918 | 220 | |
5583be24 ILT |
221 | extern int sparc_encode_asi PARAMS ((const char *)); |
222 | extern const char *sparc_decode_asi PARAMS ((int)); | |
223 | extern int sparc_encode_membar PARAMS ((const char *)); | |
224 | extern const char *sparc_decode_membar PARAMS ((int)); | |
225 | extern int sparc_encode_prefetch PARAMS ((const char *)); | |
226 | extern const char *sparc_decode_prefetch PARAMS ((int)); | |
227 | extern int sparc_encode_sparclet_cpreg PARAMS ((const char *)); | |
228 | extern const char *sparc_decode_sparclet_cpreg PARAMS ((int)); | |
44292d2e | 229 | |
0227e918 SC |
230 | /* |
231 | * Local Variables: | |
232 | * fill-column: 131 | |
233 | * comment-column: 0 | |
234 | * End: | |
235 | */ | |
236 | ||
47660bef | 237 | /* end of sparc.h */ |