[deliverable/binutils-gdb.git] / include / opcode / sparc.h

/* Definitions for opcode table for the sparc.
   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
   2003, 2005, 2010, 2011 Free Software Foundation, Inc.

   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   the GNU Binutils.

   GAS/GDB is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   GAS/GDB is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS or GDB; see the file COPYING3.  If not, write to
   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
   Boston, MA 02110-1301, USA.  */

#include "ansidecl.h"

/* The SPARC opcode table (and other related data) is defined in
   the opcodes library in sparc-opc.c.  If you change anything here, make
   sure you fix up that file, and vice versa.  */

 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
    instruction's name rather than the args.  This would make gas faster, pinsn
    slower, but would mess up some macros a bit.  xoxorich. */

/* List of instruction sets variations.
   These values are such that each element is either a superset of a
   preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
   returns non-zero.
   The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
   Don't change this without updating sparc-opc.c.  */

enum sparc_opcode_arch_val
{
  SPARC_OPCODE_ARCH_V6 = 0,
  SPARC_OPCODE_ARCH_V7,
  SPARC_OPCODE_ARCH_V8,
  SPARC_OPCODE_ARCH_SPARCLET,
  SPARC_OPCODE_ARCH_SPARCLITE,
  /* V9 variants must appear last.  */
  SPARC_OPCODE_ARCH_V9,
  SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions.  */
  SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions.  */
  SPARC_OPCODE_ARCH_BAD  /* Error return from sparc_opcode_lookup_arch.  */
};

/* The highest architecture in the table.  */
#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)

/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
   insn encoding/decoding.  */
#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))

/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9.  */
#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)

/* Table of cpu variants.  */

typedef struct sparc_opcode_arch
{
  const char *name;
  /* Mask of sparc_opcode_arch_val's supported.
     EG: For v7 this would be
     (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
     These are short's because sparc_opcode.architecture is.  */
  short supported;
} sparc_opcode_arch;

extern const struct sparc_opcode_arch sparc_opcode_archs[];

/* Given architecture name, look up it's sparc_opcode_arch_val value.  */
extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *);

/* Return the bitmask of supported architectures for ARCH.  */
#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)

/* Non-zero if ARCH1 conflicts with ARCH2.
   IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa.  */
#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
 (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
   != SPARC_OPCODE_SUPPORTED (ARCH1)) \
  && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
     != SPARC_OPCODE_SUPPORTED (ARCH2)))

/* Structure of an opcode table entry.  */

typedef struct sparc_opcode
{
  const char *name;
  unsigned long match;	/* Bits that must be set.  */
  unsigned long lose;	/* Bits that must not be set.  */
  const char *args;
  /* This was called "delayed" in versions before the flags.  */
  unsigned int flags;
  short architecture;	/* Bitmask of sparc_opcode_arch_val's.  */
} sparc_opcode;

/* FIXME: Add F_ANACHRONISTIC flag for v9.  */
#define	F_DELAYED	0x00000001 /* Delayed branch.  */
#define	F_ALIAS		0x00000002 /* Alias for a "real" instruction.  */
#define	F_UNBR		0x00000004 /* Unconditional branch.  */
#define	F_CONDBR	0x00000008 /* Conditional branch.  */
#define	F_JSR		0x00000010 /* Subroutine call.  */
#define F_FLOAT		0x00000020 /* Floating point instruction (not a branch).  */
#define F_FBR		0x00000040 /* Floating point branch.  */
#define F_MUL32		0x00000100 /* umul/umulcc/smul/smulcc insns */
#define F_DIV32		0x00000200 /* udiv/udivcc/sdiv/sdivcc insns */
#define F_FSMULD	0x00000400 /* 'fsmuld' insn */
#define F_V8PLUS	0x00000800 /* v9 insns available to 32bit */
#define F_POPC		0x00001000 /* 'popc' insn */
#define F_VIS		0x00002000 /* VIS insns */
#define F_VIS2		0x00004000 /* VIS2 insns */
#define F_ASI_BLK_INIT	0x00008000 /* block init ASIs */
#define F_FMAF		0x00010000 /* fused multiply-add */
#define F_VIS3		0x00020000 /* VIS3 insns */
#define F_HPC		0x00040000 /* HPC insns */
#define F_RANDOM	0x00080000 /* 'random' insn */
#define F_TRANS		0x00100000 /* transaction insns */
#define F_FJFMAU	0x00200000 /* unfused multiply-add */
#define F_IMA		0x00400000 /* integer multiply-add */
#define F_ASI_CACHE_SPARING \
			0x00800000 /* cache sparing ASIs */

#define F_HWCAP_MASK	0x00ffff00

/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
   macro), which is 64 bits. It is handled as a special case.

   The match component is a mask saying which bits must match a particular
   opcode in order for an instruction to be an instance of that opcode.

   The args component is a string containing one character for each operand of the
   instruction.

   Kinds of operands:
	#	Number used by optimizer.	It is ignored.
	1	rs1 register.
	2	rs2 register.
	d	rd register.
	e	frs1 floating point register.
	v	frs1 floating point register (double/even).
	V	frs1 floating point register (quad/multiple of 4).
	f	frs2 floating point register.
	B	frs2 floating point register (double/even).
	R	frs2 floating point register (quad/multiple of 4).
	4	frs3 floating point register.
	5	frs3 floating point register (doube/even).
	g	frsd floating point register.
	H	frsd floating point register (double/even).
	J	frsd floating point register (quad/multiple of 4).
	b	crs1 coprocessor register
	c	crs2 coprocessor register
	D	crsd coprocessor register
	m	alternate space register (asr) in rd
	M	alternate space register (asr) in rs1
	h	22 high bits.
	X	5 bit unsigned immediate
	Y	6 bit unsigned immediate
	3	SIAM mode (3 bits). (v9b)
	K	MEMBAR mask (7 bits). (v9)
	j	10 bit Immediate. (v9)
	I	11 bit Immediate. (v9)
	i	13 bit Immediate.
	n	22 bit immediate.
	k	2+14 bit PC relative immediate. (v9)
	G	19 bit PC relative immediate. (v9)
	l	22 bit PC relative immediate.
	L	30 bit PC relative immediate.
	a	Annul.	The annul bit is set.
	A	Alternate address space. Stored as 8 bits.
	C	Coprocessor state register.
	F	floating point state register.
	p	Processor state register.
	N	Branch predict clear ",pn" (v9)
	T	Branch predict set ",pt" (v9)
	z	%icc. (v9)
	Z	%xcc. (v9)
	q	Floating point queue.
	r	Single register that is both rs1 and rd.
	O	Single register that is both rs2 and rd.
	Q	Coprocessor queue.
	S	Special case.
	t	Trap base register.
	w	Window invalid mask register.
	y	Y register.
	u	sparclet coprocessor registers in rd position
	U	sparclet coprocessor registers in rs1 position
	E	%ccr. (v9)
	s	%fprs. (v9)
	P	%pc.  (v9)
	W	%tick.	(v9)
	o	%asi. (v9)
	6	%fcc0. (v9)
	7	%fcc1. (v9)
	8	%fcc2. (v9)
	9	%fcc3. (v9)
	!	Privileged Register in rd (v9)
	?	Privileged Register in rs1 (v9)
	*	Prefetch function constant. (v9)
	x	OPF field (v9 impdep).
	0	32/64 bit immediate for set or setx (v9) insns
	_	Ancillary state register in rd (v9a)
	/	Ancillary state register in rs1 (v9a)
	(	entire floating point state register (%efsr).  */

#define OP2(x)		(((x) & 0x7) << 22)  /* Op2 field of format2 insns.  */
#define OP3(x)		(((x) & 0x3f) << 19) /* Op3 field of format3 insns.  */
#define OP(x)		((unsigned) ((x) & 0x3) << 30) /* Op field of all insns.  */
#define OPF(x)		(((x) & 0x1ff) << 5) /* Opf field of float insns.  */
#define OPF_LOW5(x)	OPF ((x) & 0x1f)     /* V9.  */
#define OPF_LOW4(x)	OPF ((x) & 0xf)      /* V9.  */
#define F3F(x, y, z)	(OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns.  */
#define F3I(x)		(((x) & 0x1) << 13)  /* Immediate field of format 3 insns.  */
#define F2(x, y)	(OP (x) | OP2(y))    /* Format 2 insns.  */
#define F3(x, y, z)	(OP (x) | OP3(y) | F3I(z)) /* Format3 insns.  */
#define F1(x)		(OP (x))
#define DISP30(x)	((x) & 0x3fffffff)
#define ASI(x)		(((x) & 0xff) << 5)  /* Asi field of format3 insns.  */
#define RS2(x)		((x) & 0x1f)         /* Rs2 field.  */
#define SIMM13(x)	((x) & 0x1fff)       /* Simm13 field.  */
#define RD(x)		(((x) & 0x1f) << 25) /* Destination register field.  */
#define RS1(x)		(((x) & 0x1f) << 14) /* Rs1 field.  */
#define RS3(x)		(((x) & 0x1f) << 9)  /* Rs3 field.  */
#define ASI_RS2(x)	(SIMM13 (x))
#define MEMBAR(x)	((x) & 0x7f)
#define SLCPOP(x)	(((x) & 0x7f) << 6)  /* Sparclet cpop.  */

#define ANNUL	(1 << 29)
#define BPRED	(1 << 19)	/* V9.  */
#define	IMMED	F3I (1)
#define RD_G0	RD (~0)
#define	RS1_G0	RS1 (~0)
#define	RS2_G0	RS2 (~0)

extern const struct sparc_opcode sparc_opcodes[];
extern const int sparc_num_opcodes;

extern int sparc_encode_asi (const char *);
extern const char *sparc_decode_asi (int);
extern int sparc_encode_membar (const char *);
extern const char *sparc_decode_membar (int);
extern int sparc_encode_prefetch (const char *);
extern const char *sparc_decode_prefetch (int);
extern int sparc_encode_sparclet_cpreg (const char *);
extern const char *sparc_decode_sparclet_cpreg (int);

/* Local Variables:
   fill-column: 131
   comment-column: 0
   End: */
Commit	Line	Data
252b5132	1	/* Definitions for opcode table for the sparc.
8cf3f354	2	Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
9e8c70f9	3	2003, 2005, 2010, 2011 Free Software Foundation, Inc.
252b5132	4
47b0e7ad NC	5	This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
47b0e7ad NC	6	the GNU Binutils.
252b5132	7
47b0e7ad NC	8	GAS/GDB is free software; you can redistribute it and/or modify
47b0e7ad NC	9	it under the terms of the GNU General Public License as published by
e4e42b45	10	the Free Software Foundation; either version 3, or (at your option)
47b0e7ad	11	any later version.
252b5132	12
47b0e7ad NC	13	GAS/GDB is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
252b5132	17
47b0e7ad	18	You should have received a copy of the GNU General Public License
e4e42b45	19	along with GAS or GDB; see the file COPYING3. If not, write to
47b0e7ad NC	20	the Free Software Foundation, 51 Franklin Street - Fifth Floor,
47b0e7ad NC	21	Boston, MA 02110-1301, USA. */
252b5132	22
b3f7d5fd	23	#include "ansidecl.h"
252b5132 RH	24
	25	/* The SPARC opcode table (and other related data) is defined in
	26	the opcodes library in sparc-opc.c. If you change anything here, make
	27	sure you fix up that file, and vice versa. */
	28
	29	/* FIXME-someday: perhaps the ,a's and such should be embedded in the
	30	instruction's name rather than the args. This would make gas faster, pinsn
	31	slower, but would mess up some macros a bit. xoxorich. */
	32
	33	/* List of instruction sets variations.
	34	These values are such that each element is either a superset of a
	35	preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
	36	returns non-zero.
	37	The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
	38	Don't change this without updating sparc-opc.c. */
	39
47b0e7ad NC	40	enum sparc_opcode_arch_val
47b0e7ad NC	41	{
252b5132 RH	42	SPARC_OPCODE_ARCH_V6 = 0,
	43	SPARC_OPCODE_ARCH_V7,
	44	SPARC_OPCODE_ARCH_V8,
	45	SPARC_OPCODE_ARCH_SPARCLET,
	46	SPARC_OPCODE_ARCH_SPARCLITE,
47b0e7ad	47	/* V9 variants must appear last. */
252b5132	48	SPARC_OPCODE_ARCH_V9,
47b0e7ad NC	49	SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
	50	SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
	51	SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
252b5132 RH	52	};
	53
	54	/* The highest architecture in the table. */
	55	#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
	56
	57	/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
	58	insn encoding/decoding. */
	59	#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
	60
	61	/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
	62	#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
	63
	64	/* Table of cpu variants. */
	65
47b0e7ad NC	66	typedef struct sparc_opcode_arch
47b0e7ad NC	67	{
252b5132 RH	68	const char *name;
	69	/* Mask of sparc_opcode_arch_val's supported.
	70	EG: For v7 this would be
	71	(SPARC_OPCODE_ARCH_MASK (..._V6) \| SPARC_OPCODE_ARCH_MASK (..._V7)).
	72	These are short's because sparc_opcode.architecture is. */
	73	short supported;
47b0e7ad	74	} sparc_opcode_arch;
252b5132 RH	75
	76	extern const struct sparc_opcode_arch sparc_opcode_archs[];
	77
	78	/* Given architecture name, look up it's sparc_opcode_arch_val value. */
8cf3f354	79	extern enum sparc_opcode_arch_val sparc_opcode_lookup_arch (const char *);
252b5132 RH	80
	81	/* Return the bitmask of supported architectures for ARCH. */
	82	#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
	83
	84	/* Non-zero if ARCH1 conflicts with ARCH2.
	85	IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
	86	#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
47b0e7ad NC	87	(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
	88	!= SPARC_OPCODE_SUPPORTED (ARCH1)) \
	89	&& ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
252b5132 RH	90	!= SPARC_OPCODE_SUPPORTED (ARCH2)))
	91
	92	/* Structure of an opcode table entry. */
	93
47b0e7ad NC	94	typedef struct sparc_opcode
47b0e7ad NC	95	{
252b5132	96	const char *name;
47b0e7ad NC	97	unsigned long match; /* Bits that must be set. */
47b0e7ad NC	98	unsigned long lose; /* Bits that must not be set. */
252b5132	99	const char *args;
47b0e7ad	100	/* This was called "delayed" in versions before the flags. */
9e8c70f9	101	unsigned int flags;
252b5132	102	short architecture; /* Bitmask of sparc_opcode_arch_val's. */
47b0e7ad NC	103	} sparc_opcode;
47b0e7ad NC	104
252b5132	105	/* FIXME: Add F_ANACHRONISTIC flag for v9. */
9e8c70f9 DM	106	#define F_DELAYED 0x00000001 /* Delayed branch. */
	107	#define F_ALIAS 0x00000002 /* Alias for a "real" instruction. */
	108	#define F_UNBR 0x00000004 /* Unconditional branch. */
	109	#define F_CONDBR 0x00000008 /* Conditional branch. */
	110	#define F_JSR 0x00000010 /* Subroutine call. */
	111	#define F_FLOAT 0x00000020 /* Floating point instruction (not a branch). */
	112	#define F_FBR 0x00000040 /* Floating point branch. */
	113	#define F_MUL32 0x00000100 /* umul/umulcc/smul/smulcc insns */
	114	#define F_DIV32 0x00000200 /* udiv/udivcc/sdiv/sdivcc insns */
	115	#define F_FSMULD 0x00000400 /* 'fsmuld' insn */
	116	#define F_V8PLUS 0x00000800 /* v9 insns available to 32bit */
	117	#define F_POPC 0x00001000 /* 'popc' insn */
	118	#define F_VIS 0x00002000 /* VIS insns */
	119	#define F_VIS2 0x00004000 /* VIS2 insns */
	120	#define F_ASI_BLK_INIT 0x00008000 /* block init ASIs */
	121	#define F_FMAF 0x00010000 /* fused multiply-add */
	122	#define F_VIS3 0x00020000 /* VIS3 insns */
	123	#define F_HPC 0x00040000 /* HPC insns */
	124	#define F_RANDOM 0x00080000 /* 'random' insn */
	125	#define F_TRANS 0x00100000 /* transaction insns */
	126	#define F_FJFMAU 0x00200000 /* unfused multiply-add */
	127	#define F_IMA 0x00400000 /* integer multiply-add */
	128	#define F_ASI_CACHE_SPARING \
	129	0x00800000 /* cache sparing ASIs */
	130
	131	#define F_HWCAP_MASK 0x00ffff00
252b5132	132
47b0e7ad NC	133	/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
47b0e7ad NC	134	macro), which is 64 bits. It is handled as a special case.
252b5132	135
47b0e7ad NC	136	The match component is a mask saying which bits must match a particular
47b0e7ad NC	137	opcode in order for an instruction to be an instance of that opcode.
252b5132	138
47b0e7ad NC	139	The args component is a string containing one character for each operand of the
47b0e7ad NC	140	instruction.
252b5132	141
47b0e7ad	142	Kinds of operands:
252b5132 RH	143	# Number used by optimizer. It is ignored.
	144	1 rs1 register.
	145	2 rs2 register.
	146	d rd register.
	147	e frs1 floating point register.
	148	v frs1 floating point register (double/even).
	149	V frs1 floating point register (quad/multiple of 4).
	150	f frs2 floating point register.
	151	B frs2 floating point register (double/even).
	152	R frs2 floating point register (quad/multiple of 4).
ea783ef3 DM	153	4 frs3 floating point register.
ea783ef3 DM	154	5 frs3 floating point register (doube/even).
252b5132 RH	155	g frsd floating point register.
	156	H frsd floating point register (double/even).
	157	J frsd floating point register (quad/multiple of 4).
	158	b crs1 coprocessor register
	159	c crs2 coprocessor register
	160	D crsd coprocessor register
	161	m alternate space register (asr) in rd
	162	M alternate space register (asr) in rs1
	163	h 22 high bits.
	164	X 5 bit unsigned immediate
	165	Y 6 bit unsigned immediate
19f7b010	166	3 SIAM mode (3 bits). (v9b)
252b5132 RH	167	K MEMBAR mask (7 bits). (v9)
	168	j 10 bit Immediate. (v9)
	169	I 11 bit Immediate. (v9)
	170	i 13 bit Immediate.
	171	n 22 bit immediate.
	172	k 2+14 bit PC relative immediate. (v9)
	173	G 19 bit PC relative immediate. (v9)
	174	l 22 bit PC relative immediate.
	175	L 30 bit PC relative immediate.
	176	a Annul. The annul bit is set.
	177	A Alternate address space. Stored as 8 bits.
	178	C Coprocessor state register.
	179	F floating point state register.
	180	p Processor state register.
	181	N Branch predict clear ",pn" (v9)
	182	T Branch predict set ",pt" (v9)
	183	z %icc. (v9)
	184	Z %xcc. (v9)
	185	q Floating point queue.
	186	r Single register that is both rs1 and rd.
	187	O Single register that is both rs2 and rd.
	188	Q Coprocessor queue.
	189	S Special case.
	190	t Trap base register.
	191	w Window invalid mask register.
	192	y Y register.
	193	u sparclet coprocessor registers in rd position
	194	U sparclet coprocessor registers in rs1 position
	195	E %ccr. (v9)
	196	s %fprs. (v9)
	197	P %pc. (v9)
	198	W %tick. (v9)
	199	o %asi. (v9)
	200	6 %fcc0. (v9)
	201	7 %fcc1. (v9)
	202	8 %fcc2. (v9)
	203	9 %fcc3. (v9)
	204	! Privileged Register in rd (v9)
	205	? Privileged Register in rs1 (v9)
	206	* Prefetch function constant. (v9)
	207	x OPF field (v9 impdep).
	208	0 32/64 bit immediate for set or setx (v9) insns
	209	_ Ancillary state register in rd (v9a)
	210	/ Ancillary state register in rs1 (v9a)
ea783ef3	211	( entire floating point state register (%efsr). */
47b0e7ad NC	212
	213	#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
	214	#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
	215	#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
	216	#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
	217	#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
ea783ef3	218	#define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */
47b0e7ad NC	219	#define F3F(x, y, z) (OP (x) \| OP3 (y) \| OPF (z)) /* Format3 float insns. */
	220	#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
	221	#define F2(x, y) (OP (x) \| OP2(y)) /* Format 2 insns. */
	222	#define F3(x, y, z) (OP (x) \| OP3(y) \| F3I(z)) /* Format3 insns. */
	223	#define F1(x) (OP (x))
	224	#define DISP30(x) ((x) & 0x3fffffff)
	225	#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
	226	#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
	227	#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
	228	#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
	229	#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
ea783ef3	230	#define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */
47b0e7ad NC	231	#define ASI_RS2(x) (SIMM13 (x))
	232	#define MEMBAR(x) ((x) & 0x7f)
	233	#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */
	234
	235	#define ANNUL (1 << 29)
	236	#define BPRED (1 << 19) /* V9. */
	237	#define IMMED F3I (1)
	238	#define RD_G0 RD (~0)
	239	#define RS1_G0 RS1 (~0)
	240	#define RS2_G0 RS2 (~0)
252b5132 RH	241
	242	extern const struct sparc_opcode sparc_opcodes[];
	243	extern const int sparc_num_opcodes;
	244
8cf3f354 AM	245	extern int sparc_encode_asi (const char *);
	246	extern const char *sparc_decode_asi (int);
	247	extern int sparc_encode_membar (const char *);
	248	extern const char *sparc_decode_membar (int);
	249	extern int sparc_encode_prefetch (const char *);
	250	extern const char *sparc_decode_prefetch (int);
	251	extern int sparc_encode_sparclet_cpreg (const char *);
	252	extern const char *sparc_decode_sparclet_cpreg (int);
252b5132	253
47b0e7ad NC	254	/* Local Variables:
	255	fill-column: 131
	256	comment-column: 0
	257	End: */
252b5132	258