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7b22a53c | 1 | /* Definitions for opcode table for the sparc. |
22472179 | 2 | Copyright (C) 1989, 1991, 1992, 1995, 1996 Free Software Foundation, Inc. |
47660bef KR |
3 | |
4 | This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and | |
5 | the GNU Binutils. | |
0227e918 | 6 | |
0227e918 SC |
7 | GAS/GDB is free software; you can redistribute it and/or modify |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GAS/GDB is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS or GDB; see the file COPYING. If not, write to | |
44292d2e DE |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, |
20 | Boston, MA 02111-1307, USA. */ | |
0227e918 | 21 | |
7b22a53c | 22 | /* The SPARC opcode table (and other related data) is defined in |
f2c42ba4 | 23 | the opcodes library in sparc-opc.c. If you change anything here, make |
7b22a53c KR |
24 | sure you fix up that file, and vice versa. */ |
25 | ||
0227e918 SC |
26 | /* FIXME-someday: perhaps the ,a's and such should be embedded in the |
27 | instruction's name rather than the args. This would make gas faster, pinsn | |
28 | slower, but would mess up some macros a bit. xoxorich. */ | |
29 | ||
7484896b DE |
30 | /* List of instruction sets variations. |
31 | These values are such that each element is either a superset of a | |
803108ab | 32 | preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P |
7484896b DE |
33 | returns non-zero. |
34 | The values are indices into `sparc_opcode_archs' defined in sparc-opc.c. | |
35 | Don't change this without updating sparc-opc.c. */ | |
803108ab JL |
36 | /* ??? May wish to allow for anonymous architectures for variants that have |
37 | a common but unnamed subset. */ | |
7484896b DE |
38 | |
39 | enum sparc_opcode_arch_val { | |
40 | SPARC_OPCODE_ARCH_V6 = 0, | |
41 | SPARC_OPCODE_ARCH_V7, | |
42 | SPARC_OPCODE_ARCH_V8, | |
43 | SPARC_OPCODE_ARCH_SPARCLITE, | |
44 | /* v9 variants must appear last */ | |
45 | SPARC_OPCODE_ARCH_V9, | |
46 | SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */ | |
47 | SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */ | |
48 | }; | |
7b22a53c | 49 | |
7484896b DE |
50 | /* The highest architecture in the table. */ |
51 | #define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1) | |
52 | ||
53 | /* Table of cpu variants. */ | |
54 | ||
55 | struct sparc_opcode_arch { | |
56 | const char *name; | |
57 | int conflicts; | |
0227e918 SC |
58 | }; |
59 | ||
7484896b DE |
60 | extern const struct sparc_opcode_arch sparc_opcode_archs[]; |
61 | ||
803108ab | 62 | extern const enum sparc_opcode_arch_val sparc_opcode_lookup_arch (); |
0227e918 | 63 | |
7484896b | 64 | /* Non-zero if ARCH1 conflicts with ARCH2. */ |
47660bef | 65 | |
7484896b DE |
66 | #define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \ |
67 | ((1 << (ARCH1)) & sparc_opcode_archs[ARCH2].conflicts) | |
68 | ||
69 | /* Structure of an opcode table entry. */ | |
47660bef | 70 | |
0227e918 SC |
71 | struct sparc_opcode { |
72 | const char *name; | |
73 | unsigned long match; /* Bits that must be set. */ | |
74 | unsigned long lose; /* Bits that must not be set. */ | |
75 | const char *args; | |
76 | /* This was called "delayed" in versions before the flags. */ | |
77 | char flags; | |
7484896b | 78 | enum sparc_opcode_arch_val architecture; |
0227e918 SC |
79 | }; |
80 | ||
81 | #define F_DELAYED 1 /* Delayed branch */ | |
82 | #define F_ALIAS 2 /* Alias for a "real" instruction */ | |
f2c42ba4 KR |
83 | #define F_UNBR 4 /* Unconditional branch */ |
84 | #define F_CONDBR 8 /* Conditional branch */ | |
85 | #define F_JSR 16 /* Subroutine call */ | |
97eab8a1 DE |
86 | /* ??? One can argue this shouldn't be here and the architecture |
87 | field should be used instead. */ | |
88 | #define F_NOTV9 32 /* Doesn't exist in v9 */ | |
f2c42ba4 | 89 | /* FIXME: Add F_ANACHRONISTIC flag for v9. */ |
0227e918 SC |
90 | |
91 | /* | |
92 | ||
93 | All sparc opcodes are 32 bits, except for the `set' instruction (really a | |
94 | macro), which is 64 bits. It is handled as a special case. | |
95 | ||
96 | The match component is a mask saying which bits must match a particular | |
97 | opcode in order for an instruction to be an instance of that opcode. | |
98 | ||
99 | The args component is a string containing one character for each operand of the | |
100 | instruction. | |
101 | ||
102 | Kinds of operands: | |
103 | # Number used by optimizer. It is ignored. | |
104 | 1 rs1 register. | |
105 | 2 rs2 register. | |
106 | d rd register. | |
107 | e frs1 floating point register. | |
108 | v frs1 floating point register (double/even). | |
109 | V frs1 floating point register (quad/multiple of 4). | |
110 | f frs2 floating point register. | |
111 | B frs2 floating point register (double/even). | |
112 | R frs2 floating point register (quad/multiple of 4). | |
0227e918 SC |
113 | g frsd floating point register. |
114 | H frsd floating point register (double/even). | |
115 | J frsd floating point register (quad/multiple of 4). | |
116 | b crs1 coprocessor register | |
117 | c crs2 coprocessor register | |
118 | D crsd coprocessor register | |
119 | m alternate space register (asr) in rd | |
120 | M alternate space register (asr) in rs1 | |
121 | h 22 high bits. | |
f2c42ba4 KR |
122 | K MEMBAR mask (7 bits). (v9) |
123 | j 10 bit Immediate. (v9) | |
0227e918 SC |
124 | I 11 bit Immediate. (v9) |
125 | i 13 bit Immediate. | |
cc35cb05 | 126 | n 22 bit immediate. |
0227e918 SC |
127 | k 2+14 bit PC relative immediate. (v9) |
128 | G 19 bit PC relative immediate. (v9) | |
129 | l 22 bit PC relative immediate. | |
130 | L 30 bit PC relative immediate. | |
131 | a Annul. The annul bit is set. | |
132 | A Alternate address space. Stored as 8 bits. | |
133 | C Coprocessor state register. | |
134 | F floating point state register. | |
135 | p Processor state register. | |
136 | N Branch predict clear ",pn" (v9) | |
137 | T Branch predict set ",pt" (v9) | |
f2c42ba4 KR |
138 | z %icc. (v9) |
139 | Z %xcc. (v9) | |
0227e918 SC |
140 | q Floating point queue. |
141 | r Single register that is both rs1 and rsd. | |
142 | Q Coprocessor queue. | |
143 | S Special case. | |
144 | t Trap base register. | |
145 | w Window invalid mask register. | |
146 | y Y register. | |
f2c42ba4 KR |
147 | E %ccr. (v9) |
148 | s %fprs. (v9) | |
0227e918 | 149 | P %pc. (v9) |
0227e918 | 150 | W %tick. (v9) |
47660bef | 151 | o %asi. (v9) |
f2c42ba4 KR |
152 | 6 %fcc0. (v9) |
153 | 7 %fcc1. (v9) | |
154 | 8 %fcc2. (v9) | |
155 | 9 %fcc3. (v9) | |
47660bef KR |
156 | ! Privileged Register in rd (v9) |
157 | ? Privileged Register in rs1 (v9) | |
f2c42ba4 KR |
158 | * Prefetch function constant. (v9) |
159 | x OPF field (v9 impdep). | |
0227e918 SC |
160 | |
161 | The following chars are unused: (note: ,[] are used as punctuation) | |
97eab8a1 | 162 | [uOUXY3450] |
0227e918 SC |
163 | |
164 | */ | |
165 | ||
0227e918 SC |
166 | #define OP2(x) (((x)&0x7) << 22) /* op2 field of format2 insns */ |
167 | #define OP3(x) (((x)&0x3f) << 19) /* op3 field of format3 insns */ | |
47660bef | 168 | #define OP(x) ((unsigned)((x)&0x3) << 30) /* op field of all insns */ |
0227e918 | 169 | #define OPF(x) (((x)&0x1ff) << 5) /* opf field of float insns */ |
f2c42ba4 | 170 | #define OPF_LOW5(x) OPF((x)&0x1f) /* v9 */ |
0227e918 SC |
171 | #define F3F(x, y, z) (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */ |
172 | #define F3I(x) (((x)&0x1) << 13) /* immediate field of format 3 insns */ | |
173 | #define F2(x, y) (OP(x) | OP2(y)) /* format 2 insns */ | |
174 | #define F3(x, y, z) (OP(x) | OP3(y) | F3I(z)) /* format3 insns */ | |
175 | #define F1(x) (OP(x)) | |
176 | #define DISP30(x) ((x)&0x3fffffff) | |
177 | #define ASI(x) (((x)&0xff) << 5) /* asi field of format3 insns */ | |
178 | #define RS2(x) ((x)&0x1f) /* rs2 field */ | |
179 | #define SIMM13(x) ((x)&0x1fff) /* simm13 field */ | |
180 | #define RD(x) (((x)&0x1f) << 25) /* destination register field */ | |
181 | #define RS1(x) (((x)&0x1f) << 14) /* rs1 field */ | |
182 | #define ASI_RS2(x) (SIMM13(x)) | |
22472179 | 183 | #define MEMBAR(x) ((x)&0x7f) |
0227e918 SC |
184 | |
185 | #define ANNUL (1<<29) | |
f59db855 | 186 | #define BPRED (1<<19) /* v9 */ |
0227e918 SC |
187 | #define IMMED F3I(1) |
188 | #define RD_G0 RD(~0) | |
189 | #define RS1_G0 RS1(~0) | |
190 | #define RS2_G0 RS2(~0) | |
191 | ||
7b22a53c | 192 | extern struct sparc_opcode sparc_opcodes[]; |
7484896b | 193 | extern const int sparc_num_opcodes; |
0227e918 | 194 | |
44292d2e DE |
195 | int sparc_encode_asi (); |
196 | char *sparc_decode_asi (); | |
22472179 DE |
197 | int sparc_encode_membar (); |
198 | char *sparc_decode_membar (); | |
199 | int sparc_encode_prefetch (); | |
200 | char *sparc_decode_prefetch (); | |
44292d2e | 201 | |
0227e918 SC |
202 | /* |
203 | * Local Variables: | |
204 | * fill-column: 131 | |
205 | * comment-column: 0 | |
206 | * End: | |
207 | */ | |
208 | ||
47660bef | 209 | /* end of sparc.h */ |