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40b36596 | 1 | /* TI C6X opcode information. |
2571583a | 2 | Copyright (C) 2010-2017 Free Software Foundation, Inc. |
40b36596 JM |
3 | |
4 | This program is free software; you can redistribute it and/or modify | |
5 | it under the terms of the GNU General Public License as published by | |
6 | the Free Software Foundation; either version 3 of the License, or | |
7 | (at your option) any later version. | |
8 | ||
9 | This program is distributed in the hope that it will be useful, | |
10 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | GNU General Public License for more details. | |
13 | ||
14 | You should have received a copy of the GNU General Public License | |
15 | along with this program; if not, write to the Free Software | |
16 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, | |
17 | MA 02110-1301, USA. */ | |
18 | ||
19 | #ifndef OPCODE_TIC6X_H | |
20 | #define OPCODE_TIC6X_H | |
21 | ||
22 | #include "bfd.h" | |
23 | #include "symcat.h" | |
24 | ||
1fe0971e TS |
25 | #ifdef __cplusplus |
26 | extern "C" { | |
27 | #endif | |
28 | ||
40b36596 JM |
29 | /* A field in an instruction format. The names are based on those |
30 | used in the architecture manuals. */ | |
31 | typedef enum | |
32 | { | |
33 | tic6x_field_baseR, | |
51dcdd4d | 34 | tic6x_field_cc, |
40b36596 JM |
35 | tic6x_field_creg, |
36 | tic6x_field_cst, | |
37 | tic6x_field_csta, | |
38 | tic6x_field_cstb, | |
39 | tic6x_field_dst, | |
51dcdd4d NC |
40 | tic6x_field_dstms, |
41 | tic6x_field_dw, | |
40b36596 JM |
42 | tic6x_field_fstgfcyc, |
43 | tic6x_field_h, | |
51dcdd4d | 44 | tic6x_field_ii, |
40b36596 JM |
45 | tic6x_field_mask, |
46 | tic6x_field_mode, | |
51dcdd4d NC |
47 | tic6x_field_n, |
48 | tic6x_field_na, | |
40b36596 JM |
49 | tic6x_field_offsetR, |
50 | tic6x_field_op, | |
51 | tic6x_field_p, | |
51dcdd4d | 52 | tic6x_field_ptr, |
40b36596 JM |
53 | tic6x_field_r, |
54 | tic6x_field_s, | |
55 | tic6x_field_sc, | |
56 | tic6x_field_src, | |
57 | tic6x_field_src1, | |
58 | tic6x_field_src2, | |
59 | tic6x_field_srcdst, | |
51dcdd4d NC |
60 | tic6x_field_srcms, |
61 | tic6x_field_sn, | |
62 | tic6x_field_sz, | |
63 | tic6x_field_unit, | |
64 | tic6x_field_t, | |
40b36596 JM |
65 | tic6x_field_x, |
66 | tic6x_field_y, | |
67 | tic6x_field_z | |
68 | } tic6x_insn_field_id; | |
69 | ||
70 | typedef struct | |
71 | { | |
40b36596 | 72 | /* The least-significant bit position in the field. */ |
51dcdd4d | 73 | unsigned short low_pos; |
40b36596 JM |
74 | |
75 | /* The number of bits in the field. */ | |
76 | unsigned short width; | |
51dcdd4d NC |
77 | /* The position of the bitfield in the field. */ |
78 | unsigned short pos; | |
79 | } tic6x_bitfield; | |
80 | ||
81 | /* Maximum number of subfields in composite field. */ | |
82 | #define TIC6X_MAX_BITFIELDS 4 | |
83 | ||
84 | typedef struct | |
85 | { | |
86 | /* The name used to reference the field. */ | |
87 | tic6x_insn_field_id field_id; | |
88 | unsigned int num_bitfields; | |
89 | tic6x_bitfield bitfields[TIC6X_MAX_BITFIELDS]; | |
40b36596 JM |
90 | } tic6x_insn_field; |
91 | ||
92 | /* Maximum number of variable fields in an instruction format. */ | |
93 | #define TIC6X_MAX_INSN_FIELDS 11 | |
94 | ||
95 | /* A particular instruction format. */ | |
96 | typedef struct | |
97 | { | |
98 | /* How many bits in the instruction. */ | |
99 | unsigned int num_bits; | |
100 | ||
101 | /* Constant bits in the instruction. */ | |
102 | unsigned int cst_bits; | |
103 | ||
104 | /* Mask matching those bits. */ | |
105 | unsigned int mask; | |
106 | ||
107 | /* The number of instruction fields. */ | |
108 | unsigned int num_fields; | |
109 | ||
110 | /* Descriptions of instruction fields. */ | |
111 | tic6x_insn_field fields[TIC6X_MAX_INSN_FIELDS]; | |
112 | } tic6x_insn_format; | |
113 | ||
114 | /* An index into the table of instruction formats. */ | |
115 | typedef enum | |
116 | { | |
117 | #define FMT(name, num_bits, cst_bits, mask, fields) \ | |
118 | CONCAT2(tic6x_insn_format_, name), | |
119 | #include "tic6x-insn-formats.h" | |
120 | #undef FMT | |
121 | tic6x_insn_format_max | |
122 | } tic6x_insn_format_id; | |
123 | ||
124 | /* The table itself. */ | |
125 | extern const tic6x_insn_format tic6x_insn_format_table[tic6x_insn_format_max]; | |
126 | ||
127 | /* If instruction format FMT has a field FIELD, return a pointer to | |
128 | the description of that field; otherwise return NULL. */ | |
129 | ||
130 | const tic6x_insn_field *tic6x_field_from_fmt (const tic6x_insn_format *fmt, | |
131 | tic6x_insn_field_id field); | |
132 | ||
133 | /* Description of a field (in an instruction format) whose value is | |
134 | fixed, or constrained to be in a particular range, in a particular | |
135 | opcode. */ | |
136 | typedef struct | |
137 | { | |
138 | /* The name of the field. */ | |
139 | tic6x_insn_field_id field_id; | |
140 | ||
141 | /* The least value of the field in this instruction. */ | |
142 | unsigned int min_val; | |
143 | ||
144 | /* The greatest value of the field in this instruction. */ | |
145 | unsigned int max_val; | |
146 | } tic6x_fixed_field; | |
147 | ||
51dcdd4d NC |
148 | /* Pseudo opcode fields position for compact instructions |
149 | If 16 bits instruction detected, the opcode is enriched | |
150 | [DSZ/3][BR][SAT][opcode] */ | |
151 | #define TIC6X_COMPACT_SAT_POS 16 | |
152 | #define TIC6X_COMPACT_BR_POS 17 | |
153 | #define TIC6X_COMPACT_DSZ_POS 18 | |
154 | ||
40b36596 JM |
155 | /* Bit-masks for defining instructions present on some subset of |
156 | processors; each indicates an instruction present on that processor | |
157 | and those that are supersets of it. The options passed to the | |
158 | assembler determine a bit-mask ANDed with the bit-mask indicating | |
159 | when the instruction was added to determine whether the instruction | |
160 | is enabled. */ | |
161 | #define TIC6X_INSN_C62X 0x0001 | |
162 | #define TIC6X_INSN_C64X 0x0002 | |
163 | #define TIC6X_INSN_C64XP 0x0004 | |
164 | #define TIC6X_INSN_C67X 0x0008 | |
165 | #define TIC6X_INSN_C67XP 0x0010 | |
166 | #define TIC6X_INSN_C674X 0x0020 | |
40b36596 JM |
167 | |
168 | /* Flags with further information about an opcode table entry. */ | |
169 | ||
170 | /* Only used by the assembler, not the disassembler. */ | |
171 | #define TIC6X_FLAG_MACRO 0x0001 | |
172 | ||
173 | /* Must be first in its execute packet. */ | |
174 | #define TIC6X_FLAG_FIRST 0x0002 | |
175 | ||
176 | /* Multi-cycle NOP (not used for the NOP n instruction itself, which | |
177 | is only a multicycle NOP if n > 1). */ | |
178 | #define TIC6X_FLAG_MCNOP 0x0004 | |
179 | ||
180 | /* Cannot be in parallel with a multi-cycle NOP. */ | |
181 | #define TIC6X_FLAG_NO_MCNOP 0x0008 | |
182 | ||
183 | /* Load instruction. */ | |
184 | #define TIC6X_FLAG_LOAD 0x0010 | |
185 | ||
186 | /* Store instruction. */ | |
187 | #define TIC6X_FLAG_STORE 0x0020 | |
188 | ||
189 | /* Unaligned memory operation. */ | |
190 | #define TIC6X_FLAG_UNALIGNED 0x0040 | |
191 | ||
192 | /* Only on side B. */ | |
193 | #define TIC6X_FLAG_SIDE_B_ONLY 0x0080 | |
194 | ||
195 | /* Only on data path T2. */ | |
196 | #define TIC6X_FLAG_SIDE_T2_ONLY 0x0100 | |
197 | ||
198 | /* Does not support cross paths. */ | |
199 | #define TIC6X_FLAG_NO_CROSS 0x0200 | |
200 | ||
201 | /* Annotate this branch instruction as a call. */ | |
202 | #define TIC6X_FLAG_CALL 0x0400 | |
203 | ||
204 | /* Annotate this branch instruction as a return. */ | |
205 | #define TIC6X_FLAG_RETURN 0x0800 | |
206 | ||
207 | /* This instruction starts a software pipelined loop. */ | |
208 | #define TIC6X_FLAG_SPLOOP 0x1000 | |
209 | ||
210 | /* This instruction ends a software pipelined loop. */ | |
211 | #define TIC6X_FLAG_SPKERNEL 0x2000 | |
212 | ||
213 | /* This instruction takes a list of functional units as parameters; | |
214 | although described as having one parameter, the number may be 0 to | |
215 | 8. */ | |
216 | #define TIC6X_FLAG_SPMASK 0x4000 | |
217 | ||
218 | /* When more than one opcode matches the assembly source, prefer the | |
219 | one with the highest value for this bit-field. If two opcode table | |
220 | entries can match the same syntactic form, they must have different | |
221 | values here. */ | |
222 | #define TIC6X_PREFER_VAL(n) (((n) & 0x8000) >> 15) | |
223 | #define TIC6X_FLAG_PREFER(n) ((n) << 15) | |
51dcdd4d NC |
224 | |
225 | /* 16 bits opcode is predicated by register a0 (s = 0) or b0 (s = 1) */ | |
226 | #define TIC6X_FLAG_INSN16_SPRED 0x00100000 | |
227 | /* 16 bits opcode ignores RS bit of fetch packet header */ | |
228 | #define TIC6X_FLAG_INSN16_NORS 0x00200000 | |
229 | /* 16 bits opcode only on side B */ | |
230 | #define TIC6X_FLAG_INSN16_BSIDE 0x00400000 | |
231 | /* 16 bits opcode ptr reg is b15 */ | |
232 | #define TIC6X_FLAG_INSN16_B15PTR 0x00800000 | |
233 | /* 16 bits opcode memory access modes */ | |
234 | #define TIC6X_INSN16_MEM_MODE(n) ((n) << 16) | |
235 | #define TIC6X_INSN16_MEM_MODE_VAL(n) (((n) & 0x000F0000) >> 16) | |
236 | #define TIC6X_MEM_MODE_NEGATIVE 0 | |
237 | #define TIC6X_MEM_MODE_POSITIVE 1 | |
238 | #define TIC6X_MEM_MODE_REG_NEGATIVE 4 | |
239 | #define TIC6X_MEM_MODE_REG_POSITIVE 5 | |
240 | #define TIC6X_MEM_MODE_PREDECR 8 | |
241 | #define TIC6X_MEM_MODE_PREINCR 9 | |
242 | #define TIC6X_MEM_MODE_POSTDECR 10 | |
243 | #define TIC6X_MEM_MODE_POSTINCR 11 | |
244 | ||
245 | #define TIC6X_FLAG_INSN16_MEM_MODE(mode) TIC6X_INSN16_MEM_MODE(TIC6X_MEM_MODE_##mode) | |
246 | ||
40b36596 JM |
247 | #define TIC6X_NUM_PREFER 2 |
248 | ||
249 | /* Maximum number of fixed fields for a particular opcode. */ | |
250 | #define TIC6X_MAX_FIXED_FIELDS 4 | |
251 | ||
252 | /* Maximum number of operands in the opcode table for a particular | |
253 | opcode. */ | |
254 | #define TIC6X_MAX_OPERANDS 4 | |
255 | ||
256 | /* Maximum number of operands in the source code for a particular | |
257 | opcode (different from the number in the opcode table for SPMASK | |
258 | and SPMASKR). */ | |
259 | #define TIC6X_MAX_SOURCE_OPERANDS 8 | |
260 | ||
261 | /* Maximum number of variable fields for a particular opcode. */ | |
262 | #define TIC6X_MAX_VAR_FIELDS 7 | |
263 | ||
264 | /* Which functional units an opcode uses. This only describes the | |
265 | basic choice of D, L, M, S or no functional unit; other fields are | |
266 | used to describe further restrictions (instructions only operating | |
267 | on one side), use of cross paths and load/store instructions using | |
268 | one side for the address and the other side for the source or | |
269 | destination register. */ | |
270 | typedef enum | |
271 | { | |
272 | tic6x_func_unit_d, | |
273 | tic6x_func_unit_l, | |
274 | tic6x_func_unit_m, | |
275 | tic6x_func_unit_s, | |
276 | tic6x_func_unit_nfu | |
277 | } tic6x_func_unit_base; | |
278 | ||
279 | /* Possible forms of source operand. */ | |
280 | typedef enum | |
281 | { | |
282 | /* An assembly-time constant. */ | |
283 | tic6x_operand_asm_const, | |
284 | /* A link-time constant. */ | |
285 | tic6x_operand_link_const, | |
286 | /* A register, from the same side as the functional unit | |
287 | selected. */ | |
288 | tic6x_operand_reg, | |
51dcdd4d NC |
289 | /* A register, from the same side as the functional unit |
290 | selected that ignore RS header bit */ | |
291 | tic6x_operand_reg_nors, | |
292 | /* A register, from the b side */ | |
293 | tic6x_operand_reg_bside, | |
294 | /* A register, from the b side and from the low register set */ | |
295 | tic6x_operand_reg_bside_nors, | |
40b36596 JM |
296 | /* A register, that is from the other side if a cross path is |
297 | used. */ | |
298 | tic6x_operand_xreg, | |
299 | /* A register, that is from the side of the data path | |
300 | selected. */ | |
301 | tic6x_operand_dreg, | |
302 | /* An address register usable with 15-bit offsets (B14 or B15). | |
303 | This is from the same side as the functional unit if a cross | |
304 | path is not used, and the other side if a cross path is | |
305 | used. */ | |
306 | tic6x_operand_areg, | |
51dcdd4d NC |
307 | /* The B15 register */ |
308 | tic6x_operand_b15reg, | |
309 | /* A register coded as an offset from either A16 or B16 depending | |
310 | on the value of the t bit. */ | |
311 | tic6x_operand_treg, | |
312 | /* A register (A0 or B0), from the same side as the | |
313 | functional unit selected. */ | |
314 | tic6x_operand_zreg, | |
40b36596 JM |
315 | /* A return address register (A3 or B3), from the same side as the |
316 | functional unit selected. */ | |
317 | tic6x_operand_retreg, | |
318 | /* A register pair, from the same side as the functional unit | |
319 | selected. */ | |
320 | tic6x_operand_regpair, | |
321 | /* A register pair, that is from the other side if a cross path is | |
322 | used. */ | |
323 | tic6x_operand_xregpair, | |
324 | /* A register pair, from the side of the data path selected. */ | |
325 | tic6x_operand_dregpair, | |
51dcdd4d NC |
326 | /* A register pair coded as an offset from either A16 or B16 depending |
327 | on the value of the t bit. */ | |
328 | tic6x_operand_tregpair, | |
40b36596 JM |
329 | /* The literal string "irp" (case-insensitive). */ |
330 | tic6x_operand_irp, | |
331 | /* The literal string "nrp" (case-insensitive). */ | |
332 | tic6x_operand_nrp, | |
51dcdd4d NC |
333 | /* The literal string "ilc" (case-insensitive). */ |
334 | tic6x_operand_ilc, | |
40b36596 JM |
335 | /* A control register. */ |
336 | tic6x_operand_ctrl, | |
337 | /* A memory reference (base and offset registers from the side of | |
338 | the functional unit selected), using either unsigned 5-bit | |
339 | constant or register offset, if any offset; register offsets | |
340 | cannot use unscaled () syntax. */ | |
341 | tic6x_operand_mem_short, | |
342 | /* A memory reference (base and offset registers from the side of | |
343 | the functional unit selected), using either unsigned 5-bit | |
344 | constant or register offset, if any offset; register offsets | |
345 | can use unscaled () syntax (for LDNDW and STNDW). */ | |
346 | tic6x_operand_mem_ndw, | |
347 | /* A memory reference using 15-bit link-time constant offset | |
348 | relative to B14 or B15. */ | |
349 | tic6x_operand_mem_long, | |
350 | /* A memory reference that only dereferences a register with no | |
351 | further adjustments (*REG), that register being from the side | |
352 | of the functional unit selected. */ | |
353 | tic6x_operand_mem_deref, | |
354 | /* A functional unit name or a list thereof (for SPMASK and | |
355 | SPMASKR). */ | |
51dcdd4d NC |
356 | tic6x_operand_func_unit, |
357 | /* Hardwired constant '5' in Sbu8 Scs10 and Sbu8c 16 bits | |
358 | instruction formats - spru732j.pdf Appendix F.4 */ | |
359 | tic6x_operand_hw_const_minus_1, | |
360 | tic6x_operand_hw_const_0, | |
361 | tic6x_operand_hw_const_1, | |
362 | tic6x_operand_hw_const_5, | |
363 | tic6x_operand_hw_const_16, | |
364 | tic6x_operand_hw_const_24, | |
365 | tic6x_operand_hw_const_31 | |
40b36596 JM |
366 | } tic6x_operand_form; |
367 | ||
368 | /* Whether something is, or can be, read or written. */ | |
369 | typedef enum | |
370 | { | |
371 | tic6x_rw_none, | |
372 | tic6x_rw_read, | |
373 | tic6x_rw_write, | |
374 | tic6x_rw_read_write | |
375 | } tic6x_rw; | |
376 | ||
377 | /* Description of a source operand and how it is used. */ | |
378 | typedef struct | |
379 | { | |
380 | /* The syntactic form of the operand. */ | |
381 | tic6x_operand_form form; | |
382 | ||
383 | /* For non-constant operands, the size in bytes (1, 2, 4, 5 or | |
384 | 8). Ignored for constant operands. */ | |
385 | unsigned int size; | |
386 | ||
387 | /* Whether the operand is read, written or both. In addition to the | |
388 | operations described here, address registers are read on cycle 1 | |
389 | regardless of when the memory operand is read or written, and may | |
390 | be modified as described by the addressing mode, and control | |
391 | registers may be implicitly read by some instructions. There are | |
392 | also some special cases not fully described by this | |
393 | structure. | |
394 | ||
395 | - For mpydp, the low part of src2 is read on cycles 1 and 3 but | |
396 | not 2, and the high part on cycles 2 and 4 but not 3. | |
397 | ||
398 | - The swap2 pseudo-operation maps to packlh2, reading the first | |
399 | operand of swap2 twice. */ | |
400 | tic6x_rw rw; | |
401 | ||
402 | /* The first and last cycles (1 for E1, etc.) at which the operand, | |
403 | or the low part for two-register operands, is read or | |
404 | written. */ | |
405 | unsigned short low_first; | |
406 | unsigned short low_last; | |
407 | ||
408 | /* Likewise, for the high part. */ | |
409 | unsigned short high_first; | |
410 | unsigned short high_last; | |
411 | } tic6x_operand_info; | |
412 | ||
413 | /* Ways of converting an operand or functional unit specifier to a | |
414 | field value. */ | |
415 | typedef enum | |
416 | { | |
417 | /* Store an unsigned assembly-time constant (which must fit) in | |
418 | the field. */ | |
419 | tic6x_coding_ucst, | |
420 | /* Store a signed constant (which must fit) in the field. This | |
421 | may be used both for assembly-time constants and for link-time | |
422 | constants. */ | |
423 | tic6x_coding_scst, | |
424 | /* Subtract one from an unsigned assembly-time constant (which | |
425 | must be strictly positive before the subtraction) and store the | |
426 | value (which must fit) in the field. */ | |
427 | tic6x_coding_ucst_minus_one, | |
428 | /* Negate a signed assembly-time constant, and store the result of | |
429 | negation (which must fit) in the field. Used only for | |
430 | pseudo-operations. */ | |
431 | tic6x_coding_scst_negate, | |
432 | /* Store an unsigned link-time constant, implicitly DP-relative | |
433 | and counting in bytes, in the field. For expression operands, | |
434 | assembly-time constants are encoded as-is. For memory | |
435 | reference operands, the offset is encoded as-is if [] syntax is | |
436 | used and shifted if () is used. */ | |
437 | tic6x_coding_ulcst_dpr_byte, | |
438 | /* Store an unsigned link-time constant, implicitly DP-relative | |
439 | and counting in half-words, in the field. For expression | |
440 | operands, assembly-time constants are encoded as-is. For | |
441 | memory reference operands, the offset is encoded as-is if [] | |
442 | syntax is used and shifted if () is used. */ | |
443 | tic6x_coding_ulcst_dpr_half, | |
444 | /* Store an unsigned link-time constant, implicitly DP-relative | |
445 | and counting in words, in the field. For expression operands, | |
446 | assembly-time constants are encoded as-is. For memory | |
447 | reference operands, the offset is encoded as-is if [] syntax is | |
448 | used and shifted if () is used. */ | |
449 | tic6x_coding_ulcst_dpr_word, | |
450 | /* Store the low 16 bits of a link-time constant in the field; | |
451 | considered unsigned for disassembly. */ | |
452 | tic6x_coding_lcst_low16, | |
453 | /* Store the high 16 bits of a link-time constant in the field; | |
454 | considered unsigned for disassembly. */ | |
455 | tic6x_coding_lcst_high16, | |
456 | /* Store a signed PC-relative value (address of label minus | |
457 | address of fetch packet containing the current instruction, | |
458 | counted in words) in the field. */ | |
459 | tic6x_coding_pcrel, | |
460 | /* Likewise, but counting in half-words if in a header-based fetch | |
461 | packet. */ | |
462 | tic6x_coding_pcrel_half, | |
51dcdd4d NC |
463 | /* Store an unsigned PC-relative value used in compact insn */ |
464 | tic6x_coding_pcrel_half_unsigned, | |
40b36596 JM |
465 | /* Encode the register number (even number for a register pair) in |
466 | the field. When applied to a memory reference, encode the base | |
467 | register. */ | |
468 | tic6x_coding_reg, | |
795b8e6b NC |
469 | /* Encode the register-pair's lsb (even register) for instructions |
470 | that use src1 as port for loading lsb of double-precision | |
471 | operand value (absdp, dpint, dpsp, dptrunc, rcpdp, rsqrdp). */ | |
472 | tic6x_coding_regpair_lsb, | |
473 | /* Encode the register-pair's msb (odd register), see above. */ | |
474 | tic6x_coding_regpair_msb, | |
40b36596 JM |
475 | /* Store 0 for register B14, 1 for register B15. When applied to |
476 | a memory reference, encode the base register. */ | |
477 | tic6x_coding_areg, | |
51dcdd4d NC |
478 | /* Compact instruction offset base register */ |
479 | tic6x_coding_reg_ptr, | |
40b36596 JM |
480 | /* Store the low part of a control register address. */ |
481 | tic6x_coding_crlo, | |
482 | /* Store the high part of a control register address. */ | |
483 | tic6x_coding_crhi, | |
484 | /* Encode the even register number for a register pair, shifted | |
485 | right by one bit. */ | |
486 | tic6x_coding_reg_shift, | |
487 | /* Store either the offset register or the 5-bit unsigned offset | |
488 | for a memory reference. If an offset uses the unscaled () | |
489 | form, which is only permitted with constants, it is scaled | |
490 | according to the access size of the operand before being | |
491 | stored. */ | |
492 | tic6x_coding_mem_offset, | |
493 | /* Store either the offset register or the 5-bit unsigned offset | |
494 | for a memory reference, but with no scaling applied to the | |
495 | offset (for nonaligned doubleword operations). */ | |
496 | tic6x_coding_mem_offset_noscale, | |
497 | /* Store the addressing mode for a memory reference. */ | |
498 | tic6x_coding_mem_mode, | |
499 | /* Store whether a memory reference is scaled. */ | |
500 | tic6x_coding_scaled, | |
501 | /* Store the stage in an SPKERNEL instruction in the upper part of | |
502 | the field. */ | |
503 | tic6x_coding_fstg, | |
504 | /* Store the cycle in an SPKERNEL instruction in the lower part of | |
505 | the field. */ | |
506 | tic6x_coding_fcyc, | |
507 | /* Store the mask bits for functional units in the field in an | |
508 | SPMASK or SPMASKR instruction. */ | |
509 | tic6x_coding_spmask, | |
510 | /* Store the number of a register that is unused, or minimally | |
511 | used, in this execute packet. The number must be the same for | |
512 | all uses of this coding in a single instruction, but may be | |
513 | different for different instructions in the execute packet. | |
514 | This is for the "zero" pseudo-operation. This is not safe when | |
515 | reads may occur from instructions in previous execute packets; | |
516 | in such cases the programmer or compiler should use explicit | |
517 | "sub" instructions for those cases of "zero" that cannot be | |
518 | implemented as "mvk" for the processor specified. */ | |
519 | tic6x_coding_reg_unused, | |
520 | /* Store 1 if the functional unit used is on side B, 0 for side | |
521 | A. */ | |
522 | tic6x_coding_fu, | |
523 | /* Store 1 if the data path used (source register for store, | |
524 | destination for load) is on side B, 0 for side A. */ | |
525 | tic6x_coding_data_fu, | |
526 | /* Store 1 if the cross path is being used, 0 otherwise. */ | |
51dcdd4d NC |
527 | tic6x_coding_xpath, |
528 | /* L3i constant coding */ | |
529 | tic6x_coding_scst_l3i, | |
530 | /* S3i constant coding */ | |
531 | tic6x_coding_cst_s3i, | |
532 | /* mem offset minus 1 */ | |
533 | tic6x_coding_mem_offset_minus_one, | |
534 | /* non aligned mem offset minus 1 */ | |
535 | tic6x_coding_mem_offset_minus_one_noscale, | |
536 | tic6x_coding_rside | |
40b36596 JM |
537 | } tic6x_coding_method; |
538 | ||
539 | /* How to generate the value of a particular field. */ | |
540 | typedef struct | |
541 | { | |
542 | /* The name of the field. */ | |
543 | tic6x_insn_field_id field_id; | |
544 | ||
545 | /* How it is encoded. */ | |
546 | tic6x_coding_method coding_method; | |
547 | ||
548 | /* Source operand number, if any. */ | |
549 | unsigned int operand_num; | |
550 | } tic6x_coding_field; | |
551 | ||
552 | /* Types of instruction for pipeline purposes. The type determines | |
553 | functional unit and cross path latency (when the same functional | |
554 | unit can be used by other instructions, when the same cross path | |
555 | can be used by other instructions). */ | |
556 | typedef enum | |
557 | { | |
558 | tic6x_pipeline_nop, | |
559 | tic6x_pipeline_1cycle, | |
560 | tic6x_pipeline_1616_m, | |
561 | tic6x_pipeline_store, | |
562 | tic6x_pipeline_mul_ext, | |
563 | tic6x_pipeline_load, | |
564 | tic6x_pipeline_branch, | |
565 | tic6x_pipeline_2cycle_dp, | |
566 | tic6x_pipeline_4cycle, | |
567 | tic6x_pipeline_intdp, | |
568 | tic6x_pipeline_dpcmp, | |
569 | tic6x_pipeline_addsubdp, | |
570 | tic6x_pipeline_mpyi, | |
571 | tic6x_pipeline_mpyid, | |
572 | tic6x_pipeline_mpydp, | |
573 | tic6x_pipeline_mpyspdp, | |
574 | tic6x_pipeline_mpysp2dp | |
575 | } tic6x_pipeline_type; | |
576 | ||
577 | /* Description of a control register. */ | |
578 | typedef struct | |
579 | { | |
580 | /* The name of the register. */ | |
581 | const char *name; | |
582 | ||
583 | /* Which ISA variants include this control register. */ | |
584 | unsigned short isa_variants; | |
585 | ||
586 | /* Whether it can be read, written or both (in supervisor mode). | |
587 | Some registers use the same address, but different names, for | |
588 | reading and writing. */ | |
589 | tic6x_rw rw; | |
590 | ||
591 | /* crlo value for this register. */ | |
592 | unsigned int crlo; | |
593 | ||
594 | /* Mask that, ANDed with the crhi value in the instruction, must be | |
595 | 0. 0 is always generated when generating code. */ | |
596 | unsigned int crhi_mask; | |
597 | } tic6x_ctrl; | |
598 | ||
599 | /* An index into the table of control registers. */ | |
600 | typedef enum | |
601 | { | |
602 | #define CTRL(name, isa, rw, crlo, crhi_mask) \ | |
603 | CONCAT2(tic6x_ctrl_,name), | |
604 | #include "tic6x-control-registers.h" | |
605 | #undef CTRL | |
606 | tic6x_ctrl_max | |
607 | } tic6x_ctrl_id; | |
608 | ||
609 | /* The table itself. */ | |
610 | extern const tic6x_ctrl tic6x_ctrl_table[tic6x_ctrl_max]; | |
611 | ||
612 | /* An entry in the opcode table. */ | |
613 | typedef struct | |
614 | { | |
615 | /* The name of the instruction. */ | |
616 | const char *name; | |
617 | ||
618 | /* Functional unit used by this instruction (basic information). */ | |
619 | tic6x_func_unit_base func_unit; | |
620 | ||
621 | /* The format of this instruction. */ | |
622 | tic6x_insn_format_id format; | |
623 | ||
624 | /* The pipeline type of this instruction. */ | |
625 | tic6x_pipeline_type type; | |
626 | ||
627 | /* Which ISA variants include this instruction. */ | |
628 | unsigned short isa_variants; | |
629 | ||
630 | /* Flags for this instruction. */ | |
51dcdd4d | 631 | unsigned int flags; |
40b36596 JM |
632 | |
633 | /* Number of fixed fields, or fields with restricted value ranges, | |
634 | for this instruction. */ | |
635 | unsigned int num_fixed_fields; | |
636 | ||
637 | /* Values of fields fixed for this instruction. */ | |
638 | tic6x_fixed_field fixed_fields[TIC6X_MAX_FIXED_FIELDS]; | |
639 | ||
640 | /* The number of operands in the source form of this | |
641 | instruction. */ | |
642 | unsigned int num_operands; | |
643 | ||
644 | /* Information about individual operands. */ | |
645 | tic6x_operand_info operand_info[TIC6X_MAX_OPERANDS]; | |
646 | ||
647 | /* The number of variable fields for this instruction with encoding | |
648 | instructions explicitly given. */ | |
649 | unsigned int num_variable_fields; | |
650 | ||
651 | /* How fields (other than ones with fixed value) are computed from | |
652 | the source operands and functional unit specifiers. In addition | |
653 | to fields specified here: | |
654 | ||
655 | - creg, if present, is set from the predicate, along with z which | |
656 | must be present if creg is present. | |
657 | ||
658 | - p, if present (on all non-compact instructions), is set from | |
659 | the parallel bars. | |
660 | */ | |
661 | tic6x_coding_field variable_fields[TIC6X_MAX_VAR_FIELDS]; | |
662 | } tic6x_opcode; | |
663 | ||
664 | /* An index into the table of opcodes. */ | |
665 | typedef enum | |
666 | { | |
667 | #define INSN(name, func_unit, format, type, isa, flags, fixed, ops, var) \ | |
668 | CONCAT6(tic6x_opcode_,name,_,func_unit,_,format), | |
669 | #define INSNE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \ | |
670 | CONCAT4(tic6x_opcode_,name,_,e), | |
51dcdd4d NC |
671 | #define INSNU(name, func_unit, format, type, isa, flags, fixed, ops, var) \ |
672 | CONCAT6(tic6x_opcode_,name,_,func_unit,_,format), | |
673 | #define INSNUE(name, e, func_unit, format, type, isa, flags, fixed, ops, var) \ | |
674 | CONCAT6(tic6x_opcode_,name,_,func_unit,_,e), | |
40b36596 JM |
675 | #include "tic6x-opcode-table.h" |
676 | #undef INSN | |
677 | #undef INSNE | |
51dcdd4d NC |
678 | #undef INSNU |
679 | #undef INSNUE | |
40b36596 JM |
680 | tic6x_opcode_max |
681 | } tic6x_opcode_id; | |
682 | ||
683 | /* The table itself. */ | |
684 | extern const tic6x_opcode tic6x_opcode_table[tic6x_opcode_max]; | |
685 | ||
686 | /* A linked list of opcodes. */ | |
687 | typedef struct tic6x_opcode_list_tag | |
688 | { | |
689 | tic6x_opcode_id id; | |
690 | struct tic6x_opcode_list_tag *next; | |
691 | } tic6x_opcode_list; | |
692 | ||
693 | /* The information from a fetch packet header. */ | |
694 | typedef struct | |
695 | { | |
696 | /* The header itself. */ | |
697 | unsigned int header; | |
698 | ||
699 | /* Whether each word uses compact instructions. */ | |
700 | bfd_boolean word_compact[7]; | |
701 | ||
702 | /* Whether loads are protected. */ | |
703 | bfd_boolean prot; | |
704 | ||
705 | /* Whether instructions use the high register set. */ | |
706 | bfd_boolean rs; | |
707 | ||
708 | /* Data size. */ | |
709 | unsigned int dsz; | |
710 | ||
711 | /* Whether compact instructions in the S unit are decoded as | |
712 | branches. */ | |
713 | bfd_boolean br; | |
714 | ||
715 | /* Whether compact instructions saturate. */ | |
716 | bfd_boolean sat; | |
717 | ||
718 | /* P-bits. */ | |
719 | bfd_boolean p_bits[14]; | |
720 | } tic6x_fetch_packet_header; | |
721 | ||
1fe0971e TS |
722 | #ifdef __cplusplus |
723 | } | |
724 | #endif | |
725 | ||
40b36596 | 726 | #endif /* OPCODE_TIC6X_H */ |