[librseq.git] / include / rseq / arch / aarch64.h

/* SPDX-License-Identifier: MIT */
/* SPDX-FileCopyrightText: 2016-2024 Mathieu Desnoyers <mathieu.desnoyers@efficios.com> */
/* SPDX-FileCopyrightText: 2018 Will Deacon <will.deacon@arm.com> */

/*
 * rseq/arch/aarch64.h
 */

#ifndef _RSEQ_RSEQ_H
#error "Never use <rseq/arch/aarch64.h> directly; include <rseq/rseq.h> instead."
#endif

/*
 * RSEQ_ASM_*() macro helpers are internal to the librseq headers. Those
 * are not part of the public API.
 */

/*
 * aarch64 -mbig-endian generates mixed endianness code vs data:
 * little-endian code and big-endian data. Ensure the RSEQ_SIG signature
 * matches code endianness.
 */
#define RSEQ_SIG_CODE	0xd428bc00	/* BRK #0x45E0.  */

#ifdef __AARCH64EB__	/* Big endian */
# define RSEQ_SIG_DATA	0x00bc28d4	/* BRK #0x45E0.  */
#else			/* Little endian */
# define RSEQ_SIG_DATA	RSEQ_SIG_CODE
#endif

#define RSEQ_SIG	RSEQ_SIG_DATA

/*
 * Refer to the Linux kernel memory model (LKMM) for documentation of
 * the memory barriers.
 */

/* CPU memory barrier. */
#define rseq_smp_mb()	__asm__ __volatile__ ("dmb ish" ::: "memory")
/* CPU read memory barrier */
#define rseq_smp_rmb()	__asm__ __volatile__ ("dmb ishld" ::: "memory")
/* CPU write memory barrier */
#define rseq_smp_wmb()	__asm__ __volatile__ ("dmb ishst" ::: "memory")

/* Acquire: One-way permeable barrier. */
#define rseq_smp_load_acquire(p)						\
__extension__ ({								\
	union { rseq_unqual_scalar_typeof(*(p)) __val; char __c[sizeof(*(p))]; } __u; \
	switch (sizeof(*(p))) {							\
	case 1:									\
		__asm__ __volatile__ ("ldarb %w0, %1"				\
			: "=r" (*(__u8 *)__u.__c)				\
			: "Q" (*(p)) : "memory");				\
		break;								\
	case 2:									\
		__asm__ __volatile__ ("ldarh %w0, %1"				\
			: "=r" (*(__u16 *)__u.__c)				\
			: "Q" (*(p)) : "memory");				\
		break;								\
	case 4:									\
		__asm__ __volatile__ ("ldar %w0, %1"				\
			: "=r" (*(__u32 *)__u.__c)				\
			: "Q" (*(p)) : "memory");				\
		break;								\
	case 8:									\
		__asm__ __volatile__ ("ldar %0, %1"				\
			: "=r" (*(__u64 *)__u.__c)				\
			: "Q" (*(p)) : "memory");				\
		break;								\
	}									\
	(rseq_unqual_scalar_typeof(*(p)))__u.__val;				\
})

/* Acquire barrier after control dependency. */
#define rseq_smp_acquire__after_ctrl_dep()	rseq_smp_rmb()

/* Release: One-way permeable barrier. */
#define rseq_smp_store_release(p, v)						\
do {										\
	union { rseq_unqual_scalar_typeof(*(p)) __val; char __c[sizeof(*(p))]; } __u = \
		{ .__val = (rseq_unqual_scalar_typeof(*(p))) (v) };		\
	switch (sizeof(*(p))) {							\
	case 1:									\
		__asm__ __volatile__ ("stlrb %w1, %0"				\
				: "=Q" (*(p))					\
				: "r" (*(__u8 *)__u.__c)			\
				: "memory");					\
		break;								\
	case 2:									\
		__asm__ __volatile__ ("stlrh %w1, %0"				\
				: "=Q" (*(p))					\
				: "r" (*(__u16 *)__u.__c)			\
				: "memory");					\
		break;								\
	case 4:									\
		__asm__ __volatile__ ("stlr %w1, %0"				\
				: "=Q" (*(p))					\
				: "r" (*(__u32 *)__u.__c)			\
				: "memory");					\
		break;								\
	case 8:									\
		__asm__ __volatile__ ("stlr %1, %0"				\
				: "=Q" (*(p))					\
				: "r" (*(__u64 *)__u.__c)			\
				: "memory");					\
		break;								\
	}									\
} while (0)

#define RSEQ_ASM_U64_PTR(x)	".quad " x
#define RSEQ_ASM_U32(x)		".long " x

/* Temporary scratch registers. */
#define RSEQ_ASM_TMP_REG32	"w15"
#define RSEQ_ASM_TMP_REG	"x15"
#define RSEQ_ASM_TMP_REG_2	"x14"

/* Common architecture support macros. */
#include "rseq/arch/generic/common.h"

/*
 * Define a critical section abort handler.
 *
 *  @label:
 *    Local label to the abort handler.
 *  @teardown:
 *    Sequence of instructions to run on abort.
 *  @abort_label:
 *    C label to jump to at the end of the sequence.
 */
#define RSEQ_ASM_DEFINE_ABORT(label, teardown, abort_label)			\
	"	b	222f\n"							\
	"	.inst 	"	__rseq_str(RSEQ_SIG_CODE) "\n"			\
	__rseq_str(label) ":\n"							\
	teardown								\
	"	b	%l[" __rseq_str(abort_label) "]\n"			\
	"222:\n"

/* Jump to local label @label when @cpu_id != @current_cpu_id. */
#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs)			\
	RSEQ_INJECT_ASM(1)							\
	"	adrp	" RSEQ_ASM_TMP_REG ", " __rseq_str(cs_label) "\n"	\
	"	add	" RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG		\
			", :lo12:" __rseq_str(cs_label) "\n"			\
	"	str	" RSEQ_ASM_TMP_REG ", %[" __rseq_str(rseq_cs) "]\n"	\
	__rseq_str(label) ":\n"

/* Store @value to address @var. */
#define RSEQ_ASM_OP_STORE(value, var)						\
	"	str	%[" __rseq_str(value) "], %[" __rseq_str(var) "]\n"

/* Store-release @value to address @var. */
#define RSEQ_ASM_OP_STORE_RELEASE(value, var)					\
	"	stlr	%[" __rseq_str(value) "], %[" __rseq_str(var) "]\n"

/*
 * End-of-sequence store of @value to address @var. Emit
 * @post_commit_label label after the store instruction.
 */
#define RSEQ_ASM_OP_FINAL_STORE(value, var, post_commit_label)			\
	RSEQ_ASM_OP_STORE(value, var)						\
	__rseq_str(post_commit_label) ":\n"

/*
 * End-of-sequence store-release of @value to address @var. Emit
 * @post_commit_label label after the store instruction.
 */
#define RSEQ_ASM_OP_FINAL_STORE_RELEASE(value, var, post_commit_label)		\
	RSEQ_ASM_OP_STORE_RELEASE(value, var)					\
	__rseq_str(post_commit_label) ":\n"

/* Jump to local label @label when @var != @expect. */
#define RSEQ_ASM_OP_CBNE(var, expect, label)					\
	"	ldr	" RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"		\
	"	sub	" RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG		\
			", %[" __rseq_str(expect) "]\n"				\
	"	cbnz	" RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n"

/*
 * Jump to local label @label when @var != @expect (32-bit register
 * comparison).
 */
#define RSEQ_ASM_OP_CBNE32(var, expect, label)					\
	"	ldr	" RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n"	\
	"	sub	" RSEQ_ASM_TMP_REG32 ", " RSEQ_ASM_TMP_REG32		\
			", %w[" __rseq_str(expect) "]\n"			\
	"	cbnz	" RSEQ_ASM_TMP_REG32 ", " __rseq_str(label) "\n"

/* Jump to local label @label when @var == @expect. */
#define RSEQ_ASM_OP_CBEQ(var, expect, label)					\
	"	ldr	" RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"		\
	"	sub	" RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG		\
			", %[" __rseq_str(expect) "]\n"				\
	"	cbz	" RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n"

/* Jump to local label @label when @cpu_id != @current_cpu_id. */
#define RSEQ_ASM_CBNE_CPU_ID(cpu_id, current_cpu_id, label)			\
	RSEQ_INJECT_ASM(2)							\
	RSEQ_ASM_OP_CBNE32(current_cpu_id, cpu_id, label)

/* Load @var into temporary register. */
#define RSEQ_ASM_OP_R_LOAD(var)							\
	"	ldr	" RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"

/* Store from temporary register into @var. */
#define RSEQ_ASM_OP_R_STORE(var)						\
	"	str	" RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"

/* Load from address in temporary register+@offset into temporary register. */
#define RSEQ_ASM_OP_R_LOAD_OFF(offset)						\
	"	ldr	" RSEQ_ASM_TMP_REG ", [" RSEQ_ASM_TMP_REG		\
			", %[" __rseq_str(offset) "]]\n"

/* Add @count to temporary register. */
#define RSEQ_ASM_OP_R_ADD(count)						\
	"	add	" RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG		\
			", %[" __rseq_str(count) "]\n"

/*
 * End-of-sequence store of temporary register to address @var. Emit
 * @post_commit_label label after the store instruction.
 */
#define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label)			\
	"	str	" RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"		\
	__rseq_str(post_commit_label) ":\n"

/*
 * Copy @len bytes from @src to @dst. This is an inefficient bytewise
 * copy and could be improved in the future.
 */
#define RSEQ_ASM_OP_R_BYTEWISE_MEMCPY(dst, src, len)				\
	"	cbz	%[" __rseq_str(len) "], 333f\n"				\
	"	mov	" RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(len) "]\n"	\
	"222:	sub	" RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", #1\n"	\
	"	ldrb	" RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(src) "]"	\
			", " RSEQ_ASM_TMP_REG_2 "]\n"				\
	"	strb	" RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(dst) "]"	\
			", " RSEQ_ASM_TMP_REG_2 "]\n"				\
	"	cbnz	" RSEQ_ASM_TMP_REG_2 ", 222b\n"				\
	"333:\n"

/* Per-cpu-id indexing. */

#define RSEQ_TEMPLATE_INDEX_CPU_ID
#define RSEQ_TEMPLATE_MO_RELAXED
#include "rseq/arch/aarch64/bits.h"
#undef RSEQ_TEMPLATE_MO_RELAXED

#define RSEQ_TEMPLATE_MO_RELEASE
#include "rseq/arch/aarch64/bits.h"
#undef RSEQ_TEMPLATE_MO_RELEASE
#undef RSEQ_TEMPLATE_INDEX_CPU_ID

/* Per-mm-cid indexing. */

#define RSEQ_TEMPLATE_INDEX_MM_CID
#define RSEQ_TEMPLATE_MO_RELAXED
#include "rseq/arch/aarch64/bits.h"
#undef RSEQ_TEMPLATE_MO_RELAXED

#define RSEQ_TEMPLATE_MO_RELEASE
#include "rseq/arch/aarch64/bits.h"
#undef RSEQ_TEMPLATE_MO_RELEASE
#undef RSEQ_TEMPLATE_INDEX_MM_CID

/* APIs which are not indexed. */

#define RSEQ_TEMPLATE_INDEX_NONE
#define RSEQ_TEMPLATE_MO_RELAXED
#include "rseq/arch/aarch64/bits.h"
#undef RSEQ_TEMPLATE_MO_RELAXED
#undef RSEQ_TEMPLATE_INDEX_NONE
Commit	Line	Data
90702366	1	/* SPDX-License-Identifier: MIT */
21b58a3b	2	/* SPDX-FileCopyrightText: 2016-2024 Mathieu Desnoyers <mathieu.desnoyers@efficios.com> */
f2d7b530 MJ	3	/* SPDX-FileCopyrightText: 2018 Will Deacon <will.deacon@arm.com> */
f2d7b530 MJ	4
d78a16c2	5	/*
44ec21eb	6	* rseq/arch/aarch64.h
d78a16c2 MD	7	*/
d78a16c2 MD	8
44ec21eb MJ	9	#ifndef _RSEQ_RSEQ_H
	10	#error "Never use <rseq/arch/aarch64.h> directly; include <rseq/rseq.h> instead."
	11	#endif
	12
21b58a3b MD	13	/*
	14	* RSEQ_ASM_*() macro helpers are internal to the librseq headers. Those
	15	* are not part of the public API.
	16	*/
	17
8b7c64f7 MD	18	/*
	19	* aarch64 -mbig-endian generates mixed endianness code vs data:
	20	* little-endian code and big-endian data. Ensure the RSEQ_SIG signature
	21	* matches code endianness.
	22	*/
	23	#define RSEQ_SIG_CODE 0xd428bc00 /* BRK #0x45E0. */
	24
dbbd006a MD	25	#ifdef __AARCH64EB__ /* Big endian */
	26	# define RSEQ_SIG_DATA 0x00bc28d4 /* BRK #0x45E0. */
	27	#else /* Little endian */
	28	# define RSEQ_SIG_DATA RSEQ_SIG_CODE
8b7c64f7 MD	29	#endif
	30
	31	#define RSEQ_SIG RSEQ_SIG_DATA
d78a16c2	32
21b58a3b MD	33	/*
	34	* Refer to the Linux kernel memory model (LKMM) for documentation of
	35	* the memory barriers.
	36	*/
	37
	38	/* CPU memory barrier. */
d78a16c2	39	#define rseq_smp_mb() __asm__ __volatile__ ("dmb ish" ::: "memory")
21b58a3b	40	/* CPU read memory barrier */
d78a16c2	41	#define rseq_smp_rmb() __asm__ __volatile__ ("dmb ishld" ::: "memory")
21b58a3b	42	/* CPU write memory barrier */
d78a16c2 MD	43	#define rseq_smp_wmb() __asm__ __volatile__ ("dmb ishst" ::: "memory")
d78a16c2 MD	44
21b58a3b	45	/* Acquire: One-way permeable barrier. */
d78a16c2 MD	46	#define rseq_smp_load_acquire(p) \
d78a16c2 MD	47	__extension__ ({ \
18ca65e0 MD	48	union { rseq_unqual_scalar_typeof((p)) __val; char __c[sizeof((p))]; } __u; \
18ca65e0 MD	49	switch (sizeof(*(p))) { \
d78a16c2	50	case 1: \
18ca65e0 MD	51	__asm__ __volatile__ ("ldarb %w0, %1" \
	52	: "=r" ((__u8 )__u.__c) \
	53	: "Q" (*(p)) : "memory"); \
d78a16c2 MD	54	break; \
d78a16c2 MD	55	case 2: \
18ca65e0 MD	56	__asm__ __volatile__ ("ldarh %w0, %1" \
	57	: "=r" ((__u16 )__u.__c) \
	58	: "Q" (*(p)) : "memory"); \
d78a16c2 MD	59	break; \
d78a16c2 MD	60	case 4: \
18ca65e0 MD	61	__asm__ __volatile__ ("ldar %w0, %1" \
	62	: "=r" ((__u32 )__u.__c) \
	63	: "Q" (*(p)) : "memory"); \
d78a16c2 MD	64	break; \
d78a16c2 MD	65	case 8: \
18ca65e0 MD	66	__asm__ __volatile__ ("ldar %0, %1" \
	67	: "=r" ((__u64 )__u.__c) \
	68	: "Q" (*(p)) : "memory"); \
d78a16c2 MD	69	break; \
d78a16c2 MD	70	} \
0aac367c	71	(rseq_unqual_scalar_typeof(*(p)))__u.__val; \
d78a16c2 MD	72	})
d78a16c2 MD	73
21b58a3b	74	/* Acquire barrier after control dependency. */
d78a16c2 MD	75	#define rseq_smp_acquire__after_ctrl_dep() rseq_smp_rmb()
d78a16c2 MD	76
21b58a3b	77	/* Release: One-way permeable barrier. */
d78a16c2 MD	78	#define rseq_smp_store_release(p, v) \
d78a16c2 MD	79	do { \
18ca65e0 MD	80	union { rseq_unqual_scalar_typeof((p)) __val; char __c[sizeof((p))]; } __u = \
	81	{ .__val = (rseq_unqual_scalar_typeof(*(p))) (v) }; \
	82	switch (sizeof(*(p))) { \
d78a16c2	83	case 1: \
18ca65e0 MD	84	__asm__ __volatile__ ("stlrb %w1, %0" \
	85	: "=Q" (*(p)) \
	86	: "r" ((__u8 )__u.__c) \
d78a16c2 MD	87	: "memory"); \
	88	break; \
	89	case 2: \
18ca65e0 MD	90	__asm__ __volatile__ ("stlrh %w1, %0" \
	91	: "=Q" (*(p)) \
	92	: "r" ((__u16 )__u.__c) \
d78a16c2 MD	93	: "memory"); \
	94	break; \
	95	case 4: \
18ca65e0 MD	96	__asm__ __volatile__ ("stlr %w1, %0" \
	97	: "=Q" (*(p)) \
	98	: "r" ((__u32 )__u.__c) \
d78a16c2 MD	99	: "memory"); \
	100	break; \
	101	case 8: \
18ca65e0 MD	102	__asm__ __volatile__ ("stlr %1, %0" \
	103	: "=Q" (*(p)) \
	104	: "r" ((__u64 )__u.__c) \
d78a16c2 MD	105	: "memory"); \
	106	break; \
	107	} \
	108	} while (0)
	109
9ed48921	110	#define RSEQ_ASM_U64_PTR(x) ".quad " x
0f986786	111	#define RSEQ_ASM_U32(x) ".long " x
9ed48921	112
21b58a3b	113	/* Temporary scratch registers. */
d78a16c2 MD	114	#define RSEQ_ASM_TMP_REG32 "w15"
	115	#define RSEQ_ASM_TMP_REG "x15"
	116	#define RSEQ_ASM_TMP_REG_2 "x14"
	117
ed21bf6d MD	118	/* Common architecture support macros. */
ed21bf6d MD	119	#include "rseq/arch/generic/common.h"
90d9876e	120
21b58a3b MD	121	/*
	122	* Define a critical section abort handler.
	123	*
	124	* @label:
	125	* Local label to the abort handler.
	126	* @teardown:
	127	* Sequence of instructions to run on abort.
	128	* @abort_label:
	129	* C label to jump to at the end of the sequence.
	130	*/
ebd27573	131	#define RSEQ_ASM_DEFINE_ABORT(label, teardown, abort_label) \
d78a16c2	132	" b 222f\n" \
8b7c64f7	133	" .inst " __rseq_str(RSEQ_SIG_CODE) "\n" \
d78a16c2	134	__rseq_str(label) ":\n" \
ebd27573	135	teardown \
d78a16c2 MD	136	" b %l[" __rseq_str(abort_label) "]\n" \
	137	"222:\n"
	138
21b58a3b MD	139	/* Jump to local label @label when @cpu_id != @current_cpu_id. */
	140	#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \
	141	RSEQ_INJECT_ASM(1) \
	142	" adrp " RSEQ_ASM_TMP_REG ", " __rseq_str(cs_label) "\n" \
	143	" add " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
	144	", :lo12:" __rseq_str(cs_label) "\n" \
	145	" str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(rseq_cs) "]\n" \
	146	__rseq_str(label) ":\n"
	147
	148	/* Store @value to address @var. */
d78a16c2 MD	149	#define RSEQ_ASM_OP_STORE(value, var) \
	150	" str %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n"
	151
21b58a3b	152	/* Store-release @value to address @var. */
d78a16c2 MD	153	#define RSEQ_ASM_OP_STORE_RELEASE(value, var) \
	154	" stlr %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n"
	155
21b58a3b MD	156	/*
	157	* End-of-sequence store of @value to address @var. Emit
	158	* @post_commit_label label after the store instruction.
	159	*/
d78a16c2 MD	160	#define RSEQ_ASM_OP_FINAL_STORE(value, var, post_commit_label) \
	161	RSEQ_ASM_OP_STORE(value, var) \
	162	__rseq_str(post_commit_label) ":\n"
	163
21b58a3b MD	164	/*
	165	* End-of-sequence store-release of @value to address @var. Emit
	166	* @post_commit_label label after the store instruction.
	167	*/
d78a16c2 MD	168	#define RSEQ_ASM_OP_FINAL_STORE_RELEASE(value, var, post_commit_label) \
	169	RSEQ_ASM_OP_STORE_RELEASE(value, var) \
	170	__rseq_str(post_commit_label) ":\n"
	171
21b58a3b	172	/* Jump to local label @label when @var != @expect. */
769ec9a5	173	#define RSEQ_ASM_OP_CBNE(var, expect, label) \
d78a16c2 MD	174	" ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \
	175	" sub " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
	176	", %[" __rseq_str(expect) "]\n" \
	177	" cbnz " RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n"
	178
21b58a3b MD	179	/*
	180	* Jump to local label @label when @var != @expect (32-bit register
	181	* comparison).
	182	*/
769ec9a5	183	#define RSEQ_ASM_OP_CBNE32(var, expect, label) \
d78a16c2 MD	184	" ldr " RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n" \
	185	" sub " RSEQ_ASM_TMP_REG32 ", " RSEQ_ASM_TMP_REG32 \
	186	", %w[" __rseq_str(expect) "]\n" \
	187	" cbnz " RSEQ_ASM_TMP_REG32 ", " __rseq_str(label) "\n"
	188
21b58a3b	189	/* Jump to local label @label when @var == @expect. */
769ec9a5	190	#define RSEQ_ASM_OP_CBEQ(var, expect, label) \
d78a16c2 MD	191	" ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \
	192	" sub " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
	193	", %[" __rseq_str(expect) "]\n" \
	194	" cbz " RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n"
	195
21b58a3b	196	/* Jump to local label @label when @cpu_id != @current_cpu_id. */
769ec9a5	197	#define RSEQ_ASM_CBNE_CPU_ID(cpu_id, current_cpu_id, label) \
d78a16c2	198	RSEQ_INJECT_ASM(2) \
769ec9a5	199	RSEQ_ASM_OP_CBNE32(current_cpu_id, cpu_id, label)
d78a16c2	200
21b58a3b	201	/* Load @var into temporary register. */
d78a16c2 MD	202	#define RSEQ_ASM_OP_R_LOAD(var) \
	203	" ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"
	204
21b58a3b	205	/* Store from temporary register into @var. */
d78a16c2 MD	206	#define RSEQ_ASM_OP_R_STORE(var) \
	207	" str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"
	208
21b58a3b	209	/* Load from address in temporary register+@offset into temporary register. */
d78a16c2 MD	210	#define RSEQ_ASM_OP_R_LOAD_OFF(offset) \
	211	" ldr " RSEQ_ASM_TMP_REG ", [" RSEQ_ASM_TMP_REG \
	212	", %[" __rseq_str(offset) "]]\n"
	213
21b58a3b	214	/* Add @count to temporary register. */
d78a16c2 MD	215	#define RSEQ_ASM_OP_R_ADD(count) \
	216	" add " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
	217	", %[" __rseq_str(count) "]\n"
	218
21b58a3b MD	219	/*
	220	* End-of-sequence store of temporary register to address @var. Emit
	221	* @post_commit_label label after the store instruction.
	222	*/
d78a16c2 MD	223	#define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label) \
	224	" str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \
	225	__rseq_str(post_commit_label) ":\n"
	226
21b58a3b MD	227	/*
	228	* Copy @len bytes from @src to @dst. This is an inefficient bytewise
	229	* copy and could be improved in the future.
	230	*/
6020ff66	231	#define RSEQ_ASM_OP_R_BYTEWISE_MEMCPY(dst, src, len) \
d78a16c2 MD	232	" cbz %[" __rseq_str(len) "], 333f\n" \
	233	" mov " RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(len) "]\n" \
	234	"222: sub " RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", #1\n" \
	235	" ldrb " RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(src) "]" \
	236	", " RSEQ_ASM_TMP_REG_2 "]\n" \
	237	" strb " RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(dst) "]" \
	238	", " RSEQ_ASM_TMP_REG_2 "]\n" \
	239	" cbnz " RSEQ_ASM_TMP_REG_2 ", 222b\n" \
	240	"333:\n"
	241
a98a3b6d	242	/* Per-cpu-id indexing. */
d78a16c2	243
abf9e855	244	#define RSEQ_TEMPLATE_INDEX_CPU_ID
a98a3b6d	245	#define RSEQ_TEMPLATE_MO_RELAXED
44ec21eb	246	#include "rseq/arch/aarch64/bits.h"
a98a3b6d	247	#undef RSEQ_TEMPLATE_MO_RELAXED
d78a16c2	248
a98a3b6d	249	#define RSEQ_TEMPLATE_MO_RELEASE
44ec21eb	250	#include "rseq/arch/aarch64/bits.h"
a98a3b6d	251	#undef RSEQ_TEMPLATE_MO_RELEASE
abf9e855	252	#undef RSEQ_TEMPLATE_INDEX_CPU_ID
a98a3b6d MD	253
	254	/* Per-mm-cid indexing. */
	255
abf9e855	256	#define RSEQ_TEMPLATE_INDEX_MM_CID
a98a3b6d	257	#define RSEQ_TEMPLATE_MO_RELAXED
44ec21eb	258	#include "rseq/arch/aarch64/bits.h"
a98a3b6d MD	259	#undef RSEQ_TEMPLATE_MO_RELAXED
	260
	261	#define RSEQ_TEMPLATE_MO_RELEASE
44ec21eb	262	#include "rseq/arch/aarch64/bits.h"
a98a3b6d	263	#undef RSEQ_TEMPLATE_MO_RELEASE
abf9e855	264	#undef RSEQ_TEMPLATE_INDEX_MM_CID
a98a3b6d	265
abf9e855	266	/* APIs which are not indexed. */
a98a3b6d	267
abf9e855	268	#define RSEQ_TEMPLATE_INDEX_NONE
a98a3b6d	269	#define RSEQ_TEMPLATE_MO_RELAXED
44ec21eb	270	#include "rseq/arch/aarch64/bits.h"
a98a3b6d	271	#undef RSEQ_TEMPLATE_MO_RELAXED
abf9e855	272	#undef RSEQ_TEMPLATE_INDEX_NONE