[librseq.git] / include / rseq / arch / ppc.h

/* SPDX-License-Identifier: MIT */
/* SPDX-FileCopyrightText: 2016-2024 Mathieu Desnoyers <mathieu.desnoyers@efficios.com> */
/* SPDX-FileCopyrightText: 2016-2018 Boqun Feng <boqun.feng@gmail.com> */

/*
 * rseq/arch/ppc.h
 */

#ifndef _RSEQ_RSEQ_H
#error "Never use <rseq/arch/ppc.h> directly; include <rseq/rseq.h> instead."
#endif

/*
 * RSEQ_ASM_*() macro helpers are internal to the librseq headers. Those
 * are not part of the public API.
 */

/*
 * RSEQ_SIG is used with the following trap instruction:
 *
 * powerpc-be:    0f e5 00 0b           twui   r5,11
 * powerpc64-le:  0b 00 e5 0f           twui   r5,11
 * powerpc64-be:  0f e5 00 0b           twui   r5,11
 */

#define RSEQ_SIG	0x0fe5000b

/*
 * Refer to the Linux kernel memory model (LKMM) for documentation of
 * the memory barriers.
 */

/* CPU memory barrier. */
#define rseq_smp_mb()		__asm__ __volatile__ ("sync"	::: "memory", "cc")
/* Only used internally in this header. */
#define __rseq_smp_lwsync()	__asm__ __volatile__ ("lwsync"	::: "memory", "cc")
/* CPU read memory barrier */
#define rseq_smp_rmb()		__rseq_smp_lwsync()
/* CPU write memory barrier */
#define rseq_smp_wmb()		__rseq_smp_lwsync()

/* Acquire: One-way permeable barrier. */
#define rseq_smp_load_acquire(p)					\
__extension__ ({							\
	rseq_unqual_scalar_typeof(*(p)) ____p1 = RSEQ_READ_ONCE(*(p));	\
	__rseq_smp_lwsync();						\
	____p1;								\
})

/* Acquire barrier after control dependency. */
#define rseq_smp_acquire__after_ctrl_dep()	__rseq_smp_lwsync()

/* Release: One-way permeable barrier. */
#define rseq_smp_store_release(p, v)					\
do {									\
	__rseq_smp_lwsync();						\
	RSEQ_WRITE_ONCE(*(p), v);					\
} while (0)

/*
 * Helper macros to define and access a variable of long integer type.
 * Only used internally in rseq headers.
 */
#ifdef RSEQ_ARCH_PPC64
# define RSEQ_ASM_STORE_LONG(arg)	"std%U[" __rseq_str(arg) "]%X[" __rseq_str(arg) "] "	/* To memory ("m" constraint) */
# define RSEQ_ASM_STORE_INT(arg)	"stw%U[" __rseq_str(arg) "]%X[" __rseq_str(arg) "] "	/* To memory ("m" constraint) */
# define RSEQ_ASM_LOAD_LONG(arg)	"ld%U[" __rseq_str(arg) "]%X[" __rseq_str(arg) "] "	/* From memory ("m" constraint) */
# define RSEQ_ASM_LOAD_INT(arg)		"lwz%U[" __rseq_str(arg) "]%X[" __rseq_str(arg) "] "	/* From memory ("m" constraint) */
# define RSEQ_ASM_LOADX_LONG		"ldx "							/* From base register ("b" constraint) */
# define RSEQ_ASM_CMP_LONG		"cmpd "							/* Register-to-register comparison */
# define RSEQ_ASM_CMP_LONG_INT		"cmpdi "						/* Register-to-immediate comparison */
#else
# define RSEQ_ASM_STORE_LONG(arg)	"stw%U[" __rseq_str(arg) "]%X[" __rseq_str(arg) "] "	/* To memory ("m" constraint) */
# define RSEQ_ASM_STORE_INT(arg)	RSEQ_ASM_STORE_LONG(arg)				/* To memory ("m" constraint) */
# define RSEQ_ASM_LOAD_LONG(arg)	"lwz%U[" __rseq_str(arg) "]%X[" __rseq_str(arg) "] "	/* From memory ("m" constraint) */
# define RSEQ_ASM_LOAD_INT(arg)		RSEQ_ASM_LOAD_LONG(arg)					/* From memory ("m" constraint) */
# define RSEQ_ASM_LOADX_LONG		"lwzx "							/* From base register ("b" constraint) */
# define RSEQ_ASM_CMP_LONG		"cmpw "							/* Register-to-register comparison */
# define RSEQ_ASM_CMP_LONG_INT		"cmpwi "						/* Register-to-immediate comparison */
#endif

/*
 * Helper macros to define a variable of pointer type stored in a 64-bit
 * integer. Only used internally in rseq headers.
 */
#ifdef RSEQ_ARCH_PPC64
# define RSEQ_ASM_U64_PTR(x)		".quad " x
#else
/* 32-bit only supported on big endian. */
# define RSEQ_ASM_U64_PTR(x)		".long 0x0, " x
#endif

#define RSEQ_ASM_U32(x)			".long " x

/* Common architecture support macros. */
#include "rseq/arch/generic/common.h"

/*
 * Define a critical section abort handler.
 *
 *  @label:
 *    Local label to the abort handler.
 *  @teardown:
 *    Sequence of instructions to run on abort.
 *  @abort_label:
 *    C label to jump to at the end of the sequence.
 */
#define RSEQ_ASM_DEFINE_ABORT(label, teardown, abort_label)			\
		".pushsection __rseq_failure, \"ax\"\n\t"			\
		RSEQ_ASM_U32(__rseq_str(RSEQ_SIG)) "\n\t"			\
		__rseq_str(label) ":\n\t"					\
		teardown							\
		"b %l[" __rseq_str(abort_label) "]\n\t"				\
		".popsection\n\t"

/*
 * Store the address of the critical section descriptor structure at
 * @cs_label into the @rseq_cs pointer and emit the label @label, which
 * is the beginning of the sequence of consecutive assembly instructions.
 *
 *  @label:
 *    Local label to the beginning of the sequence of consecutive assembly
 *    instructions.
 *  @cs_label:
 *    Source local label to the critical section descriptor structure.
 *  @rseq_cs:
 *    Destination pointer where to store the address of the critical
 *    section descriptor structure.
 */
#ifdef RSEQ_ARCH_PPC64
# define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs)			\
		RSEQ_INJECT_ASM(1)						\
		"lis %%r17, (" __rseq_str(cs_label) ")@highest\n\t"		\
		"ori %%r17, %%r17, (" __rseq_str(cs_label) ")@higher\n\t"	\
		"rldicr %%r17, %%r17, 32, 31\n\t"				\
		"oris %%r17, %%r17, (" __rseq_str(cs_label) ")@high\n\t"	\
		"ori %%r17, %%r17, (" __rseq_str(cs_label) ")@l\n\t"		\
		"std %%r17, %[" __rseq_str(rseq_cs) "]\n\t"			\
		__rseq_str(label) ":\n\t"
#else
# define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs)			\
		RSEQ_INJECT_ASM(1)						\
		"lis %%r17, (" __rseq_str(cs_label) ")@ha\n\t"			\
		"addi %%r17, %%r17, (" __rseq_str(cs_label) ")@l\n\t"		\
		RSEQ_ASM_STORE_INT(rseq_cs) "%%r17, %[" __rseq_str(rseq_cs) "]\n\t" \
		__rseq_str(label) ":\n\t"
#endif

/* Jump to local label @label when @cpu_id != @current_cpu_id. */
#define RSEQ_ASM_CBNE_CPU_ID(cpu_id, current_cpu_id, label)			\
		RSEQ_INJECT_ASM(2)						\
		RSEQ_ASM_LOAD_INT(current_cpu_id) "%%r17, %[" __rseq_str(current_cpu_id) "]\n\t" \
		"cmpw cr7, %[" __rseq_str(cpu_id) "], %%r17\n\t"		\
		"bne- cr7, " __rseq_str(label) "\n\t"

/*
 * RSEQ_ASM_OPs: asm operations for rseq. Only used internally by rseq headers.
 * 	RSEQ_ASM_OP_R_*: has hard-coded registers in it
 * 	RSEQ_ASM_OP_* (else): doesn't have hard-coded registers(unless cr7)
 */

/* Jump to local label @label when @var != @expect. */
#define RSEQ_ASM_OP_CBNE(var, expect, label)					\
		RSEQ_ASM_LOAD_LONG(var) "%%r17, %[" __rseq_str(var) "]\n\t"	\
		RSEQ_ASM_CMP_LONG "cr7, %%r17, %[" __rseq_str(expect) "]\n\t"	\
		"bne- cr7, " __rseq_str(label) "\n\t"

/* Jump to local label @label when @var == @expect. */
#define RSEQ_ASM_OP_CBEQ(var, expect, label)					\
		RSEQ_ASM_LOAD_LONG(var) "%%r17, %[" __rseq_str(var) "]\n\t"	\
		RSEQ_ASM_CMP_LONG "cr7, %%r17, %[" __rseq_str(expect) "]\n\t" \
		"beq- cr7, " __rseq_str(label) "\n\t"

/* Store @value to address @var. */
#define RSEQ_ASM_OP_STORE(value, var)						\
		RSEQ_ASM_STORE_LONG(var) "%[" __rseq_str(value) "], %[" __rseq_str(var) "]\n\t"

/* Load @var to r17 */
#define RSEQ_ASM_OP_R_LOAD(var)							\
		RSEQ_ASM_LOAD_LONG(var) "%%r17, %[" __rseq_str(var) "]\n\t"

/* Store r17 to @var */
#define RSEQ_ASM_OP_R_STORE(var)						\
		RSEQ_ASM_STORE_LONG(var) "%%r17, %[" __rseq_str(var) "]\n\t"

/* Add @count to r17 */
#define RSEQ_ASM_OP_R_ADD(count)						\
		"add %%r17, %[" __rseq_str(count) "], %%r17\n\t"

/* Load (r17 + voffp) to r17 */
#define RSEQ_ASM_OP_R_LOADX(voffp)						\
		RSEQ_ASM_LOADX_LONG "%%r17, %[" __rseq_str(voffp) "], %%r17\n\t"

/*
 * Copy @len bytes from @src to @dst. This is an inefficient bytewise
 * copy and could be improved in the future.
 */
#define RSEQ_ASM_OP_R_BYTEWISE_MEMCPY() \
		RSEQ_ASM_CMP_LONG_INT "%%r19, 0\n\t" \
		"beq 333f\n\t" \
		"addi %%r20, %%r20, -1\n\t" \
		"addi %%r21, %%r21, -1\n\t" \
		"222:\n\t" \
		"lbzu %%r18, 1(%%r20)\n\t" \
		"stbu %%r18, 1(%%r21)\n\t" \
		"addi %%r19, %%r19, -1\n\t" \
		RSEQ_ASM_CMP_LONG_INT "%%r19, 0\n\t" \
		"bne 222b\n\t" \
		"333:\n\t" \

/*
 * End-of-sequence store of r17 to address @var. Emit
 * @post_commit_label label after the store instruction.
 */
#define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label)			\
		RSEQ_ASM_STORE_LONG(var) "%%r17, %[" __rseq_str(var) "]\n\t"	\
		__rseq_str(post_commit_label) ":\n\t"

/*
 * End-of-sequence store of @value to address @var. Emit
 * @post_commit_label label after the store instruction.
 */
#define RSEQ_ASM_OP_FINAL_STORE(value, var, post_commit_label)			\
		RSEQ_ASM_STORE_LONG(var) "%[" __rseq_str(value) "], %[" __rseq_str(var) "]\n\t" \
		__rseq_str(post_commit_label) ":\n\t"

/* Per-cpu-id indexing. */

#define RSEQ_TEMPLATE_INDEX_CPU_ID
#define RSEQ_TEMPLATE_MO_RELAXED
#include "rseq/arch/ppc/bits.h"
#undef RSEQ_TEMPLATE_MO_RELAXED

#define RSEQ_TEMPLATE_MO_RELEASE
#include "rseq/arch/ppc/bits.h"
#undef RSEQ_TEMPLATE_MO_RELEASE
#undef RSEQ_TEMPLATE_INDEX_CPU_ID

/* Per-mm-cid indexing. */

#define RSEQ_TEMPLATE_INDEX_MM_CID
#define RSEQ_TEMPLATE_MO_RELAXED
#include "rseq/arch/ppc/bits.h"
#undef RSEQ_TEMPLATE_MO_RELAXED

#define RSEQ_TEMPLATE_MO_RELEASE
#include "rseq/arch/ppc/bits.h"
#undef RSEQ_TEMPLATE_MO_RELEASE
#undef RSEQ_TEMPLATE_INDEX_MM_CID

/* APIs which are not indexed. */

#define RSEQ_TEMPLATE_INDEX_NONE
#define RSEQ_TEMPLATE_MO_RELAXED
#include "rseq/arch/ppc/bits.h"
#undef RSEQ_TEMPLATE_MO_RELAXED
#undef RSEQ_TEMPLATE_INDEX_NONE
Commit	Line	Data
90702366	1	/* SPDX-License-Identifier: MIT */
5ad4f704	2	/* SPDX-FileCopyrightText: 2016-2024 Mathieu Desnoyers <mathieu.desnoyers@efficios.com> */
f2d7b530 MJ	3	/* SPDX-FileCopyrightText: 2016-2018 Boqun Feng <boqun.feng@gmail.com> */
f2d7b530 MJ	4
784b0012	5	/*
44ec21eb	6	* rseq/arch/ppc.h
784b0012 MD	7	*/
784b0012 MD	8
44ec21eb MJ	9	#ifndef _RSEQ_RSEQ_H
	10	#error "Never use <rseq/arch/ppc.h> directly; include <rseq/rseq.h> instead."
	11	#endif
	12
5ad4f704 MD	13	/*
	14	* RSEQ_ASM_*() macro helpers are internal to the librseq headers. Those
	15	* are not part of the public API.
	16	*/
	17
0158e666 MD	18	/*
	19	* RSEQ_SIG is used with the following trap instruction:
	20	*
	21	* powerpc-be: 0f e5 00 0b twui r5,11
	22	* powerpc64-le: 0b 00 e5 0f twui r5,11
	23	* powerpc64-be: 0f e5 00 0b twui r5,11
	24	*/
	25
	26	#define RSEQ_SIG 0x0fe5000b
784b0012	27
5ad4f704 MD	28	/*
	29	* Refer to the Linux kernel memory model (LKMM) for documentation of
	30	* the memory barriers.
	31	*/
784b0012	32
5ad4f704 MD	33	/* CPU memory barrier. */
	34	#define rseq_smp_mb() __asm__ __volatile__ ("sync" ::: "memory", "cc")
	35	/* Only used internally in this header. */
	36	#define __rseq_smp_lwsync() __asm__ __volatile__ ("lwsync" ::: "memory", "cc")
	37	/* CPU read memory barrier */
	38	#define rseq_smp_rmb() __rseq_smp_lwsync()
	39	/* CPU write memory barrier */
	40	#define rseq_smp_wmb() __rseq_smp_lwsync()
	41
	42	/* Acquire: One-way permeable barrier. */
784b0012 MD	43	#define rseq_smp_load_acquire(p) \
784b0012 MD	44	__extension__ ({ \
3664a718	45	rseq_unqual_scalar_typeof((p)) ____p1 = RSEQ_READ_ONCE((p)); \
5ad4f704	46	__rseq_smp_lwsync(); \
784b0012 MD	47	____p1; \
	48	})
	49
5ad4f704 MD	50	/* Acquire barrier after control dependency. */
5ad4f704 MD	51	#define rseq_smp_acquire__after_ctrl_dep() __rseq_smp_lwsync()
784b0012	52
5ad4f704	53	/* Release: One-way permeable barrier. */
784b0012 MD	54	#define rseq_smp_store_release(p, v) \
784b0012 MD	55	do { \
5ad4f704	56	__rseq_smp_lwsync(); \
826417f6	57	RSEQ_WRITE_ONCE(*(p), v); \
784b0012 MD	58	} while (0)
784b0012 MD	59
f6b00247 MD	60	/*
	61	* Helper macros to define and access a variable of long integer type.
	62	* Only used internally in rseq headers.
	63	*/
44ec21eb	64	#ifdef RSEQ_ARCH_PPC64
f6b00247 MD	65	# define RSEQ_ASM_STORE_LONG(arg) "std%U[" __rseq_str(arg) "]%X[" __rseq_str(arg) "] " /* To memory ("m" constraint) */
	66	# define RSEQ_ASM_STORE_INT(arg) "stw%U[" __rseq_str(arg) "]%X[" __rseq_str(arg) "] " /* To memory ("m" constraint) */
	67	# define RSEQ_ASM_LOAD_LONG(arg) "ld%U[" __rseq_str(arg) "]%X[" __rseq_str(arg) "] " /* From memory ("m" constraint) */
	68	# define RSEQ_ASM_LOAD_INT(arg) "lwz%U[" __rseq_str(arg) "]%X[" __rseq_str(arg) "] " /* From memory ("m" constraint) */
	69	# define RSEQ_ASM_LOADX_LONG "ldx " /* From base register ("b" constraint) */
	70	# define RSEQ_ASM_CMP_LONG "cmpd " /* Register-to-register comparison */
	71	# define RSEQ_ASM_CMP_LONG_INT "cmpdi " /* Register-to-immediate comparison */
	72	#else
	73	# define RSEQ_ASM_STORE_LONG(arg) "stw%U[" __rseq_str(arg) "]%X[" __rseq_str(arg) "] " /* To memory ("m" constraint) */
	74	# define RSEQ_ASM_STORE_INT(arg) RSEQ_ASM_STORE_LONG(arg) /* To memory ("m" constraint) */
	75	# define RSEQ_ASM_LOAD_LONG(arg) "lwz%U[" __rseq_str(arg) "]%X[" __rseq_str(arg) "] " /* From memory ("m" constraint) */
	76	# define RSEQ_ASM_LOAD_INT(arg) RSEQ_ASM_LOAD_LONG(arg) /* From memory ("m" constraint) */
	77	# define RSEQ_ASM_LOADX_LONG "lwzx " /* From base register ("b" constraint) */
	78	# define RSEQ_ASM_CMP_LONG "cmpw " /* Register-to-register comparison */
	79	# define RSEQ_ASM_CMP_LONG_INT "cmpwi " /* Register-to-immediate comparison */
	80	#endif
784b0012	81
f6b00247 MD	82	/*
	83	* Helper macros to define a variable of pointer type stored in a 64-bit
	84	* integer. Only used internally in rseq headers.
	85	*/
	86	#ifdef RSEQ_ARCH_PPC64
	87	# define RSEQ_ASM_U64_PTR(x) ".quad " x
	88	#else
	89	/* 32-bit only supported on big endian. */
	90	# define RSEQ_ASM_U64_PTR(x) ".long 0x0, " x
	91	#endif
784b0012	92
d68304d1 MD	93	#define RSEQ_ASM_U32(x) ".long " x
d68304d1 MD	94
ed21bf6d MD	95	/* Common architecture support macros. */
	96	#include "rseq/arch/generic/common.h"
	97
	98	/*
	99	* Define a critical section abort handler.
	100	*
	101	* @label:
	102	* Local label to the abort handler.
	103	* @teardown:
	104	* Sequence of instructions to run on abort.
	105	* @abort_label:
	106	* C label to jump to at the end of the sequence.
	107	*/
	108	#define RSEQ_ASM_DEFINE_ABORT(label, teardown, abort_label) \
	109	".pushsection __rseq_failure, \"ax\"\n\t" \
	110	RSEQ_ASM_U32(__rseq_str(RSEQ_SIG)) "\n\t" \
	111	__rseq_str(label) ":\n\t" \
	112	teardown \
	113	"b %l[" __rseq_str(abort_label) "]\n\t" \
	114	".popsection\n\t"
	115
5ad4f704 MD	116	/*
	117	* Store the address of the critical section descriptor structure at
	118	* @cs_label into the @rseq_cs pointer and emit the label @label, which
	119	* is the beginning of the sequence of consecutive assembly instructions.
	120	*
	121	* @label:
	122	* Local label to the beginning of the sequence of consecutive assembly
	123	* instructions.
	124	* @cs_label:
	125	* Source local label to the critical section descriptor structure.
	126	* @rseq_cs:
	127	* Destination pointer where to store the address of the critical
	128	* section descriptor structure.
	129	*/
f6b00247 MD	130	#ifdef RSEQ_ARCH_PPC64
f6b00247 MD	131	# define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \
784b0012 MD	132	RSEQ_INJECT_ASM(1) \
	133	"lis %%r17, (" __rseq_str(cs_label) ")@highest\n\t" \
	134	"ori %%r17, %%r17, (" __rseq_str(cs_label) ")@higher\n\t" \
	135	"rldicr %%r17, %%r17, 32, 31\n\t" \
	136	"oris %%r17, %%r17, (" __rseq_str(cs_label) ")@high\n\t" \
	137	"ori %%r17, %%r17, (" __rseq_str(cs_label) ")@l\n\t" \
	138	"std %%r17, %[" __rseq_str(rseq_cs) "]\n\t" \
	139	__rseq_str(label) ":\n\t"
f6b00247 MD	140	#else
	141	# define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \
	142	RSEQ_INJECT_ASM(1) \
	143	"lis %%r17, (" __rseq_str(cs_label) ")@ha\n\t" \
	144	"addi %%r17, %%r17, (" __rseq_str(cs_label) ")@l\n\t" \
	145	RSEQ_ASM_STORE_INT(rseq_cs) "%%r17, %[" __rseq_str(rseq_cs) "]\n\t" \
	146	__rseq_str(label) ":\n\t"
	147	#endif
784b0012	148
5ad4f704 MD	149	/* Jump to local label @label when @cpu_id != @current_cpu_id. */
	150	#define RSEQ_ASM_CBNE_CPU_ID(cpu_id, current_cpu_id, label) \
	151	RSEQ_INJECT_ASM(2) \
	152	RSEQ_ASM_LOAD_INT(current_cpu_id) "%%r17, %[" __rseq_str(current_cpu_id) "]\n\t" \
	153	"cmpw cr7, %[" __rseq_str(cpu_id) "], %%r17\n\t" \
	154	"bne- cr7, " __rseq_str(label) "\n\t"
	155
784b0012	156	/*
5ad4f704 MD	157	* RSEQ_ASM_OPs: asm operations for rseq. Only used internally by rseq headers.
	158	* RSEQ_ASM_OP_R_*: has hard-coded registers in it
	159	* RSEQ_ASM_OP_* (else): doesn't have hard-coded registers(unless cr7)
784b0012	160	*/
5ad4f704 MD	161
5ad4f704 MD	162	/* Jump to local label @label when @var != @expect. */
769ec9a5	163	#define RSEQ_ASM_OP_CBNE(var, expect, label) \
d1d63a2d MD	164	RSEQ_ASM_LOAD_LONG(var) "%%r17, %[" __rseq_str(var) "]\n\t" \
d1d63a2d MD	165	RSEQ_ASM_CMP_LONG "cr7, %%r17, %[" __rseq_str(expect) "]\n\t" \
784b0012 MD	166	"bne- cr7, " __rseq_str(label) "\n\t"
784b0012 MD	167
5ad4f704 MD	168	/* Jump to local label @label when @var == @expect. */
5ad4f704 MD	169	#define RSEQ_ASM_OP_CBEQ(var, expect, label) \
d1d63a2d	170	RSEQ_ASM_LOAD_LONG(var) "%%r17, %[" __rseq_str(var) "]\n\t" \
5ad4f704	171	RSEQ_ASM_CMP_LONG "cr7, %%r17, %[" __rseq_str(expect) "]\n\t" \
784b0012 MD	172	"beq- cr7, " __rseq_str(label) "\n\t"
784b0012 MD	173
5ad4f704	174	/* Store @value to address @var. */
784b0012	175	#define RSEQ_ASM_OP_STORE(value, var) \
d1d63a2d	176	RSEQ_ASM_STORE_LONG(var) "%[" __rseq_str(value) "], %[" __rseq_str(var) "]\n\t"
784b0012 MD	177
	178	/* Load @var to r17 */
	179	#define RSEQ_ASM_OP_R_LOAD(var) \
d1d63a2d	180	RSEQ_ASM_LOAD_LONG(var) "%%r17, %[" __rseq_str(var) "]\n\t"
784b0012 MD	181
	182	/* Store r17 to @var */
	183	#define RSEQ_ASM_OP_R_STORE(var) \
d1d63a2d	184	RSEQ_ASM_STORE_LONG(var) "%%r17, %[" __rseq_str(var) "]\n\t"
784b0012 MD	185
	186	/* Add @count to r17 */
	187	#define RSEQ_ASM_OP_R_ADD(count) \
	188	"add %%r17, %[" __rseq_str(count) "], %%r17\n\t"
	189
	190	/* Load (r17 + voffp) to r17 */
	191	#define RSEQ_ASM_OP_R_LOADX(voffp) \
d1d63a2d	192	RSEQ_ASM_LOADX_LONG "%%r17, %[" __rseq_str(voffp) "], %%r17\n\t"
784b0012	193
5ad4f704 MD	194	/*
	195	* Copy @len bytes from @src to @dst. This is an inefficient bytewise
	196	* copy and could be improved in the future.
	197	*/
08130179	198	#define RSEQ_ASM_OP_R_BYTEWISE_MEMCPY() \
d1d63a2d	199	RSEQ_ASM_CMP_LONG_INT "%%r19, 0\n\t" \
784b0012 MD	200	"beq 333f\n\t" \
	201	"addi %%r20, %%r20, -1\n\t" \
	202	"addi %%r21, %%r21, -1\n\t" \
	203	"222:\n\t" \
	204	"lbzu %%r18, 1(%%r20)\n\t" \
	205	"stbu %%r18, 1(%%r21)\n\t" \
	206	"addi %%r19, %%r19, -1\n\t" \
d1d63a2d	207	RSEQ_ASM_CMP_LONG_INT "%%r19, 0\n\t" \
784b0012 MD	208	"bne 222b\n\t" \
	209	"333:\n\t" \
	210
5ad4f704 MD	211	/*
	212	* End-of-sequence store of r17 to address @var. Emit
	213	* @post_commit_label label after the store instruction.
	214	*/
784b0012	215	#define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label) \
d1d63a2d	216	RSEQ_ASM_STORE_LONG(var) "%%r17, %[" __rseq_str(var) "]\n\t" \
784b0012 MD	217	__rseq_str(post_commit_label) ":\n\t"
784b0012 MD	218
5ad4f704 MD	219	/*
	220	* End-of-sequence store of @value to address @var. Emit
	221	* @post_commit_label label after the store instruction.
	222	*/
784b0012	223	#define RSEQ_ASM_OP_FINAL_STORE(value, var, post_commit_label) \
d1d63a2d	224	RSEQ_ASM_STORE_LONG(var) "%[" __rseq_str(value) "], %[" __rseq_str(var) "]\n\t" \
784b0012 MD	225	__rseq_str(post_commit_label) ":\n\t"
784b0012 MD	226
8fad586a MD	227	/* Per-cpu-id indexing. */
8fad586a MD	228
abf9e855	229	#define RSEQ_TEMPLATE_INDEX_CPU_ID
8fad586a	230	#define RSEQ_TEMPLATE_MO_RELAXED
44ec21eb	231	#include "rseq/arch/ppc/bits.h"
8fad586a MD	232	#undef RSEQ_TEMPLATE_MO_RELAXED
	233
	234	#define RSEQ_TEMPLATE_MO_RELEASE
44ec21eb	235	#include "rseq/arch/ppc/bits.h"
8fad586a	236	#undef RSEQ_TEMPLATE_MO_RELEASE
abf9e855	237	#undef RSEQ_TEMPLATE_INDEX_CPU_ID
8fad586a MD	238
	239	/* Per-mm-cid indexing. */
	240
abf9e855	241	#define RSEQ_TEMPLATE_INDEX_MM_CID
8fad586a	242	#define RSEQ_TEMPLATE_MO_RELAXED
44ec21eb	243	#include "rseq/arch/ppc/bits.h"
8fad586a MD	244	#undef RSEQ_TEMPLATE_MO_RELAXED
	245
	246	#define RSEQ_TEMPLATE_MO_RELEASE
44ec21eb	247	#include "rseq/arch/ppc/bits.h"
8fad586a	248	#undef RSEQ_TEMPLATE_MO_RELEASE
abf9e855	249	#undef RSEQ_TEMPLATE_INDEX_MM_CID
8fad586a	250
abf9e855	251	/* APIs which are not indexed. */
8fad586a	252
abf9e855	253	#define RSEQ_TEMPLATE_INDEX_NONE
8fad586a	254	#define RSEQ_TEMPLATE_MO_RELAXED
44ec21eb	255	#include "rseq/arch/ppc/bits.h"
8fad586a	256	#undef RSEQ_TEMPLATE_MO_RELAXED
abf9e855	257	#undef RSEQ_TEMPLATE_INDEX_NONE