[librseq.git] / include / rseq / rseq-arm64.h

/* SPDX-License-Identifier: MIT */
/* SPDX-FileCopyrightText: 2016-2018 Mathieu Desnoyers <mathieu.desnoyers@efficios.com> */
/* SPDX-FileCopyrightText: 2018 Will Deacon <will.deacon@arm.com> */

/*
 * rseq-arm64.h
 */

/*
 * aarch64 -mbig-endian generates mixed endianness code vs data:
 * little-endian code and big-endian data. Ensure the RSEQ_SIG signature
 * matches code endianness.
 */
#define RSEQ_SIG_CODE	0xd428bc00	/* BRK #0x45E0.  */

#ifdef __AARCH64EB__
#define RSEQ_SIG_DATA	0x00bc28d4	/* BRK #0x45E0.  */
#else
#define RSEQ_SIG_DATA	RSEQ_SIG_CODE
#endif

#define RSEQ_SIG	RSEQ_SIG_DATA

#define rseq_smp_mb()	__asm__ __volatile__ ("dmb ish" ::: "memory")
#define rseq_smp_rmb()	__asm__ __volatile__ ("dmb ishld" ::: "memory")
#define rseq_smp_wmb()	__asm__ __volatile__ ("dmb ishst" ::: "memory")

#define rseq_smp_load_acquire(p)						\
__extension__ ({								\
	union { rseq_unqual_scalar_typeof(*(p)) __val; char __c[sizeof(*(p))]; } __u; \
	switch (sizeof(*(p))) {							\
	case 1:									\
		__asm__ __volatile__ ("ldarb %w0, %1"				\
			: "=r" (*(__u8 *)__u.__c)				\
			: "Q" (*(p)) : "memory");				\
		break;								\
	case 2:									\
		__asm__ __volatile__ ("ldarh %w0, %1"				\
			: "=r" (*(__u16 *)__u.__c)				\
			: "Q" (*(p)) : "memory");				\
		break;								\
	case 4:									\
		__asm__ __volatile__ ("ldar %w0, %1"				\
			: "=r" (*(__u32 *)__u.__c)				\
			: "Q" (*(p)) : "memory");				\
		break;								\
	case 8:									\
		__asm__ __volatile__ ("ldar %0, %1"				\
			: "=r" (*(__u64 *)__u.__c)				\
			: "Q" (*(p)) : "memory");				\
		break;								\
	}									\
	(rseq_unqual_scalar_typeof(*(p)))__u.__val;				\
})

#define rseq_smp_acquire__after_ctrl_dep()	rseq_smp_rmb()

#define rseq_smp_store_release(p, v)						\
do {										\
	union { rseq_unqual_scalar_typeof(*(p)) __val; char __c[sizeof(*(p))]; } __u = \
		{ .__val = (rseq_unqual_scalar_typeof(*(p))) (v) };		\
	switch (sizeof(*(p))) {							\
	case 1:									\
		__asm__ __volatile__ ("stlrb %w1, %0"				\
				: "=Q" (*(p))					\
				: "r" (*(__u8 *)__u.__c)			\
				: "memory");					\
		break;								\
	case 2:									\
		__asm__ __volatile__ ("stlrh %w1, %0"				\
				: "=Q" (*(p))					\
				: "r" (*(__u16 *)__u.__c)			\
				: "memory");					\
		break;								\
	case 4:									\
		__asm__ __volatile__ ("stlr %w1, %0"				\
				: "=Q" (*(p))					\
				: "r" (*(__u32 *)__u.__c)			\
				: "memory");					\
		break;								\
	case 8:									\
		__asm__ __volatile__ ("stlr %1, %0"				\
				: "=Q" (*(p))					\
				: "r" (*(__u64 *)__u.__c)			\
				: "memory");					\
		break;								\
	}									\
} while (0)

#define RSEQ_ASM_TMP_REG32	"w15"
#define RSEQ_ASM_TMP_REG	"x15"
#define RSEQ_ASM_TMP_REG_2	"x14"

#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip,		\
				post_commit_offset, abort_ip)			\
	"	.pushsection	__rseq_cs, \"aw\"\n"				\
	"	.balign	32\n"							\
	__rseq_str(label) ":\n"							\
	"	.long	" __rseq_str(version) ", " __rseq_str(flags) "\n"	\
	"	.quad	" __rseq_str(start_ip) ", "				\
			  __rseq_str(post_commit_offset) ", "			\
			  __rseq_str(abort_ip) "\n"				\
	"	.popsection\n\t"						\
	"	.pushsection __rseq_cs_ptr_array, \"aw\"\n"				\
	"	.quad " __rseq_str(label) "b\n"					\
	"	.popsection\n"

#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip)	\
	__RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip,			\
				(post_commit_ip - start_ip), abort_ip)

/*
 * Exit points of a rseq critical section consist of all instructions outside
 * of the critical section where a critical section can either branch to or
 * reach through the normal course of its execution. The abort IP and the
 * post-commit IP are already part of the __rseq_cs section and should not be
 * explicitly defined as additional exit points. Knowing all exit points is
 * useful to assist debuggers stepping over the critical section.
 */
#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip)				\
	"	.pushsection __rseq_exit_point_array, \"aw\"\n"			\
	"	.quad " __rseq_str(start_ip) ", " __rseq_str(exit_ip) "\n"	\
	"	.popsection\n"

#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs)			\
	RSEQ_INJECT_ASM(1)							\
	"	adrp	" RSEQ_ASM_TMP_REG ", " __rseq_str(cs_label) "\n"	\
	"	add	" RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG		\
			", :lo12:" __rseq_str(cs_label) "\n"			\
	"	str	" RSEQ_ASM_TMP_REG ", %[" __rseq_str(rseq_cs) "]\n"	\
	__rseq_str(label) ":\n"

#define RSEQ_ASM_DEFINE_ABORT(label, teardown, abort_label)			\
	"	b	222f\n"							\
	"	.inst 	"	__rseq_str(RSEQ_SIG_CODE) "\n"			\
	__rseq_str(label) ":\n"							\
	teardown								\
	"	b	%l[" __rseq_str(abort_label) "]\n"			\
	"222:\n"

#define RSEQ_ASM_OP_STORE(value, var)						\
	"	str	%[" __rseq_str(value) "], %[" __rseq_str(var) "]\n"

#define RSEQ_ASM_OP_STORE_RELEASE(value, var)					\
	"	stlr	%[" __rseq_str(value) "], %[" __rseq_str(var) "]\n"

#define RSEQ_ASM_OP_FINAL_STORE(value, var, post_commit_label)			\
	RSEQ_ASM_OP_STORE(value, var)						\
	__rseq_str(post_commit_label) ":\n"

#define RSEQ_ASM_OP_FINAL_STORE_RELEASE(value, var, post_commit_label)		\
	RSEQ_ASM_OP_STORE_RELEASE(value, var)					\
	__rseq_str(post_commit_label) ":\n"

#define RSEQ_ASM_OP_CBNE(var, expect, label)					\
	"	ldr	" RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"		\
	"	sub	" RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG		\
			", %[" __rseq_str(expect) "]\n"				\
	"	cbnz	" RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n"

#define RSEQ_ASM_OP_CBNE32(var, expect, label)					\
	"	ldr	" RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n"	\
	"	sub	" RSEQ_ASM_TMP_REG32 ", " RSEQ_ASM_TMP_REG32		\
			", %w[" __rseq_str(expect) "]\n"			\
	"	cbnz	" RSEQ_ASM_TMP_REG32 ", " __rseq_str(label) "\n"

#define RSEQ_ASM_OP_CBEQ(var, expect, label)					\
	"	ldr	" RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"		\
	"	sub	" RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG		\
			", %[" __rseq_str(expect) "]\n"				\
	"	cbz	" RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n"

#define RSEQ_ASM_CBNE_CPU_ID(cpu_id, current_cpu_id, label)			\
	RSEQ_INJECT_ASM(2)							\
	RSEQ_ASM_OP_CBNE32(current_cpu_id, cpu_id, label)

#define RSEQ_ASM_OP_R_LOAD(var)							\
	"	ldr	" RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"

#define RSEQ_ASM_OP_R_STORE(var)						\
	"	str	" RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"

#define RSEQ_ASM_OP_R_LOAD_OFF(offset)						\
	"	ldr	" RSEQ_ASM_TMP_REG ", [" RSEQ_ASM_TMP_REG		\
			", %[" __rseq_str(offset) "]]\n"

#define RSEQ_ASM_OP_R_ADD(count)						\
	"	add	" RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG		\
			", %[" __rseq_str(count) "]\n"

#define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label)			\
	"	str	" RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"		\
	__rseq_str(post_commit_label) ":\n"

#define RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len)					\
	"	cbz	%[" __rseq_str(len) "], 333f\n"				\
	"	mov	" RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(len) "]\n"	\
	"222:	sub	" RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", #1\n"	\
	"	ldrb	" RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(src) "]"	\
			", " RSEQ_ASM_TMP_REG_2 "]\n"				\
	"	strb	" RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(dst) "]"	\
			", " RSEQ_ASM_TMP_REG_2 "]\n"				\
	"	cbnz	" RSEQ_ASM_TMP_REG_2 ", 222b\n"				\
	"333:\n"

/* Per-cpu-id indexing. */

#define RSEQ_TEMPLATE_CPU_ID
#define RSEQ_TEMPLATE_MO_RELAXED
#include "rseq-arm64-bits.h"
#undef RSEQ_TEMPLATE_MO_RELAXED

#define RSEQ_TEMPLATE_MO_RELEASE
#include "rseq-arm64-bits.h"
#undef RSEQ_TEMPLATE_MO_RELEASE
#undef RSEQ_TEMPLATE_CPU_ID

/* Per-mm-cid indexing. */

#define RSEQ_TEMPLATE_MM_CID
#define RSEQ_TEMPLATE_MO_RELAXED
#include "rseq-arm64-bits.h"
#undef RSEQ_TEMPLATE_MO_RELAXED

#define RSEQ_TEMPLATE_MO_RELEASE
#include "rseq-arm64-bits.h"
#undef RSEQ_TEMPLATE_MO_RELEASE
#undef RSEQ_TEMPLATE_MM_CID

/* APIs which are not based on cpu ids. */

#define RSEQ_TEMPLATE_CPU_ID_NONE
#define RSEQ_TEMPLATE_MO_RELAXED
#include "rseq-arm64-bits.h"
#undef RSEQ_TEMPLATE_MO_RELAXED
#undef RSEQ_TEMPLATE_CPU_ID_NONE
Commit	Line	Data
90702366	1	/* SPDX-License-Identifier: MIT */
f2d7b530 MJ	2	/* SPDX-FileCopyrightText: 2016-2018 Mathieu Desnoyers <mathieu.desnoyers@efficios.com> */
	3	/* SPDX-FileCopyrightText: 2018 Will Deacon <will.deacon@arm.com> */
	4
d78a16c2 MD	5	/*
d78a16c2 MD	6	* rseq-arm64.h
d78a16c2 MD	7	*/
d78a16c2 MD	8
8b7c64f7 MD	9	/*
	10	* aarch64 -mbig-endian generates mixed endianness code vs data:
	11	* little-endian code and big-endian data. Ensure the RSEQ_SIG signature
	12	* matches code endianness.
	13	*/
	14	#define RSEQ_SIG_CODE 0xd428bc00 /* BRK #0x45E0. */
	15
	16	#ifdef __AARCH64EB__
	17	#define RSEQ_SIG_DATA 0x00bc28d4 /* BRK #0x45E0. */
	18	#else
	19	#define RSEQ_SIG_DATA RSEQ_SIG_CODE
	20	#endif
	21
	22	#define RSEQ_SIG RSEQ_SIG_DATA
d78a16c2 MD	23
	24	#define rseq_smp_mb() __asm__ __volatile__ ("dmb ish" ::: "memory")
	25	#define rseq_smp_rmb() __asm__ __volatile__ ("dmb ishld" ::: "memory")
	26	#define rseq_smp_wmb() __asm__ __volatile__ ("dmb ishst" ::: "memory")
	27
	28	#define rseq_smp_load_acquire(p) \
	29	__extension__ ({ \
18ca65e0 MD	30	union { rseq_unqual_scalar_typeof((p)) __val; char __c[sizeof((p))]; } __u; \
18ca65e0 MD	31	switch (sizeof(*(p))) { \
d78a16c2	32	case 1: \
18ca65e0 MD	33	__asm__ __volatile__ ("ldarb %w0, %1" \
	34	: "=r" ((__u8 )__u.__c) \
	35	: "Q" (*(p)) : "memory"); \
d78a16c2 MD	36	break; \
d78a16c2 MD	37	case 2: \
18ca65e0 MD	38	__asm__ __volatile__ ("ldarh %w0, %1" \
	39	: "=r" ((__u16 )__u.__c) \
	40	: "Q" (*(p)) : "memory"); \
d78a16c2 MD	41	break; \
d78a16c2 MD	42	case 4: \
18ca65e0 MD	43	__asm__ __volatile__ ("ldar %w0, %1" \
	44	: "=r" ((__u32 )__u.__c) \
	45	: "Q" (*(p)) : "memory"); \
d78a16c2 MD	46	break; \
d78a16c2 MD	47	case 8: \
18ca65e0 MD	48	__asm__ __volatile__ ("ldar %0, %1" \
	49	: "=r" ((__u64 )__u.__c) \
	50	: "Q" (*(p)) : "memory"); \
d78a16c2 MD	51	break; \
d78a16c2 MD	52	} \
0aac367c	53	(rseq_unqual_scalar_typeof(*(p)))__u.__val; \
d78a16c2 MD	54	})
	55
	56	#define rseq_smp_acquire__after_ctrl_dep() rseq_smp_rmb()
	57
	58	#define rseq_smp_store_release(p, v) \
	59	do { \
18ca65e0 MD	60	union { rseq_unqual_scalar_typeof((p)) __val; char __c[sizeof((p))]; } __u = \
	61	{ .__val = (rseq_unqual_scalar_typeof(*(p))) (v) }; \
	62	switch (sizeof(*(p))) { \
d78a16c2	63	case 1: \
18ca65e0 MD	64	__asm__ __volatile__ ("stlrb %w1, %0" \
	65	: "=Q" (*(p)) \
	66	: "r" ((__u8 )__u.__c) \
d78a16c2 MD	67	: "memory"); \
	68	break; \
	69	case 2: \
18ca65e0 MD	70	__asm__ __volatile__ ("stlrh %w1, %0" \
	71	: "=Q" (*(p)) \
	72	: "r" ((__u16 )__u.__c) \
d78a16c2 MD	73	: "memory"); \
	74	break; \
	75	case 4: \
18ca65e0 MD	76	__asm__ __volatile__ ("stlr %w1, %0" \
	77	: "=Q" (*(p)) \
	78	: "r" ((__u32 )__u.__c) \
d78a16c2 MD	79	: "memory"); \
	80	break; \
	81	case 8: \
18ca65e0 MD	82	__asm__ __volatile__ ("stlr %1, %0" \
	83	: "=Q" (*(p)) \
	84	: "r" ((__u64 )__u.__c) \
d78a16c2 MD	85	: "memory"); \
	86	break; \
	87	} \
	88	} while (0)
	89
d78a16c2 MD	90	#define RSEQ_ASM_TMP_REG32 "w15"
	91	#define RSEQ_ASM_TMP_REG "x15"
	92	#define RSEQ_ASM_TMP_REG_2 "x14"
	93
	94	#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip, \
	95	post_commit_offset, abort_ip) \
dd01d0fb	96	" .pushsection __rseq_cs, \"aw\"\n" \
d78a16c2 MD	97	" .balign 32\n" \
	98	__rseq_str(label) ":\n" \
	99	" .long " __rseq_str(version) ", " __rseq_str(flags) "\n" \
	100	" .quad " __rseq_str(start_ip) ", " \
	101	__rseq_str(post_commit_offset) ", " \
	102	__rseq_str(abort_ip) "\n" \
dd01d0fb MD	103	" .popsection\n\t" \
	104	" .pushsection __rseq_cs_ptr_array, \"aw\"\n" \
	105	" .quad " __rseq_str(label) "b\n" \
d78a16c2 MD	106	" .popsection\n"
	107
	108	#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \
	109	__RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \
	110	(post_commit_ip - start_ip), abort_ip)
	111
90d9876e MD	112	/*
90d9876e MD	113	* Exit points of a rseq critical section consist of all instructions outside
fd622cad MD	114	* of the critical section where a critical section can either branch to or
	115	* reach through the normal course of its execution. The abort IP and the
	116	* post-commit IP are already part of the __rseq_cs section and should not be
	117	* explicitly defined as additional exit points. Knowing all exit points is
	118	* useful to assist debuggers stepping over the critical section.
90d9876e MD	119	*/
	120	#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \
	121	" .pushsection __rseq_exit_point_array, \"aw\"\n" \
	122	" .quad " __rseq_str(start_ip) ", " __rseq_str(exit_ip) "\n" \
	123	" .popsection\n"
	124
d78a16c2 MD	125	#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \
	126	RSEQ_INJECT_ASM(1) \
	127	" adrp " RSEQ_ASM_TMP_REG ", " __rseq_str(cs_label) "\n" \
	128	" add " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
	129	", :lo12:" __rseq_str(cs_label) "\n" \
	130	" str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(rseq_cs) "]\n" \
	131	__rseq_str(label) ":\n"
	132
ebd27573	133	#define RSEQ_ASM_DEFINE_ABORT(label, teardown, abort_label) \
d78a16c2	134	" b 222f\n" \
8b7c64f7	135	" .inst " __rseq_str(RSEQ_SIG_CODE) "\n" \
d78a16c2	136	__rseq_str(label) ":\n" \
ebd27573	137	teardown \
d78a16c2 MD	138	" b %l[" __rseq_str(abort_label) "]\n" \
	139	"222:\n"
	140
	141	#define RSEQ_ASM_OP_STORE(value, var) \
	142	" str %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n"
	143
	144	#define RSEQ_ASM_OP_STORE_RELEASE(value, var) \
	145	" stlr %[" __rseq_str(value) "], %[" __rseq_str(var) "]\n"
	146
	147	#define RSEQ_ASM_OP_FINAL_STORE(value, var, post_commit_label) \
	148	RSEQ_ASM_OP_STORE(value, var) \
	149	__rseq_str(post_commit_label) ":\n"
	150
	151	#define RSEQ_ASM_OP_FINAL_STORE_RELEASE(value, var, post_commit_label) \
	152	RSEQ_ASM_OP_STORE_RELEASE(value, var) \
	153	__rseq_str(post_commit_label) ":\n"
	154
769ec9a5	155	#define RSEQ_ASM_OP_CBNE(var, expect, label) \
d78a16c2 MD	156	" ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \
	157	" sub " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
	158	", %[" __rseq_str(expect) "]\n" \
	159	" cbnz " RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n"
	160
769ec9a5	161	#define RSEQ_ASM_OP_CBNE32(var, expect, label) \
d78a16c2 MD	162	" ldr " RSEQ_ASM_TMP_REG32 ", %[" __rseq_str(var) "]\n" \
	163	" sub " RSEQ_ASM_TMP_REG32 ", " RSEQ_ASM_TMP_REG32 \
	164	", %w[" __rseq_str(expect) "]\n" \
	165	" cbnz " RSEQ_ASM_TMP_REG32 ", " __rseq_str(label) "\n"
	166
769ec9a5	167	#define RSEQ_ASM_OP_CBEQ(var, expect, label) \
d78a16c2 MD	168	" ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \
	169	" sub " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
	170	", %[" __rseq_str(expect) "]\n" \
	171	" cbz " RSEQ_ASM_TMP_REG ", " __rseq_str(label) "\n"
	172
769ec9a5	173	#define RSEQ_ASM_CBNE_CPU_ID(cpu_id, current_cpu_id, label) \
d78a16c2	174	RSEQ_INJECT_ASM(2) \
769ec9a5	175	RSEQ_ASM_OP_CBNE32(current_cpu_id, cpu_id, label)
d78a16c2 MD	176
	177	#define RSEQ_ASM_OP_R_LOAD(var) \
	178	" ldr " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"
	179
	180	#define RSEQ_ASM_OP_R_STORE(var) \
	181	" str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n"
	182
	183	#define RSEQ_ASM_OP_R_LOAD_OFF(offset) \
	184	" ldr " RSEQ_ASM_TMP_REG ", [" RSEQ_ASM_TMP_REG \
	185	", %[" __rseq_str(offset) "]]\n"
	186
	187	#define RSEQ_ASM_OP_R_ADD(count) \
	188	" add " RSEQ_ASM_TMP_REG ", " RSEQ_ASM_TMP_REG \
	189	", %[" __rseq_str(count) "]\n"
	190
	191	#define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label) \
	192	" str " RSEQ_ASM_TMP_REG ", %[" __rseq_str(var) "]\n" \
	193	__rseq_str(post_commit_label) ":\n"
	194
	195	#define RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) \
	196	" cbz %[" __rseq_str(len) "], 333f\n" \
	197	" mov " RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(len) "]\n" \
	198	"222: sub " RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", #1\n" \
	199	" ldrb " RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(src) "]" \
	200	", " RSEQ_ASM_TMP_REG_2 "]\n" \
	201	" strb " RSEQ_ASM_TMP_REG32 ", [%[" __rseq_str(dst) "]" \
	202	", " RSEQ_ASM_TMP_REG_2 "]\n" \
	203	" cbnz " RSEQ_ASM_TMP_REG_2 ", 222b\n" \
	204	"333:\n"
	205
a98a3b6d	206	/* Per-cpu-id indexing. */
d78a16c2	207
a98a3b6d MD	208	#define RSEQ_TEMPLATE_CPU_ID
	209	#define RSEQ_TEMPLATE_MO_RELAXED
	210	#include "rseq-arm64-bits.h"
	211	#undef RSEQ_TEMPLATE_MO_RELAXED
d78a16c2	212
a98a3b6d MD	213	#define RSEQ_TEMPLATE_MO_RELEASE
	214	#include "rseq-arm64-bits.h"
	215	#undef RSEQ_TEMPLATE_MO_RELEASE
	216	#undef RSEQ_TEMPLATE_CPU_ID
	217
	218	/* Per-mm-cid indexing. */
	219
	220	#define RSEQ_TEMPLATE_MM_CID
	221	#define RSEQ_TEMPLATE_MO_RELAXED
	222	#include "rseq-arm64-bits.h"
	223	#undef RSEQ_TEMPLATE_MO_RELAXED
	224
	225	#define RSEQ_TEMPLATE_MO_RELEASE
	226	#include "rseq-arm64-bits.h"
	227	#undef RSEQ_TEMPLATE_MO_RELEASE
	228	#undef RSEQ_TEMPLATE_MM_CID
	229
	230	/* APIs which are not based on cpu ids. */
	231
	232	#define RSEQ_TEMPLATE_CPU_ID_NONE
	233	#define RSEQ_TEMPLATE_MO_RELAXED
	234	#include "rseq-arm64-bits.h"
	235	#undef RSEQ_TEMPLATE_MO_RELAXED
	236	#undef RSEQ_TEMPLATE_CPU_ID_NONE