projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| c7736edf PG |
1 | /* |
| 2 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify it | |
| 5 | * under the terms and conditions of the GNU General Public License, | |
| 6 | * version 2, as published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 11 | * more details. | |
| 12 | * | |
| 13 | * You should have received a copy of the GNU General Public License | |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
| 15 | */ | |
| 16 | ||
| 306a7f91 TR |
17 | #ifndef __SOC_TEGRA_FUSE_H__ |
| 18 | #define __SOC_TEGRA_FUSE_H__ | |
| c7736edf | 19 | |
| 304664ea TR |
20 | #define TEGRA20 0x20 |
| 21 | #define TEGRA30 0x30 | |
| 22 | #define TEGRA114 0x35 | |
| 23 | #define TEGRA124 0x40 | |
| 24ef5745 | 24 | #define TEGRA132 0x13 |
| 0dc5a0d8 | 25 | #define TEGRA210 0x21 |
| 304664ea | 26 | |
| 783c8f4c PDS |
27 | #define TEGRA_FUSE_SKU_CALIB_0 0xf0 |
| 28 | #define TEGRA30_FUSE_SATA_CALIB 0x124 | |
| 87d66f28 | 29 | #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250 |
| 783c8f4c | 30 | |
| 304664ea TR |
31 | #ifndef __ASSEMBLY__ |
| 32 | ||
| c7736edf | 33 | u32 tegra_read_chipid(void); |
| 304664ea TR |
34 | u8 tegra_get_chip_id(void); |
| 35 | ||
| 35874f36 PDS |
36 | enum tegra_revision { |
| 37 | TEGRA_REVISION_UNKNOWN = 0, | |
| 38 | TEGRA_REVISION_A01, | |
| 39 | TEGRA_REVISION_A02, | |
| 40 | TEGRA_REVISION_A03, | |
| 41 | TEGRA_REVISION_A03p, | |
| 42 | TEGRA_REVISION_A04, | |
| 43 | TEGRA_REVISION_MAX, | |
| 44 | }; | |
| 45 | ||
| 783c8f4c PDS |
46 | struct tegra_sku_info { |
| 47 | int sku_id; | |
| 48 | int cpu_process_id; | |
| 49 | int cpu_speedo_id; | |
| 50 | int cpu_speedo_value; | |
| 51 | int cpu_iddq_value; | |
| 03b3f4c8 | 52 | int soc_process_id; |
| 783c8f4c | 53 | int soc_speedo_id; |
| 0dc5a0d8 | 54 | int soc_speedo_value; |
| 783c8f4c | 55 | int gpu_process_id; |
| 0dc5a0d8 | 56 | int gpu_speedo_id; |
| 783c8f4c PDS |
57 | int gpu_speedo_value; |
| 58 | enum tegra_revision revision; | |
| 59 | }; | |
| 60 | ||
| 35874f36 | 61 | u32 tegra_read_straps(void); |
| 6ea2609a | 62 | u32 tegra_read_ram_code(void); |
| 35874f36 | 63 | u32 tegra_read_chipid(void); |
| 783c8f4c | 64 | int tegra_fuse_readl(unsigned long offset, u32 *value); |
| 35874f36 | 65 | |
| 783c8f4c | 66 | extern struct tegra_sku_info tegra_sku_info; |
| 35874f36 | 67 | |
| 304664ea | 68 | #endif /* __ASSEMBLY__ */ |
| c7736edf | 69 | |
| 306a7f91 | 70 | #endif /* __SOC_TEGRA_FUSE_H__ */ |