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ef5fa1a4 | 1 | #ifndef __SOUND_HDSPM_H |
763f356c TI |
2 | #define __SOUND_HDSPM_H |
3 | /* | |
4 | * Copyright (C) 2003 Winfried Ritsch (IEM) | |
5 | * based on hdsp.h from Thomas Charbonnel (thomas@undata.org) | |
0dca1793 AK |
6 | * |
7 | * | |
763f356c TI |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
23 | /* Maximum channels is 64 even on 56Mode you have 64playbacks to matrix */ | |
24 | #define HDSPM_MAX_CHANNELS 64 | |
25 | ||
0dca1793 AK |
26 | enum hdspm_io_type { |
27 | MADI, | |
28 | MADIface, | |
29 | AIO, | |
30 | AES32, | |
31 | RayDAT | |
32 | }; | |
763f356c | 33 | |
0dca1793 AK |
34 | enum hdspm_speed { |
35 | ss, | |
36 | ds, | |
37 | qs | |
38 | }; | |
763f356c | 39 | |
0dca1793 | 40 | /* -------------------- IOCTL Peak/RMS Meters -------------------- */ |
763f356c | 41 | |
0dca1793 AK |
42 | struct hdspm_peak_rms { |
43 | uint32_t input_peaks[64]; | |
44 | uint32_t playback_peaks[64]; | |
45 | uint32_t output_peaks[64]; | |
763f356c | 46 | |
0dca1793 AK |
47 | uint64_t input_rms[64]; |
48 | uint64_t playback_rms[64]; | |
49 | uint64_t output_rms[64]; | |
763f356c | 50 | |
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51 | uint8_t speed; /* enum {ss, ds, qs} */ |
52 | int status2; | |
763f356c TI |
53 | }; |
54 | ||
ef5fa1a4 | 55 | #define SNDRV_HDSPM_IOCTL_GET_PEAK_RMS \ |
0dca1793 | 56 | _IOR('H', 0x42, struct hdspm_peak_rms) |
763f356c TI |
57 | |
58 | /* ------------ CONFIG block IOCTL ---------------------- */ | |
59 | ||
0dca1793 | 60 | struct hdspm_config { |
763f356c TI |
61 | unsigned char pref_sync_ref; |
62 | unsigned char wordclock_sync_check; | |
63 | unsigned char madi_sync_check; | |
64 | unsigned int system_sample_rate; | |
65 | unsigned int autosync_sample_rate; | |
66 | unsigned char system_clock_mode; | |
67 | unsigned char clock_source; | |
68 | unsigned char autosync_ref; | |
69 | unsigned char line_out; | |
70 | unsigned int passthru; | |
71 | unsigned int analog_out; | |
72 | }; | |
73 | ||
0dca1793 AK |
74 | #define SNDRV_HDSPM_IOCTL_GET_CONFIG \ |
75 | _IOR('H', 0x41, struct hdspm_config) | |
76 | ||
77 | /** | |
78 | * If there's a TCO (TimeCode Option) board installed, | |
79 | * there are further options and status data available. | |
80 | * The hdspm_ltc structure contains the current SMPTE | |
81 | * timecode and some status information and can be | |
82 | * obtained via SNDRV_HDSPM_IOCTL_GET_LTC or in the | |
83 | * hdspm_status struct. | |
84 | **/ | |
85 | ||
86 | enum hdspm_ltc_format { | |
87 | format_invalid, | |
88 | fps_24, | |
89 | fps_25, | |
90 | fps_2997, | |
91 | fps_30 | |
92 | }; | |
93 | ||
94 | enum hdspm_ltc_frame { | |
95 | frame_invalid, | |
96 | drop_frame, | |
97 | full_frame | |
98 | }; | |
99 | ||
100 | enum hdspm_ltc_input_format { | |
101 | ntsc, | |
102 | pal, | |
103 | no_video | |
104 | }; | |
105 | ||
106 | struct hdspm_ltc { | |
107 | unsigned int ltc; | |
108 | ||
109 | enum hdspm_ltc_format format; | |
110 | enum hdspm_ltc_frame frame; | |
111 | enum hdspm_ltc_input_format input_format; | |
112 | }; | |
113 | ||
114 | #define SNDRV_HDSPM_IOCTL_GET_LTC _IOR('H', 0x46, struct hdspm_mixer_ioctl) | |
115 | ||
116 | /** | |
117 | * The status data reflects the device's current state | |
118 | * as determined by the card's configuration and | |
119 | * connection status. | |
120 | **/ | |
121 | ||
122 | enum hdspm_sync { | |
123 | hdspm_sync_no_lock = 0, | |
124 | hdspm_sync_lock = 1, | |
125 | hdspm_sync_sync = 2 | |
126 | }; | |
127 | ||
128 | enum hdspm_madi_input { | |
129 | hdspm_input_optical = 0, | |
130 | hdspm_input_coax = 1 | |
131 | }; | |
132 | ||
133 | enum hdspm_madi_channel_format { | |
134 | hdspm_format_ch_64 = 0, | |
135 | hdspm_format_ch_56 = 1 | |
136 | }; | |
137 | ||
138 | enum hdspm_madi_frame_format { | |
139 | hdspm_frame_48 = 0, | |
140 | hdspm_frame_96 = 1 | |
141 | }; | |
142 | ||
143 | enum hdspm_syncsource { | |
144 | syncsource_wc = 0, | |
145 | syncsource_madi = 1, | |
146 | syncsource_tco = 2, | |
147 | syncsource_sync = 3, | |
148 | syncsource_none = 4 | |
149 | }; | |
150 | ||
151 | struct hdspm_status { | |
152 | uint8_t card_type; /* enum hdspm_io_type */ | |
153 | enum hdspm_syncsource autosync_source; | |
763f356c | 154 | |
0dca1793 AK |
155 | uint64_t card_clock; |
156 | uint32_t master_period; | |
157 | ||
158 | union { | |
159 | struct { | |
160 | uint8_t sync_wc; /* enum hdspm_sync */ | |
161 | uint8_t sync_madi; /* enum hdspm_sync */ | |
162 | uint8_t sync_tco; /* enum hdspm_sync */ | |
163 | uint8_t sync_in; /* enum hdspm_sync */ | |
164 | uint8_t madi_input; /* enum hdspm_madi_input */ | |
165 | uint8_t channel_format; /* enum hdspm_madi_channel_format */ | |
166 | uint8_t frame_format; /* enum hdspm_madi_frame_format */ | |
167 | } madi; | |
168 | } card_specific; | |
169 | }; | |
763f356c | 170 | |
0dca1793 AK |
171 | #define SNDRV_HDSPM_IOCTL_GET_STATUS \ |
172 | _IOR('H', 0x47, struct hdspm_status) | |
173 | ||
174 | /** | |
175 | * Get information about the card and its add-ons. | |
176 | **/ | |
177 | ||
178 | #define HDSPM_ADDON_TCO 1 | |
763f356c | 179 | |
98274f07 | 180 | struct hdspm_version { |
0dca1793 AK |
181 | uint8_t card_type; /* enum hdspm_io_type */ |
182 | char cardname[20]; | |
183 | unsigned int serial; | |
763f356c | 184 | unsigned short firmware_rev; |
0dca1793 | 185 | int addons; |
763f356c TI |
186 | }; |
187 | ||
0dca1793 | 188 | #define SNDRV_HDSPM_IOCTL_GET_VERSION _IOR('H', 0x48, struct hdspm_version) |
763f356c TI |
189 | |
190 | /* ------------- get Matrix Mixer IOCTL --------------- */ | |
191 | ||
ef5fa1a4 TI |
192 | /* MADI mixer: 64inputs+64playback in 64outputs = 8192 => *4Byte = |
193 | * 32768 Bytes | |
194 | */ | |
763f356c | 195 | |
25985edc | 196 | /* organisation is 64 channelfader in a continuous memory block */ |
ef5fa1a4 TI |
197 | /* equivalent to hardware definition, maybe for future feature of mmap of |
198 | * them | |
199 | */ | |
0dca1793 | 200 | /* each of 64 outputs has 64 infader and 64 outfader: |
763f356c TI |
201 | Ins to Outs mixer[out].in[in], Outstreams to Outs mixer[out].pb[pb] */ |
202 | ||
203 | #define HDSPM_MIXER_CHANNELS HDSPM_MAX_CHANNELS | |
204 | ||
98274f07 | 205 | struct hdspm_channelfader { |
763f356c TI |
206 | unsigned int in[HDSPM_MIXER_CHANNELS]; |
207 | unsigned int pb[HDSPM_MIXER_CHANNELS]; | |
208 | }; | |
209 | ||
98274f07 TI |
210 | struct hdspm_mixer { |
211 | struct hdspm_channelfader ch[HDSPM_MIXER_CHANNELS]; | |
763f356c TI |
212 | }; |
213 | ||
98274f07 TI |
214 | struct hdspm_mixer_ioctl { |
215 | struct hdspm_mixer *mixer; | |
763f356c TI |
216 | }; |
217 | ||
218 | /* use indirect access due to the limit of ioctl bit size */ | |
98274f07 TI |
219 | #define SNDRV_HDSPM_IOCTL_GET_MIXER _IOR('H', 0x44, struct hdspm_mixer_ioctl) |
220 | ||
221 | /* typedefs for compatibility to user-space */ | |
222 | typedef struct hdspm_peak_rms hdspm_peak_rms_t; | |
223 | typedef struct hdspm_config_info hdspm_config_info_t; | |
224 | typedef struct hdspm_version hdspm_version_t; | |
225 | typedef struct hdspm_channelfader snd_hdspm_channelfader_t; | |
226 | typedef struct hdspm_mixer hdspm_mixer_t; | |
763f356c | 227 | |
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228 | |
229 | #endif |