Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * Driver for Digigram VX soundcards | |
3 | * | |
4 | * Hardware core part | |
5 | * | |
6 | * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #ifndef __SOUND_VX_COMMON_H | |
24 | #define __SOUND_VX_COMMON_H | |
25 | ||
26 | #include <sound/pcm.h> | |
27 | #include <sound/hwdep.h> | |
28 | #include <linux/interrupt.h> | |
29 | ||
1da177e4 LT |
30 | struct firmware; |
31 | struct device; | |
32 | ||
1da177e4 LT |
33 | #define VX_DRIVER_VERSION 0x010000 /* 1.0.0 */ |
34 | ||
35 | /* | |
36 | */ | |
37 | #define SIZE_MAX_CMD 0x10 | |
38 | #define SIZE_MAX_STATUS 0x10 | |
39 | ||
40 | struct vx_rmh { | |
41 | u16 LgCmd; /* length of the command to send (WORDs) */ | |
42 | u16 LgStat; /* length of the status received (WORDs) */ | |
43 | u32 Cmd[SIZE_MAX_CMD]; | |
44 | u32 Stat[SIZE_MAX_STATUS]; | |
45 | u16 DspStat; /* status type, RMP_SSIZE_XXX */ | |
46 | }; | |
47 | ||
48 | typedef u64 pcx_time_t; | |
49 | ||
50 | #define VX_MAX_PIPES 16 | |
51 | #define VX_MAX_PERIODS 32 | |
52 | #define VX_MAX_CODECS 2 | |
53 | ||
54 | struct vx_ibl_info { | |
55 | int size; /* the current IBL size (0 = query) in bytes */ | |
56 | int max_size; /* max. IBL size in bytes */ | |
57 | int min_size; /* min. IBL size in bytes */ | |
58 | int granularity; /* granularity */ | |
59 | }; | |
60 | ||
61 | struct vx_pipe { | |
62 | int number; | |
63 | unsigned int is_capture: 1; | |
64 | unsigned int data_mode: 1; | |
65 | unsigned int running: 1; | |
66 | unsigned int prepared: 1; | |
67 | int channels; | |
68 | unsigned int differed_type; | |
69 | pcx_time_t pcx_time; | |
af26367f | 70 | struct snd_pcm_substream *substream; |
1da177e4 LT |
71 | |
72 | int hbuf_size; /* H-buffer size in bytes */ | |
73 | int buffer_bytes; /* the ALSA pcm buffer size in bytes */ | |
74 | int period_bytes; /* the ALSA pcm period size in bytes */ | |
75 | int hw_ptr; /* the current hardware pointer in bytes */ | |
76 | int position; /* the current position in frames (playback only) */ | |
77 | int transferred; /* the transferred size (per period) in frames */ | |
78 | int align; /* size of alignment */ | |
79 | u64 cur_count; /* current sample position (for playback) */ | |
80 | ||
81 | unsigned int references; /* an output pipe may be used for monitoring and/or playback */ | |
af26367f | 82 | struct vx_pipe *monitoring_pipe; /* pointer to the monitoring pipe (capture pipe only)*/ |
1da177e4 LT |
83 | }; |
84 | ||
af26367f TI |
85 | struct vx_core; |
86 | ||
1da177e4 LT |
87 | struct snd_vx_ops { |
88 | /* low-level i/o */ | |
af26367f TI |
89 | unsigned char (*in8)(struct vx_core *chip, int reg); |
90 | unsigned int (*in32)(struct vx_core *chip, int reg); | |
91 | void (*out8)(struct vx_core *chip, int reg, unsigned char val); | |
92 | void (*out32)(struct vx_core *chip, int reg, unsigned int val); | |
1da177e4 | 93 | /* irq */ |
af26367f TI |
94 | int (*test_and_ack)(struct vx_core *chip); |
95 | void (*validate_irq)(struct vx_core *chip, int enable); | |
1da177e4 | 96 | /* codec */ |
af26367f TI |
97 | void (*write_codec)(struct vx_core *chip, int codec, unsigned int data); |
98 | void (*akm_write)(struct vx_core *chip, int reg, unsigned int data); | |
99 | void (*reset_codec)(struct vx_core *chip); | |
100 | void (*change_audio_source)(struct vx_core *chip, int src); | |
101 | void (*set_clock_source)(struct vx_core *chp, int src); | |
1da177e4 | 102 | /* chip init */ |
af26367f TI |
103 | int (*load_dsp)(struct vx_core *chip, int idx, const struct firmware *fw); |
104 | void (*reset_dsp)(struct vx_core *chip); | |
105 | void (*reset_board)(struct vx_core *chip, int cold_reset); | |
106 | int (*add_controls)(struct vx_core *chip); | |
1da177e4 | 107 | /* pcm */ |
af26367f TI |
108 | void (*dma_write)(struct vx_core *chip, struct snd_pcm_runtime *runtime, |
109 | struct vx_pipe *pipe, int count); | |
110 | void (*dma_read)(struct vx_core *chip, struct snd_pcm_runtime *runtime, | |
111 | struct vx_pipe *pipe, int count); | |
1da177e4 LT |
112 | }; |
113 | ||
114 | struct snd_vx_hardware { | |
115 | const char *name; | |
116 | int type; /* VX_TYPE_XXX */ | |
117 | ||
118 | /* hardware specs */ | |
119 | unsigned int num_codecs; | |
120 | unsigned int num_ins; | |
121 | unsigned int num_outs; | |
122 | unsigned int output_level_max; | |
0cb29ea0 | 123 | const unsigned int *output_level_db_scale; |
1da177e4 LT |
124 | }; |
125 | ||
126 | /* hwdep id string */ | |
127 | #define SND_VX_HWDEP_ID "VX Loader" | |
128 | ||
129 | /* hardware type */ | |
130 | enum { | |
131 | /* VX222 PCI */ | |
132 | VX_TYPE_BOARD, /* old VX222 PCI */ | |
133 | VX_TYPE_V2, /* VX222 V2 PCI */ | |
134 | VX_TYPE_MIC, /* VX222 Mic PCI */ | |
135 | /* VX-pocket */ | |
136 | VX_TYPE_VXPOCKET, /* VXpocket V2 */ | |
137 | VX_TYPE_VXP440, /* VXpocket 440 */ | |
138 | VX_TYPE_NUMS | |
139 | }; | |
140 | ||
141 | /* chip status */ | |
142 | enum { | |
143 | VX_STAT_XILINX_LOADED = (1 << 0), /* devices are registered */ | |
144 | VX_STAT_DEVICE_INIT = (1 << 1), /* devices are registered */ | |
145 | VX_STAT_CHIP_INIT = (1 << 2), /* all operational */ | |
146 | VX_STAT_IN_SUSPEND = (1 << 10), /* in suspend phase */ | |
147 | VX_STAT_IS_STALE = (1 << 15) /* device is stale */ | |
148 | }; | |
149 | ||
150 | /* min/max values for analog output for old codecs */ | |
151 | #define VX_ANALOG_OUT_LEVEL_MAX 0xe3 | |
152 | ||
af26367f | 153 | struct vx_core { |
1da177e4 | 154 | /* ALSA stuff */ |
af26367f TI |
155 | struct snd_card *card; |
156 | struct snd_pcm *pcm[VX_MAX_CODECS]; | |
1da177e4 LT |
157 | int type; /* VX_TYPE_XXX */ |
158 | ||
159 | int irq; | |
160 | /* ports are defined externally */ | |
161 | ||
162 | /* low-level functions */ | |
163 | struct snd_vx_hardware *hw; | |
164 | struct snd_vx_ops *ops; | |
165 | ||
db0a5214 | 166 | struct mutex lock; |
1da177e4 LT |
167 | |
168 | unsigned int chip_status; | |
169 | unsigned int pcm_running; | |
170 | ||
171 | struct device *dev; | |
af26367f | 172 | struct snd_hwdep *hwdep; |
1da177e4 LT |
173 | |
174 | struct vx_rmh irq_rmh; /* RMH used in interrupts */ | |
175 | ||
176 | unsigned int audio_info; /* see VX_AUDIO_INFO */ | |
177 | unsigned int audio_ins; | |
178 | unsigned int audio_outs; | |
179 | struct vx_pipe **playback_pipes; | |
180 | struct vx_pipe **capture_pipes; | |
181 | ||
182 | /* clock and audio sources */ | |
183 | unsigned int audio_source; /* current audio input source */ | |
184 | unsigned int audio_source_target; | |
185 | unsigned int clock_mode; /* clock mode (VX_CLOCK_MODE_XXX) */ | |
186 | unsigned int clock_source; /* current clock source (INTERNAL_QUARTZ or UER_SYNC) */ | |
187 | unsigned int freq; /* current frequency */ | |
188 | unsigned int freq_detected; /* detected frequency from digital in */ | |
189 | unsigned int uer_detected; /* VX_UER_MODE_XXX */ | |
190 | unsigned int uer_bits; /* IEC958 status bits */ | |
191 | struct vx_ibl_info ibl; /* IBL information */ | |
192 | ||
193 | /* mixer setting */ | |
194 | int output_level[VX_MAX_CODECS][2]; /* analog output level */ | |
195 | int audio_gain[2][4]; /* digital audio level (playback/capture) */ | |
196 | unsigned char audio_active[4]; /* mute/unmute on digital playback */ | |
197 | int audio_monitor[4]; /* playback hw-monitor level */ | |
198 | unsigned char audio_monitor_active[4]; /* playback hw-monitor mute/unmute */ | |
199 | ||
ef9f0a42 | 200 | struct mutex mixer_mutex; |
1da177e4 LT |
201 | |
202 | const struct firmware *firmware[4]; /* loaded firmware data */ | |
203 | }; | |
204 | ||
205 | ||
206 | /* | |
207 | * constructor | |
208 | */ | |
af26367f TI |
209 | struct vx_core *snd_vx_create(struct snd_card *card, struct snd_vx_hardware *hw, |
210 | struct snd_vx_ops *ops, int extra_size); | |
211 | int snd_vx_setup_firmware(struct vx_core *chip); | |
212 | int snd_vx_load_boot_image(struct vx_core *chip, const struct firmware *dsp); | |
213 | int snd_vx_dsp_boot(struct vx_core *chip, const struct firmware *dsp); | |
214 | int snd_vx_dsp_load(struct vx_core *chip, const struct firmware *dsp); | |
1da177e4 | 215 | |
af26367f | 216 | void snd_vx_free_firmware(struct vx_core *chip); |
1da177e4 LT |
217 | |
218 | /* | |
219 | * interrupt handler; exported for pcmcia | |
220 | */ | |
7d12e780 | 221 | irqreturn_t snd_vx_irq_handler(int irq, void *dev); |
db0a5214 | 222 | irqreturn_t snd_vx_threaded_irq_handler(int irq, void *dev); |
1da177e4 LT |
223 | |
224 | /* | |
225 | * lowlevel functions | |
226 | */ | |
af26367f | 227 | static inline int vx_test_and_ack(struct vx_core *chip) |
1da177e4 | 228 | { |
1da177e4 LT |
229 | return chip->ops->test_and_ack(chip); |
230 | } | |
231 | ||
af26367f | 232 | static inline void vx_validate_irq(struct vx_core *chip, int enable) |
1da177e4 | 233 | { |
1da177e4 LT |
234 | chip->ops->validate_irq(chip, enable); |
235 | } | |
236 | ||
af26367f | 237 | static inline unsigned char snd_vx_inb(struct vx_core *chip, int reg) |
1da177e4 | 238 | { |
1da177e4 LT |
239 | return chip->ops->in8(chip, reg); |
240 | } | |
241 | ||
af26367f | 242 | static inline unsigned int snd_vx_inl(struct vx_core *chip, int reg) |
1da177e4 | 243 | { |
1da177e4 LT |
244 | return chip->ops->in32(chip, reg); |
245 | } | |
246 | ||
af26367f | 247 | static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val) |
1da177e4 | 248 | { |
1da177e4 LT |
249 | chip->ops->out8(chip, reg, val); |
250 | } | |
251 | ||
af26367f | 252 | static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val) |
1da177e4 | 253 | { |
1da177e4 LT |
254 | chip->ops->out32(chip, reg, val); |
255 | } | |
256 | ||
257 | #define vx_inb(chip,reg) snd_vx_inb(chip, VX_##reg) | |
258 | #define vx_outb(chip,reg,val) snd_vx_outb(chip, VX_##reg,val) | |
259 | #define vx_inl(chip,reg) snd_vx_inl(chip, VX_##reg) | |
260 | #define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val) | |
261 | ||
af26367f | 262 | static inline void vx_reset_dsp(struct vx_core *chip) |
1da177e4 | 263 | { |
1da177e4 LT |
264 | chip->ops->reset_dsp(chip); |
265 | } | |
266 | ||
af26367f TI |
267 | int vx_send_msg(struct vx_core *chip, struct vx_rmh *rmh); |
268 | int vx_send_msg_nolock(struct vx_core *chip, struct vx_rmh *rmh); | |
269 | int vx_send_rih(struct vx_core *chip, int cmd); | |
270 | int vx_send_rih_nolock(struct vx_core *chip, int cmd); | |
1da177e4 | 271 | |
af26367f | 272 | void vx_reset_codec(struct vx_core *chip, int cold_reset); |
1da177e4 LT |
273 | |
274 | /* | |
275 | * check the bit on the specified register | |
276 | * returns zero if a bit matches, or a negative error code. | |
277 | * exported for vxpocket driver | |
278 | */ | |
af26367f | 279 | int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time); |
1da177e4 LT |
280 | #define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time) |
281 | #define vx_wait_isr_bit(chip,bit) vx_check_isr(chip, bit, bit, 200) | |
282 | #define vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL) | |
283 | ||
284 | ||
285 | /* | |
286 | * pseudo-DMA transfer | |
287 | */ | |
af26367f TI |
288 | static inline void vx_pseudo_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime, |
289 | struct vx_pipe *pipe, int count) | |
1da177e4 | 290 | { |
1da177e4 LT |
291 | chip->ops->dma_write(chip, runtime, pipe, count); |
292 | } | |
293 | ||
af26367f TI |
294 | static inline void vx_pseudo_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime, |
295 | struct vx_pipe *pipe, int count) | |
1da177e4 | 296 | { |
1da177e4 LT |
297 | chip->ops->dma_read(chip, runtime, pipe, count); |
298 | } | |
299 | ||
300 | ||
301 | ||
302 | /* error with hardware code, | |
303 | * the return value is -(VX_ERR_MASK | actual-hw-error-code) | |
304 | */ | |
305 | #define VX_ERR_MASK 0x1000000 | |
306 | #define vx_get_error(err) (-(err) & ~VX_ERR_MASK) | |
307 | ||
308 | ||
309 | /* | |
310 | * pcm stuff | |
311 | */ | |
af26367f TI |
312 | int snd_vx_pcm_new(struct vx_core *chip); |
313 | void vx_pcm_update_intr(struct vx_core *chip, unsigned int events); | |
1da177e4 LT |
314 | |
315 | /* | |
316 | * mixer stuff | |
317 | */ | |
af26367f TI |
318 | int snd_vx_mixer_new(struct vx_core *chip); |
319 | void vx_toggle_dac_mute(struct vx_core *chip, int mute); | |
320 | int vx_sync_audio_source(struct vx_core *chip); | |
321 | int vx_set_monitor_level(struct vx_core *chip, int audio, int level, int active); | |
1da177e4 LT |
322 | |
323 | /* | |
324 | * IEC958 & clock stuff | |
325 | */ | |
af26367f TI |
326 | void vx_set_iec958_status(struct vx_core *chip, unsigned int bits); |
327 | int vx_set_clock(struct vx_core *chip, unsigned int freq); | |
328 | void vx_set_internal_clock(struct vx_core *chip, unsigned int freq); | |
329 | int vx_change_frequency(struct vx_core *chip); | |
1da177e4 LT |
330 | |
331 | ||
0ed1cad1 TI |
332 | /* |
333 | * PM | |
334 | */ | |
68cb2b55 | 335 | int snd_vx_suspend(struct vx_core *card); |
0ed1cad1 TI |
336 | int snd_vx_resume(struct vx_core *card); |
337 | ||
1da177e4 LT |
338 | /* |
339 | * hardware constants | |
340 | */ | |
341 | ||
342 | #define vx_has_new_dsp(chip) ((chip)->type != VX_TYPE_BOARD) | |
343 | #define vx_is_pcmcia(chip) ((chip)->type >= VX_TYPE_VXPOCKET) | |
344 | ||
345 | /* audio input source */ | |
346 | enum { | |
347 | VX_AUDIO_SRC_DIGITAL, | |
348 | VX_AUDIO_SRC_LINE, | |
349 | VX_AUDIO_SRC_MIC | |
350 | }; | |
351 | ||
352 | /* clock source */ | |
353 | enum { | |
354 | INTERNAL_QUARTZ, | |
355 | UER_SYNC | |
356 | }; | |
357 | ||
358 | /* clock mode */ | |
359 | enum { | |
360 | VX_CLOCK_MODE_AUTO, /* depending on the current audio source */ | |
361 | VX_CLOCK_MODE_INTERNAL, /* fixed to internal quartz */ | |
362 | VX_CLOCK_MODE_EXTERNAL /* fixed to UER sync */ | |
363 | }; | |
364 | ||
365 | /* SPDIF/UER type */ | |
366 | enum { | |
367 | VX_UER_MODE_CONSUMER, | |
368 | VX_UER_MODE_PROFESSIONAL, | |
369 | VX_UER_MODE_NOT_PRESENT, | |
370 | }; | |
371 | ||
372 | /* register indices */ | |
373 | enum { | |
374 | VX_ICR, | |
375 | VX_CVR, | |
376 | VX_ISR, | |
377 | VX_IVR, | |
378 | VX_RXH, | |
379 | VX_TXH = VX_RXH, | |
380 | VX_RXM, | |
381 | VX_TXM = VX_RXM, | |
382 | VX_RXL, | |
383 | VX_TXL = VX_RXL, | |
384 | VX_DMA, | |
385 | VX_CDSP, | |
386 | VX_RFREQ, | |
387 | VX_RUER_V2, | |
388 | VX_GAIN, | |
389 | VX_DATA = VX_GAIN, | |
390 | VX_MEMIRQ, | |
391 | VX_ACQ, | |
392 | VX_BIT0, | |
393 | VX_BIT1, | |
394 | VX_MIC0, | |
395 | VX_MIC1, | |
396 | VX_MIC2, | |
397 | VX_MIC3, | |
398 | VX_PLX0, | |
399 | VX_PLX1, | |
400 | VX_PLX2, | |
401 | ||
402 | VX_LOFREQ, // V2: ACQ, VP: RFREQ | |
403 | VX_HIFREQ, // V2: BIT0, VP: RUER_V2 | |
404 | VX_CSUER, // V2: BIT1, VP: BIT0 | |
405 | VX_RUER, // V2: RUER_V2, VP: BIT1 | |
406 | ||
407 | VX_REG_MAX, | |
408 | ||
409 | /* aliases for VX board */ | |
410 | VX_RESET_DMA = VX_ISR, | |
411 | VX_CFG = VX_RFREQ, | |
412 | VX_STATUS = VX_MEMIRQ, | |
413 | VX_SELMIC = VX_MIC0, | |
414 | VX_COMPOT = VX_MIC1, | |
415 | VX_SCOMPR = VX_MIC2, | |
416 | VX_GLIMIT = VX_MIC3, | |
417 | VX_INTCSR = VX_PLX0, | |
418 | VX_CNTRL = VX_PLX1, | |
419 | VX_GPIOC = VX_PLX2, | |
420 | ||
421 | /* aliases for VXPOCKET board */ | |
422 | VX_MICRO = VX_MEMIRQ, | |
423 | VX_CODEC2 = VX_MEMIRQ, | |
424 | VX_DIALOG = VX_ACQ, | |
425 | ||
426 | }; | |
427 | ||
428 | /* RMH status type */ | |
429 | enum { | |
430 | RMH_SSIZE_FIXED = 0, /* status size given by the driver (in LgStat) */ | |
431 | RMH_SSIZE_ARG = 1, /* status size given in the LSB byte */ | |
432 | RMH_SSIZE_MASK = 2, /* status size given in bitmask */ | |
433 | }; | |
434 | ||
435 | ||
436 | /* bits for ICR register */ | |
437 | #define ICR_HF1 0x10 | |
438 | #define ICR_HF0 0x08 | |
439 | #define ICR_TREQ 0x02 /* Interrupt mode + HREQ set on for transfer (->DSP) request */ | |
440 | #define ICR_RREQ 0x01 /* Interrupt mode + RREQ set on for transfer (->PC) request */ | |
441 | ||
442 | /* bits for CVR register */ | |
443 | #define CVR_HC 0x80 | |
444 | ||
445 | /* bits for ISR register */ | |
446 | #define ISR_HF3 0x10 | |
447 | #define ISR_HF2 0x08 | |
448 | #define ISR_CHK 0x10 | |
449 | #define ISR_ERR 0x08 | |
450 | #define ISR_TX_READY 0x04 | |
451 | #define ISR_TX_EMPTY 0x02 | |
452 | #define ISR_RX_FULL 0x01 | |
453 | ||
454 | /* Constants used to access the DATA register */ | |
455 | #define VX_DATA_CODEC_MASK 0x80 | |
456 | #define VX_DATA_XICOR_MASK 0x80 | |
457 | ||
458 | /* Constants used to access the CSUER register (both for VX2 and VXP) */ | |
459 | #define VX_SUER_FREQ_MASK 0x0c | |
460 | #define VX_SUER_FREQ_32KHz_MASK 0x0c | |
461 | #define VX_SUER_FREQ_44KHz_MASK 0x00 | |
462 | #define VX_SUER_FREQ_48KHz_MASK 0x04 | |
463 | #define VX_SUER_DATA_PRESENT_MASK 0x02 | |
464 | #define VX_SUER_CLOCK_PRESENT_MASK 0x01 | |
465 | ||
466 | #define VX_CUER_HH_BITC_SEL_MASK 0x08 | |
467 | #define VX_CUER_MH_BITC_SEL_MASK 0x04 | |
468 | #define VX_CUER_ML_BITC_SEL_MASK 0x02 | |
469 | #define VX_CUER_LL_BITC_SEL_MASK 0x01 | |
470 | ||
471 | #define XX_UER_CBITS_OFFSET_MASK 0x1f | |
472 | ||
473 | ||
474 | /* bits for audio_info */ | |
475 | #define VX_AUDIO_INFO_REAL_TIME (1<<0) /* real-time processing available */ | |
476 | #define VX_AUDIO_INFO_OFFLINE (1<<1) /* offline processing available */ | |
477 | #define VX_AUDIO_INFO_MPEG1 (1<<5) | |
478 | #define VX_AUDIO_INFO_MPEG2 (1<<6) | |
479 | #define VX_AUDIO_INFO_LINEAR_8 (1<<7) | |
480 | #define VX_AUDIO_INFO_LINEAR_16 (1<<8) | |
481 | #define VX_AUDIO_INFO_LINEAR_24 (1<<9) | |
482 | ||
483 | /* DSP Interrupt Request values */ | |
484 | #define VXP_IRQ_OFFSET 0x40 /* add 0x40 offset for vxpocket and vx222/v2 */ | |
485 | /* call with vx_send_irq_dsp() */ | |
486 | #define IRQ_MESS_WRITE_END 0x30 | |
487 | #define IRQ_MESS_WRITE_NEXT 0x32 | |
488 | #define IRQ_MESS_READ_NEXT 0x34 | |
489 | #define IRQ_MESS_READ_END 0x36 | |
490 | #define IRQ_MESSAGE 0x38 | |
491 | #define IRQ_RESET_CHK 0x3A | |
492 | #define IRQ_CONNECT_STREAM_NEXT 0x26 | |
493 | #define IRQ_CONNECT_STREAM_END 0x28 | |
494 | #define IRQ_PAUSE_START_CONNECT 0x2A | |
495 | #define IRQ_END_CONNECTION 0x2C | |
496 | ||
497 | /* Is there async. events pending ( IT Source Test ) */ | |
498 | #define ASYNC_EVENTS_PENDING 0x008000 | |
499 | #define HBUFFER_EVENTS_PENDING 0x004000 // Not always accurate | |
500 | #define NOTIF_EVENTS_PENDING 0x002000 | |
501 | #define TIME_CODE_EVENT_PENDING 0x001000 | |
502 | #define FREQUENCY_CHANGE_EVENT_PENDING 0x000800 | |
503 | #define END_OF_BUFFER_EVENTS_PENDING 0x000400 | |
504 | #define FATAL_DSP_ERROR 0xff0000 | |
505 | ||
506 | /* Stream Format Header Defines */ | |
507 | #define HEADER_FMT_BASE 0xFED00000 | |
508 | #define HEADER_FMT_MONO 0x000000C0 | |
509 | #define HEADER_FMT_INTEL 0x00008000 | |
510 | #define HEADER_FMT_16BITS 0x00002000 | |
511 | #define HEADER_FMT_24BITS 0x00004000 | |
512 | #define HEADER_FMT_UPTO11 0x00000200 /* frequency is less or equ. to 11k.*/ | |
513 | #define HEADER_FMT_UPTO32 0x00000100 /* frequency is over 11k and less then 32k.*/ | |
514 | ||
515 | /* Constants used to access the Codec */ | |
516 | #define XX_CODEC_SELECTOR 0x20 | |
517 | /* codec commands */ | |
518 | #define XX_CODEC_ADC_CONTROL_REGISTER 0x01 | |
519 | #define XX_CODEC_DAC_CONTROL_REGISTER 0x02 | |
520 | #define XX_CODEC_LEVEL_LEFT_REGISTER 0x03 | |
521 | #define XX_CODEC_LEVEL_RIGHT_REGISTER 0x04 | |
522 | #define XX_CODEC_PORT_MODE_REGISTER 0x05 | |
523 | #define XX_CODEC_STATUS_REPORT_REGISTER 0x06 | |
524 | #define XX_CODEC_CLOCK_CONTROL_REGISTER 0x07 | |
525 | ||
526 | /* | |
527 | * Audio-level control values | |
528 | */ | |
529 | #define CVAL_M110DB 0x000 /* -110dB */ | |
530 | #define CVAL_M99DB 0x02C | |
531 | #define CVAL_M21DB 0x163 | |
532 | #define CVAL_M18DB 0x16F | |
533 | #define CVAL_M10DB 0x18F | |
534 | #define CVAL_0DB 0x1B7 | |
535 | #define CVAL_18DB 0x1FF /* +18dB */ | |
536 | #define CVAL_MAX 0x1FF | |
537 | ||
538 | #define AUDIO_IO_HAS_MUTE_LEVEL 0x400000 | |
539 | #define AUDIO_IO_HAS_MUTE_MONITORING_1 0x200000 | |
540 | #define AUDIO_IO_HAS_MUTE_MONITORING_2 0x100000 | |
541 | #define VALID_AUDIO_IO_DIGITAL_LEVEL 0x01 | |
542 | #define VALID_AUDIO_IO_MONITORING_LEVEL 0x02 | |
543 | #define VALID_AUDIO_IO_MUTE_LEVEL 0x04 | |
544 | #define VALID_AUDIO_IO_MUTE_MONITORING_1 0x08 | |
545 | #define VALID_AUDIO_IO_MUTE_MONITORING_2 0x10 | |
546 | ||
547 | ||
548 | #endif /* __SOUND_VX_COMMON_H */ |