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81629cba AD |
1 | /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- |
2 | * | |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. | |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. | |
6 | * Copyright 2014 Advanced Micro Devices, Inc. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
24 | * OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | * Authors: | |
27 | * Kevin E. Martin <martin@valinux.com> | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | */ | |
31 | ||
32 | #ifndef __AMDGPU_DRM_H__ | |
33 | #define __AMDGPU_DRM_H__ | |
34 | ||
b3fcf36a | 35 | #include "drm.h" |
81629cba AD |
36 | |
37 | #define DRM_AMDGPU_GEM_CREATE 0x00 | |
38 | #define DRM_AMDGPU_GEM_MMAP 0x01 | |
39 | #define DRM_AMDGPU_CTX 0x02 | |
40 | #define DRM_AMDGPU_BO_LIST 0x03 | |
41 | #define DRM_AMDGPU_CS 0x04 | |
42 | #define DRM_AMDGPU_INFO 0x05 | |
43 | #define DRM_AMDGPU_GEM_METADATA 0x06 | |
44 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 | |
45 | #define DRM_AMDGPU_GEM_VA 0x08 | |
46 | #define DRM_AMDGPU_WAIT_CS 0x09 | |
47 | #define DRM_AMDGPU_GEM_OP 0x10 | |
48 | #define DRM_AMDGPU_GEM_USERPTR 0x11 | |
49 | ||
50 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) | |
51 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) | |
52 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) | |
53 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) | |
54 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) | |
55 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) | |
56 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) | |
57 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) | |
34b5f6a6 | 58 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
81629cba AD |
59 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
60 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) | |
61 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) | |
62 | ||
63 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 | |
64 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 | |
65 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 | |
66 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 | |
67 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 | |
68 | #define AMDGPU_GEM_DOMAIN_OA 0x20 | |
69 | ||
81629cba AD |
70 | /* Flag that CPU access will be required for the case of VRAM domain */ |
71 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) | |
72 | /* Flag that CPU access will not work, this VRAM domain is invisible */ | |
73 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) | |
81629cba | 74 | /* Flag that USWC attributes should be used for GTT */ |
88671288 | 75 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
81629cba | 76 | |
81629cba AD |
77 | struct drm_amdgpu_gem_create_in { |
78 | /** the requested memory size */ | |
2ce9dde0 | 79 | __u64 bo_size; |
81629cba | 80 | /** physical start_addr alignment in bytes for some HW requirements */ |
2ce9dde0 | 81 | __u64 alignment; |
81629cba | 82 | /** the requested memory domains */ |
2ce9dde0 | 83 | __u64 domains; |
81629cba | 84 | /** allocation flags */ |
2ce9dde0 | 85 | __u64 domain_flags; |
81629cba AD |
86 | }; |
87 | ||
88 | struct drm_amdgpu_gem_create_out { | |
89 | /** returned GEM object handle */ | |
2ce9dde0 MR |
90 | __u32 handle; |
91 | __u32 _pad; | |
81629cba AD |
92 | }; |
93 | ||
94 | union drm_amdgpu_gem_create { | |
95 | struct drm_amdgpu_gem_create_in in; | |
96 | struct drm_amdgpu_gem_create_out out; | |
97 | }; | |
98 | ||
99 | /** Opcode to create new residency list. */ | |
100 | #define AMDGPU_BO_LIST_OP_CREATE 0 | |
101 | /** Opcode to destroy previously created residency list */ | |
102 | #define AMDGPU_BO_LIST_OP_DESTROY 1 | |
103 | /** Opcode to update resource information in the list */ | |
104 | #define AMDGPU_BO_LIST_OP_UPDATE 2 | |
105 | ||
106 | struct drm_amdgpu_bo_list_in { | |
107 | /** Type of operation */ | |
2ce9dde0 | 108 | __u32 operation; |
81629cba | 109 | /** Handle of list or 0 if we want to create one */ |
2ce9dde0 | 110 | __u32 list_handle; |
81629cba | 111 | /** Number of BOs in list */ |
2ce9dde0 | 112 | __u32 bo_number; |
81629cba | 113 | /** Size of each element describing BO */ |
2ce9dde0 | 114 | __u32 bo_info_size; |
81629cba | 115 | /** Pointer to array describing BOs */ |
2ce9dde0 | 116 | __u64 bo_info_ptr; |
81629cba AD |
117 | }; |
118 | ||
119 | struct drm_amdgpu_bo_list_entry { | |
120 | /** Handle of BO */ | |
2ce9dde0 | 121 | __u32 bo_handle; |
81629cba | 122 | /** New (if specified) BO priority to be used during migration */ |
2ce9dde0 | 123 | __u32 bo_priority; |
81629cba AD |
124 | }; |
125 | ||
126 | struct drm_amdgpu_bo_list_out { | |
127 | /** Handle of resource list */ | |
2ce9dde0 MR |
128 | __u32 list_handle; |
129 | __u32 _pad; | |
81629cba AD |
130 | }; |
131 | ||
132 | union drm_amdgpu_bo_list { | |
133 | struct drm_amdgpu_bo_list_in in; | |
134 | struct drm_amdgpu_bo_list_out out; | |
135 | }; | |
136 | ||
137 | /* context related */ | |
138 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 | |
139 | #define AMDGPU_CTX_OP_FREE_CTX 2 | |
140 | #define AMDGPU_CTX_OP_QUERY_STATE 3 | |
141 | ||
d94aed5a MO |
142 | /* GPU reset status */ |
143 | #define AMDGPU_CTX_NO_RESET 0 | |
675da0dd CK |
144 | /* this the context caused it */ |
145 | #define AMDGPU_CTX_GUILTY_RESET 1 | |
146 | /* some other context caused it */ | |
147 | #define AMDGPU_CTX_INNOCENT_RESET 2 | |
148 | /* unknown cause */ | |
149 | #define AMDGPU_CTX_UNKNOWN_RESET 3 | |
d94aed5a | 150 | |
81629cba | 151 | struct drm_amdgpu_ctx_in { |
675da0dd | 152 | /** AMDGPU_CTX_OP_* */ |
2ce9dde0 | 153 | __u32 op; |
675da0dd | 154 | /** For future use, no flags defined so far */ |
2ce9dde0 MR |
155 | __u32 flags; |
156 | __u32 ctx_id; | |
157 | __u32 _pad; | |
81629cba AD |
158 | }; |
159 | ||
160 | union drm_amdgpu_ctx_out { | |
161 | struct { | |
2ce9dde0 MR |
162 | __u32 ctx_id; |
163 | __u32 _pad; | |
81629cba AD |
164 | } alloc; |
165 | ||
166 | struct { | |
675da0dd | 167 | /** For future use, no flags defined so far */ |
2ce9dde0 | 168 | __u64 flags; |
d94aed5a | 169 | /** Number of resets caused by this context so far. */ |
2ce9dde0 | 170 | __u32 hangs; |
d94aed5a | 171 | /** Reset status since the last call of the ioctl. */ |
2ce9dde0 | 172 | __u32 reset_status; |
81629cba AD |
173 | } state; |
174 | }; | |
175 | ||
176 | union drm_amdgpu_ctx { | |
177 | struct drm_amdgpu_ctx_in in; | |
178 | union drm_amdgpu_ctx_out out; | |
179 | }; | |
180 | ||
181 | /* | |
182 | * This is not a reliable API and you should expect it to fail for any | |
183 | * number of reasons and have fallback path that do not use userptr to | |
184 | * perform any operation. | |
185 | */ | |
186 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) | |
187 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) | |
188 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) | |
189 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) | |
190 | ||
191 | struct drm_amdgpu_gem_userptr { | |
2ce9dde0 MR |
192 | __u64 addr; |
193 | __u64 size; | |
675da0dd | 194 | /* AMDGPU_GEM_USERPTR_* */ |
2ce9dde0 | 195 | __u32 flags; |
675da0dd | 196 | /* Resulting GEM handle */ |
2ce9dde0 | 197 | __u32 handle; |
81629cba AD |
198 | }; |
199 | ||
fbd76d59 MO |
200 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ |
201 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 | |
202 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf | |
203 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 | |
204 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f | |
205 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 | |
206 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 | |
207 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 | |
208 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 | |
209 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 | |
210 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 | |
211 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 | |
212 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 | |
213 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 | |
214 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 | |
215 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 | |
216 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 | |
217 | ||
218 | #define AMDGPU_TILING_SET(field, value) \ | |
219 | (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) | |
220 | #define AMDGPU_TILING_GET(value, field) \ | |
221 | (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) | |
81629cba AD |
222 | |
223 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 | |
224 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 | |
225 | ||
226 | /** The same structure is shared for input/output */ | |
227 | struct drm_amdgpu_gem_metadata { | |
675da0dd | 228 | /** GEM Object handle */ |
2ce9dde0 | 229 | __u32 handle; |
675da0dd | 230 | /** Do we want get or set metadata */ |
2ce9dde0 | 231 | __u32 op; |
81629cba | 232 | struct { |
675da0dd | 233 | /** For future use, no flags defined so far */ |
2ce9dde0 | 234 | __u64 flags; |
675da0dd | 235 | /** family specific tiling info */ |
2ce9dde0 MR |
236 | __u64 tiling_info; |
237 | __u32 data_size_bytes; | |
238 | __u32 data[64]; | |
81629cba AD |
239 | } data; |
240 | }; | |
241 | ||
242 | struct drm_amdgpu_gem_mmap_in { | |
675da0dd | 243 | /** the GEM object handle */ |
2ce9dde0 MR |
244 | __u32 handle; |
245 | __u32 _pad; | |
81629cba AD |
246 | }; |
247 | ||
248 | struct drm_amdgpu_gem_mmap_out { | |
675da0dd | 249 | /** mmap offset from the vma offset manager */ |
2ce9dde0 | 250 | __u64 addr_ptr; |
81629cba AD |
251 | }; |
252 | ||
253 | union drm_amdgpu_gem_mmap { | |
254 | struct drm_amdgpu_gem_mmap_in in; | |
255 | struct drm_amdgpu_gem_mmap_out out; | |
256 | }; | |
257 | ||
258 | struct drm_amdgpu_gem_wait_idle_in { | |
675da0dd | 259 | /** GEM object handle */ |
2ce9dde0 | 260 | __u32 handle; |
675da0dd | 261 | /** For future use, no flags defined so far */ |
2ce9dde0 | 262 | __u32 flags; |
675da0dd | 263 | /** Absolute timeout to wait */ |
2ce9dde0 | 264 | __u64 timeout; |
81629cba AD |
265 | }; |
266 | ||
267 | struct drm_amdgpu_gem_wait_idle_out { | |
675da0dd | 268 | /** BO status: 0 - BO is idle, 1 - BO is busy */ |
2ce9dde0 | 269 | __u32 status; |
675da0dd | 270 | /** Returned current memory domain */ |
2ce9dde0 | 271 | __u32 domain; |
81629cba AD |
272 | }; |
273 | ||
274 | union drm_amdgpu_gem_wait_idle { | |
275 | struct drm_amdgpu_gem_wait_idle_in in; | |
276 | struct drm_amdgpu_gem_wait_idle_out out; | |
277 | }; | |
278 | ||
279 | struct drm_amdgpu_wait_cs_in { | |
675da0dd | 280 | /** Command submission handle */ |
2ce9dde0 | 281 | __u64 handle; |
675da0dd | 282 | /** Absolute timeout to wait */ |
2ce9dde0 MR |
283 | __u64 timeout; |
284 | __u32 ip_type; | |
285 | __u32 ip_instance; | |
286 | __u32 ring; | |
287 | __u32 ctx_id; | |
81629cba AD |
288 | }; |
289 | ||
290 | struct drm_amdgpu_wait_cs_out { | |
675da0dd | 291 | /** CS status: 0 - CS completed, 1 - CS still busy */ |
2ce9dde0 | 292 | __u64 status; |
81629cba AD |
293 | }; |
294 | ||
295 | union drm_amdgpu_wait_cs { | |
296 | struct drm_amdgpu_wait_cs_in in; | |
297 | struct drm_amdgpu_wait_cs_out out; | |
298 | }; | |
299 | ||
675da0dd CK |
300 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
301 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 | |
302 | ||
81629cba AD |
303 | /* Sets or returns a value associated with a buffer. */ |
304 | struct drm_amdgpu_gem_op { | |
675da0dd | 305 | /** GEM object handle */ |
2ce9dde0 | 306 | __u32 handle; |
675da0dd | 307 | /** AMDGPU_GEM_OP_* */ |
2ce9dde0 | 308 | __u32 op; |
675da0dd | 309 | /** Input or return value */ |
2ce9dde0 | 310 | __u64 value; |
81629cba AD |
311 | }; |
312 | ||
81629cba AD |
313 | #define AMDGPU_VA_OP_MAP 1 |
314 | #define AMDGPU_VA_OP_UNMAP 2 | |
315 | ||
fc220f65 CK |
316 | /* Delay the page table update till the next CS */ |
317 | #define AMDGPU_VM_DELAY_UPDATE (1 << 0) | |
318 | ||
81629cba AD |
319 | /* Mapping flags */ |
320 | /* readable mapping */ | |
321 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) | |
322 | /* writable mapping */ | |
323 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) | |
324 | /* executable mapping, new for VI */ | |
325 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) | |
326 | ||
34b5f6a6 | 327 | struct drm_amdgpu_gem_va { |
675da0dd | 328 | /** GEM object handle */ |
2ce9dde0 MR |
329 | __u32 handle; |
330 | __u32 _pad; | |
675da0dd | 331 | /** AMDGPU_VA_OP_* */ |
2ce9dde0 | 332 | __u32 operation; |
675da0dd | 333 | /** AMDGPU_VM_PAGE_* */ |
2ce9dde0 | 334 | __u32 flags; |
675da0dd | 335 | /** va address to assign . Must be correctly aligned.*/ |
2ce9dde0 | 336 | __u64 va_address; |
675da0dd | 337 | /** Specify offset inside of BO to assign. Must be correctly aligned.*/ |
2ce9dde0 | 338 | __u64 offset_in_bo; |
675da0dd | 339 | /** Specify mapping size. Must be correctly aligned. */ |
2ce9dde0 | 340 | __u64 map_size; |
81629cba AD |
341 | }; |
342 | ||
81629cba AD |
343 | #define AMDGPU_HW_IP_GFX 0 |
344 | #define AMDGPU_HW_IP_COMPUTE 1 | |
345 | #define AMDGPU_HW_IP_DMA 2 | |
346 | #define AMDGPU_HW_IP_UVD 3 | |
347 | #define AMDGPU_HW_IP_VCE 4 | |
348 | #define AMDGPU_HW_IP_NUM 5 | |
349 | ||
350 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 | |
351 | ||
352 | #define AMDGPU_CHUNK_ID_IB 0x01 | |
353 | #define AMDGPU_CHUNK_ID_FENCE 0x02 | |
2b48d323 | 354 | #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 |
675da0dd | 355 | |
81629cba | 356 | struct drm_amdgpu_cs_chunk { |
2ce9dde0 MR |
357 | __u32 chunk_id; |
358 | __u32 length_dw; | |
359 | __u64 chunk_data; | |
81629cba AD |
360 | }; |
361 | ||
362 | struct drm_amdgpu_cs_in { | |
363 | /** Rendering context id */ | |
2ce9dde0 | 364 | __u32 ctx_id; |
81629cba | 365 | /** Handle of resource list associated with CS */ |
2ce9dde0 MR |
366 | __u32 bo_list_handle; |
367 | __u32 num_chunks; | |
368 | __u32 _pad; | |
369 | /** this points to __u64 * which point to cs chunks */ | |
370 | __u64 chunks; | |
81629cba AD |
371 | }; |
372 | ||
373 | struct drm_amdgpu_cs_out { | |
2ce9dde0 | 374 | __u64 handle; |
81629cba AD |
375 | }; |
376 | ||
377 | union drm_amdgpu_cs { | |
675da0dd CK |
378 | struct drm_amdgpu_cs_in in; |
379 | struct drm_amdgpu_cs_out out; | |
81629cba AD |
380 | }; |
381 | ||
382 | /* Specify flags to be used for IB */ | |
383 | ||
384 | /* This IB should be submitted to CE */ | |
385 | #define AMDGPU_IB_FLAG_CE (1<<0) | |
386 | ||
aa2bdb24 | 387 | /* CE Preamble */ |
cab6d57c | 388 | #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) |
aa2bdb24 | 389 | |
81629cba | 390 | struct drm_amdgpu_cs_chunk_ib { |
2ce9dde0 | 391 | __u32 _pad; |
675da0dd | 392 | /** AMDGPU_IB_FLAG_* */ |
2ce9dde0 | 393 | __u32 flags; |
675da0dd | 394 | /** Virtual address to begin IB execution */ |
2ce9dde0 | 395 | __u64 va_start; |
675da0dd | 396 | /** Size of submission */ |
2ce9dde0 | 397 | __u32 ib_bytes; |
675da0dd | 398 | /** HW IP to submit to */ |
2ce9dde0 | 399 | __u32 ip_type; |
675da0dd | 400 | /** HW IP index of the same type to submit to */ |
2ce9dde0 | 401 | __u32 ip_instance; |
675da0dd | 402 | /** Ring index to submit to */ |
2ce9dde0 | 403 | __u32 ring; |
81629cba AD |
404 | }; |
405 | ||
2b48d323 | 406 | struct drm_amdgpu_cs_chunk_dep { |
2ce9dde0 MR |
407 | __u32 ip_type; |
408 | __u32 ip_instance; | |
409 | __u32 ring; | |
410 | __u32 ctx_id; | |
411 | __u64 handle; | |
2b48d323 CK |
412 | }; |
413 | ||
81629cba | 414 | struct drm_amdgpu_cs_chunk_fence { |
2ce9dde0 MR |
415 | __u32 handle; |
416 | __u32 offset; | |
81629cba AD |
417 | }; |
418 | ||
419 | struct drm_amdgpu_cs_chunk_data { | |
420 | union { | |
421 | struct drm_amdgpu_cs_chunk_ib ib_data; | |
422 | struct drm_amdgpu_cs_chunk_fence fence_data; | |
423 | }; | |
424 | }; | |
425 | ||
426 | /** | |
427 | * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU | |
428 | * | |
429 | */ | |
430 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 | |
431 | ||
432 | /* indicate if acceleration can be working */ | |
433 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 | |
434 | /* get the crtc_id from the mode object id? */ | |
435 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 | |
436 | /* query hw IP info */ | |
437 | #define AMDGPU_INFO_HW_IP_INFO 0x02 | |
438 | /* query hw IP instance count for the specified type */ | |
439 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 | |
440 | /* timestamp for GL_ARB_timer_query */ | |
441 | #define AMDGPU_INFO_TIMESTAMP 0x05 | |
442 | /* Query the firmware version */ | |
443 | #define AMDGPU_INFO_FW_VERSION 0x0e | |
444 | /* Subquery id: Query VCE firmware version */ | |
445 | #define AMDGPU_INFO_FW_VCE 0x1 | |
446 | /* Subquery id: Query UVD firmware version */ | |
447 | #define AMDGPU_INFO_FW_UVD 0x2 | |
448 | /* Subquery id: Query GMC firmware version */ | |
449 | #define AMDGPU_INFO_FW_GMC 0x03 | |
450 | /* Subquery id: Query GFX ME firmware version */ | |
451 | #define AMDGPU_INFO_FW_GFX_ME 0x04 | |
452 | /* Subquery id: Query GFX PFP firmware version */ | |
453 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 | |
454 | /* Subquery id: Query GFX CE firmware version */ | |
455 | #define AMDGPU_INFO_FW_GFX_CE 0x06 | |
456 | /* Subquery id: Query GFX RLC firmware version */ | |
457 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 | |
458 | /* Subquery id: Query GFX MEC firmware version */ | |
459 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 | |
460 | /* Subquery id: Query SMC firmware version */ | |
461 | #define AMDGPU_INFO_FW_SMC 0x0a | |
462 | /* Subquery id: Query SDMA firmware version */ | |
463 | #define AMDGPU_INFO_FW_SDMA 0x0b | |
464 | /* number of bytes moved for TTM migration */ | |
465 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f | |
466 | /* the used VRAM size */ | |
467 | #define AMDGPU_INFO_VRAM_USAGE 0x10 | |
468 | /* the used GTT size */ | |
469 | #define AMDGPU_INFO_GTT_USAGE 0x11 | |
470 | /* Information about GDS, etc. resource configuration */ | |
471 | #define AMDGPU_INFO_GDS_CONFIG 0x13 | |
472 | /* Query information about VRAM and GTT domains */ | |
473 | #define AMDGPU_INFO_VRAM_GTT 0x14 | |
474 | /* Query information about register in MMR address space*/ | |
475 | #define AMDGPU_INFO_READ_MMR_REG 0x15 | |
476 | /* Query information about device: rev id, family, etc. */ | |
477 | #define AMDGPU_INFO_DEV_INFO 0x16 | |
478 | /* visible vram usage */ | |
479 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 | |
480 | ||
481 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 | |
482 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff | |
483 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 | |
484 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff | |
485 | ||
486 | /* Input structure for the INFO ioctl */ | |
487 | struct drm_amdgpu_info { | |
488 | /* Where the return value will be stored */ | |
2ce9dde0 | 489 | __u64 return_pointer; |
81629cba AD |
490 | /* The size of the return value. Just like "size" in "snprintf", |
491 | * it limits how many bytes the kernel can write. */ | |
2ce9dde0 | 492 | __u32 return_size; |
81629cba | 493 | /* The query request id. */ |
2ce9dde0 | 494 | __u32 query; |
81629cba AD |
495 | |
496 | union { | |
497 | struct { | |
2ce9dde0 MR |
498 | __u32 id; |
499 | __u32 _pad; | |
81629cba AD |
500 | } mode_crtc; |
501 | ||
502 | struct { | |
503 | /** AMDGPU_HW_IP_* */ | |
2ce9dde0 | 504 | __u32 type; |
81629cba | 505 | /** |
675da0dd CK |
506 | * Index of the IP if there are more IPs of the same |
507 | * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. | |
81629cba | 508 | */ |
2ce9dde0 | 509 | __u32 ip_instance; |
81629cba AD |
510 | } query_hw_ip; |
511 | ||
512 | struct { | |
2ce9dde0 | 513 | __u32 dword_offset; |
675da0dd | 514 | /** number of registers to read */ |
2ce9dde0 MR |
515 | __u32 count; |
516 | __u32 instance; | |
675da0dd | 517 | /** For future use, no flags defined so far */ |
2ce9dde0 | 518 | __u32 flags; |
81629cba AD |
519 | } read_mmr_reg; |
520 | ||
521 | struct { | |
522 | /** AMDGPU_INFO_FW_* */ | |
2ce9dde0 | 523 | __u32 fw_type; |
675da0dd CK |
524 | /** |
525 | * Index of the IP if there are more IPs of | |
526 | * the same type. | |
527 | */ | |
2ce9dde0 | 528 | __u32 ip_instance; |
81629cba AD |
529 | /** |
530 | * Index of the engine. Whether this is used depends | |
531 | * on the firmware type. (e.g. MEC, SDMA) | |
532 | */ | |
2ce9dde0 MR |
533 | __u32 index; |
534 | __u32 _pad; | |
81629cba AD |
535 | } query_fw; |
536 | }; | |
537 | }; | |
538 | ||
539 | struct drm_amdgpu_info_gds { | |
540 | /** GDS GFX partition size */ | |
2ce9dde0 | 541 | __u32 gds_gfx_partition_size; |
81629cba | 542 | /** GDS compute partition size */ |
2ce9dde0 | 543 | __u32 compute_partition_size; |
81629cba | 544 | /** total GDS memory size */ |
2ce9dde0 | 545 | __u32 gds_total_size; |
81629cba | 546 | /** GWS size per GFX partition */ |
2ce9dde0 | 547 | __u32 gws_per_gfx_partition; |
81629cba | 548 | /** GSW size per compute partition */ |
2ce9dde0 | 549 | __u32 gws_per_compute_partition; |
81629cba | 550 | /** OA size per GFX partition */ |
2ce9dde0 | 551 | __u32 oa_per_gfx_partition; |
81629cba | 552 | /** OA size per compute partition */ |
2ce9dde0 MR |
553 | __u32 oa_per_compute_partition; |
554 | __u32 _pad; | |
81629cba AD |
555 | }; |
556 | ||
557 | struct drm_amdgpu_info_vram_gtt { | |
2ce9dde0 MR |
558 | __u64 vram_size; |
559 | __u64 vram_cpu_accessible_size; | |
560 | __u64 gtt_size; | |
81629cba AD |
561 | }; |
562 | ||
563 | struct drm_amdgpu_info_firmware { | |
2ce9dde0 MR |
564 | __u32 ver; |
565 | __u32 feature; | |
81629cba AD |
566 | }; |
567 | ||
81c59f54 KW |
568 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
569 | #define AMDGPU_VRAM_TYPE_GDDR1 1 | |
570 | #define AMDGPU_VRAM_TYPE_DDR2 2 | |
571 | #define AMDGPU_VRAM_TYPE_GDDR3 3 | |
572 | #define AMDGPU_VRAM_TYPE_GDDR4 4 | |
573 | #define AMDGPU_VRAM_TYPE_GDDR5 5 | |
574 | #define AMDGPU_VRAM_TYPE_HBM 6 | |
575 | #define AMDGPU_VRAM_TYPE_DDR3 7 | |
576 | ||
81629cba AD |
577 | struct drm_amdgpu_info_device { |
578 | /** PCI Device ID */ | |
2ce9dde0 | 579 | __u32 device_id; |
81629cba | 580 | /** Internal chip revision: A0, A1, etc.) */ |
2ce9dde0 MR |
581 | __u32 chip_rev; |
582 | __u32 external_rev; | |
81629cba | 583 | /** Revision id in PCI Config space */ |
2ce9dde0 MR |
584 | __u32 pci_rev; |
585 | __u32 family; | |
586 | __u32 num_shader_engines; | |
587 | __u32 num_shader_arrays_per_engine; | |
675da0dd | 588 | /* in KHz */ |
2ce9dde0 MR |
589 | __u32 gpu_counter_freq; |
590 | __u64 max_engine_clock; | |
591 | __u64 max_memory_clock; | |
81629cba | 592 | /* cu information */ |
2ce9dde0 MR |
593 | __u32 cu_active_number; |
594 | __u32 cu_ao_mask; | |
595 | __u32 cu_bitmap[4][4]; | |
81629cba | 596 | /** Render backend pipe mask. One render backend is CB+DB. */ |
2ce9dde0 MR |
597 | __u32 enabled_rb_pipes_mask; |
598 | __u32 num_rb_pipes; | |
599 | __u32 num_hw_gfx_contexts; | |
600 | __u32 _pad; | |
601 | __u64 ids_flags; | |
81629cba | 602 | /** Starting virtual address for UMDs. */ |
2ce9dde0 | 603 | __u64 virtual_address_offset; |
02b70c8c | 604 | /** The maximum virtual address */ |
2ce9dde0 | 605 | __u64 virtual_address_max; |
81629cba | 606 | /** Required alignment of virtual addresses. */ |
2ce9dde0 | 607 | __u32 virtual_address_alignment; |
81629cba | 608 | /** Page table entry - fragment size */ |
2ce9dde0 MR |
609 | __u32 pte_fragment_size; |
610 | __u32 gart_page_size; | |
a101a899 | 611 | /** constant engine ram size*/ |
2ce9dde0 | 612 | __u32 ce_ram_size; |
cab6d57c | 613 | /** video memory type info*/ |
2ce9dde0 | 614 | __u32 vram_type; |
81c59f54 | 615 | /** video memory bit width*/ |
2ce9dde0 | 616 | __u32 vram_bit_width; |
fa92754e | 617 | /* vce harvesting instance */ |
2ce9dde0 | 618 | __u32 vce_harvest_config; |
81629cba AD |
619 | }; |
620 | ||
621 | struct drm_amdgpu_info_hw_ip { | |
622 | /** Version of h/w IP */ | |
2ce9dde0 MR |
623 | __u32 hw_ip_version_major; |
624 | __u32 hw_ip_version_minor; | |
81629cba | 625 | /** Capabilities */ |
2ce9dde0 | 626 | __u64 capabilities_flags; |
71062f43 | 627 | /** command buffer address start alignment*/ |
2ce9dde0 | 628 | __u32 ib_start_alignment; |
71062f43 | 629 | /** command buffer size alignment*/ |
2ce9dde0 | 630 | __u32 ib_size_alignment; |
81629cba | 631 | /** Bitmask of available rings. Bit 0 means ring 0, etc. */ |
2ce9dde0 MR |
632 | __u32 available_rings; |
633 | __u32 _pad; | |
81629cba AD |
634 | }; |
635 | ||
636 | /* | |
637 | * Supported GPU families | |
638 | */ | |
639 | #define AMDGPU_FAMILY_UNKNOWN 0 | |
640 | #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ | |
641 | #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ | |
642 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ | |
39bb0c92 | 643 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ |
81629cba AD |
644 | |
645 | #endif |