Commit | Line | Data |
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1da177e4 | 1 | /** |
b5e89ed5 | 2 | * \file drm.h |
1da177e4 | 3 | * Header for the Direct Rendering Manager |
b5e89ed5 | 4 | * |
1da177e4 LT |
5 | * \author Rickard E. (Rik) Faith <faith@valinux.com> |
6 | * | |
7 | * \par Acknowledgments: | |
8 | * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. | |
9 | */ | |
10 | ||
11 | /* | |
12 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | |
13 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
14 | * All rights reserved. | |
15 | * | |
16 | * Permission is hereby granted, free of charge, to any person obtaining a | |
17 | * copy of this software and associated documentation files (the "Software"), | |
18 | * to deal in the Software without restriction, including without limitation | |
19 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
20 | * and/or sell copies of the Software, and to permit persons to whom the | |
21 | * Software is furnished to do so, subject to the following conditions: | |
22 | * | |
23 | * The above copyright notice and this permission notice (including the next | |
24 | * paragraph) shall be included in all copies or substantial portions of the | |
25 | * Software. | |
26 | * | |
27 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
28 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
29 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
30 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
31 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
32 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
33 | * OTHER DEALINGS IN THE SOFTWARE. | |
34 | */ | |
35 | ||
1da177e4 LT |
36 | #ifndef _DRM_H_ |
37 | #define _DRM_H_ | |
38 | ||
b6330548 | 39 | #if defined(__KERNEL__) || defined(__linux__) |
1a95916f | 40 | |
1d7f83d5 | 41 | #include <linux/types.h> |
1a95916f KH |
42 | #include <asm/ioctl.h> |
43 | typedef unsigned int drm_handle_t; | |
44 | ||
45 | #else /* One of the BSDs */ | |
1da177e4 | 46 | |
1a95916f KH |
47 | #include <sys/ioccom.h> |
48 | #include <sys/types.h> | |
49 | typedef int8_t __s8; | |
50 | typedef uint8_t __u8; | |
51 | typedef int16_t __s16; | |
52 | typedef uint16_t __u16; | |
53 | typedef int32_t __s32; | |
54 | typedef uint32_t __u32; | |
55 | typedef int64_t __s64; | |
56 | typedef uint64_t __u64; | |
57 | typedef unsigned long drm_handle_t; | |
58 | ||
59 | #endif | |
b589ee59 | 60 | |
1da177e4 LT |
61 | #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ |
62 | #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ | |
63 | #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ | |
64 | #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ | |
65 | ||
b3a80a22 DA |
66 | #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ |
67 | #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ | |
1da177e4 LT |
68 | #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) |
69 | #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) | |
70 | #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) | |
71 | ||
b5e89ed5 DA |
72 | typedef unsigned int drm_context_t; |
73 | typedef unsigned int drm_drawable_t; | |
74 | typedef unsigned int drm_magic_t; | |
1da177e4 LT |
75 | |
76 | /** | |
77 | * Cliprect. | |
b5e89ed5 | 78 | * |
1da177e4 LT |
79 | * \warning: If you change this structure, make sure you change |
80 | * XF86DRIClipRectRec in the server as well | |
81 | * | |
82 | * \note KW: Actually it's illegal to change either for | |
83 | * backwards-compatibility reasons. | |
84 | */ | |
c60ce623 | 85 | struct drm_clip_rect { |
b5e89ed5 DA |
86 | unsigned short x1; |
87 | unsigned short y1; | |
88 | unsigned short x2; | |
89 | unsigned short y2; | |
c60ce623 | 90 | }; |
1da177e4 | 91 | |
bea5679f MCA |
92 | /** |
93 | * Drawable information. | |
94 | */ | |
c60ce623 | 95 | struct drm_drawable_info { |
bea5679f | 96 | unsigned int num_rects; |
c60ce623 DA |
97 | struct drm_clip_rect *rects; |
98 | }; | |
bea5679f | 99 | |
1da177e4 LT |
100 | /** |
101 | * Texture region, | |
102 | */ | |
c60ce623 | 103 | struct drm_tex_region { |
b5e89ed5 DA |
104 | unsigned char next; |
105 | unsigned char prev; | |
106 | unsigned char in_use; | |
107 | unsigned char padding; | |
108 | unsigned int age; | |
c60ce623 | 109 | }; |
1da177e4 LT |
110 | |
111 | /** | |
112 | * Hardware lock. | |
113 | * | |
114 | * The lock structure is a simple cache-line aligned integer. To avoid | |
115 | * processor bus contention on a multiprocessor system, there should not be any | |
116 | * other data stored in the same cache line. | |
117 | */ | |
c60ce623 | 118 | struct drm_hw_lock { |
1da177e4 | 119 | __volatile__ unsigned int lock; /**< lock variable */ |
b5e89ed5 | 120 | char padding[60]; /**< Pad to cache line */ |
c60ce623 | 121 | }; |
1da177e4 | 122 | |
1da177e4 LT |
123 | /** |
124 | * DRM_IOCTL_VERSION ioctl argument type. | |
b5e89ed5 | 125 | * |
1da177e4 LT |
126 | * \sa drmGetVersion(). |
127 | */ | |
c60ce623 | 128 | struct drm_version { |
b5e89ed5 DA |
129 | int version_major; /**< Major version */ |
130 | int version_minor; /**< Minor version */ | |
131 | int version_patchlevel; /**< Patch level */ | |
1da177e4 | 132 | size_t name_len; /**< Length of name buffer */ |
b5e89ed5 | 133 | char __user *name; /**< Name of driver */ |
1da177e4 | 134 | size_t date_len; /**< Length of date buffer */ |
b5e89ed5 | 135 | char __user *date; /**< User-space buffer to hold date */ |
1da177e4 | 136 | size_t desc_len; /**< Length of desc buffer */ |
b5e89ed5 | 137 | char __user *desc; /**< User-space buffer to hold desc */ |
c60ce623 | 138 | }; |
1da177e4 | 139 | |
1da177e4 LT |
140 | /** |
141 | * DRM_IOCTL_GET_UNIQUE ioctl argument type. | |
142 | * | |
143 | * \sa drmGetBusid() and drmSetBusId(). | |
144 | */ | |
c60ce623 | 145 | struct drm_unique { |
1da177e4 | 146 | size_t unique_len; /**< Length of unique */ |
b5e89ed5 | 147 | char __user *unique; /**< Unique name for driver instantiation */ |
c60ce623 | 148 | }; |
1da177e4 | 149 | |
c60ce623 | 150 | struct drm_list { |
b5e89ed5 | 151 | int count; /**< Length of user-space structures */ |
c60ce623 DA |
152 | struct drm_version __user *version; |
153 | }; | |
1da177e4 | 154 | |
c60ce623 | 155 | struct drm_block { |
b5e89ed5 | 156 | int unused; |
c60ce623 | 157 | }; |
1da177e4 | 158 | |
1da177e4 LT |
159 | /** |
160 | * DRM_IOCTL_CONTROL ioctl argument type. | |
161 | * | |
162 | * \sa drmCtlInstHandler() and drmCtlUninstHandler(). | |
163 | */ | |
c60ce623 | 164 | struct drm_control { |
1da177e4 LT |
165 | enum { |
166 | DRM_ADD_COMMAND, | |
167 | DRM_RM_COMMAND, | |
168 | DRM_INST_HANDLER, | |
169 | DRM_UNINST_HANDLER | |
b5e89ed5 DA |
170 | } func; |
171 | int irq; | |
c60ce623 | 172 | }; |
1da177e4 | 173 | |
1da177e4 LT |
174 | /** |
175 | * Type of memory to map. | |
176 | */ | |
c60ce623 | 177 | enum drm_map_type { |
b5e89ed5 DA |
178 | _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ |
179 | _DRM_REGISTERS = 1, /**< no caching, no core dump */ | |
180 | _DRM_SHM = 2, /**< shared, cached */ | |
181 | _DRM_AGP = 3, /**< AGP/GART */ | |
2d0f9eaf | 182 | _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ |
b5e89ed5 | 183 | _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */ |
c60ce623 | 184 | }; |
1da177e4 | 185 | |
1da177e4 LT |
186 | /** |
187 | * Memory mapping flags. | |
188 | */ | |
c60ce623 | 189 | enum drm_map_flags { |
b5e89ed5 DA |
190 | _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ |
191 | _DRM_READ_ONLY = 0x02, | |
192 | _DRM_LOCKED = 0x04, /**< shared, cached, locked */ | |
193 | _DRM_KERNEL = 0x08, /**< kernel requires access */ | |
1da177e4 | 194 | _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ |
b5e89ed5 | 195 | _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ |
e3236a11 DA |
196 | _DRM_REMOVABLE = 0x40, /**< Removable mapping */ |
197 | _DRM_DRIVER = 0x80 /**< Managed by driver */ | |
c60ce623 | 198 | }; |
1da177e4 | 199 | |
c60ce623 | 200 | struct drm_ctx_priv_map { |
b5e89ed5 DA |
201 | unsigned int ctx_id; /**< Context requesting private mapping */ |
202 | void *handle; /**< Handle of map */ | |
c60ce623 | 203 | }; |
1da177e4 | 204 | |
1da177e4 LT |
205 | /** |
206 | * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls | |
207 | * argument type. | |
208 | * | |
209 | * \sa drmAddMap(). | |
210 | */ | |
c60ce623 | 211 | struct drm_map { |
b5e89ed5 DA |
212 | unsigned long offset; /**< Requested physical address (0 for SAREA)*/ |
213 | unsigned long size; /**< Requested physical size (bytes) */ | |
c60ce623 DA |
214 | enum drm_map_type type; /**< Type of memory to map */ |
215 | enum drm_map_flags flags; /**< Flags */ | |
b5e89ed5 | 216 | void *handle; /**< User-space: "Handle" to pass to mmap() */ |
1da177e4 | 217 | /**< Kernel-space: kernel-virtual address */ |
b5e89ed5 DA |
218 | int mtrr; /**< MTRR slot used */ |
219 | /* Private data */ | |
c60ce623 | 220 | }; |
1da177e4 | 221 | |
1da177e4 LT |
222 | /** |
223 | * DRM_IOCTL_GET_CLIENT ioctl argument type. | |
224 | */ | |
c60ce623 | 225 | struct drm_client { |
b5e89ed5 DA |
226 | int idx; /**< Which client desired? */ |
227 | int auth; /**< Is client authenticated? */ | |
228 | unsigned long pid; /**< Process ID */ | |
229 | unsigned long uid; /**< User ID */ | |
230 | unsigned long magic; /**< Magic */ | |
231 | unsigned long iocs; /**< Ioctl count */ | |
c60ce623 | 232 | }; |
1da177e4 | 233 | |
c60ce623 | 234 | enum drm_stat_type { |
1da177e4 LT |
235 | _DRM_STAT_LOCK, |
236 | _DRM_STAT_OPENS, | |
237 | _DRM_STAT_CLOSES, | |
238 | _DRM_STAT_IOCTLS, | |
239 | _DRM_STAT_LOCKS, | |
240 | _DRM_STAT_UNLOCKS, | |
241 | _DRM_STAT_VALUE, /**< Generic value */ | |
242 | _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ | |
243 | _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ | |
244 | ||
245 | _DRM_STAT_IRQ, /**< IRQ */ | |
246 | _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ | |
247 | _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ | |
248 | _DRM_STAT_DMA, /**< DMA */ | |
249 | _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ | |
250 | _DRM_STAT_MISSED /**< Missed DMA opportunity */ | |
b5e89ed5 | 251 | /* Add to the *END* of the list */ |
c60ce623 | 252 | }; |
1da177e4 | 253 | |
1da177e4 LT |
254 | /** |
255 | * DRM_IOCTL_GET_STATS ioctl argument type. | |
256 | */ | |
c60ce623 | 257 | struct drm_stats { |
1da177e4 LT |
258 | unsigned long count; |
259 | struct { | |
b5e89ed5 | 260 | unsigned long value; |
c60ce623 | 261 | enum drm_stat_type type; |
1da177e4 | 262 | } data[15]; |
c60ce623 | 263 | }; |
1da177e4 | 264 | |
1da177e4 LT |
265 | /** |
266 | * Hardware locking flags. | |
267 | */ | |
c60ce623 | 268 | enum drm_lock_flags { |
b5e89ed5 DA |
269 | _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ |
270 | _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ | |
271 | _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ | |
272 | _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ | |
273 | /* These *HALT* flags aren't supported yet | |
274 | -- they will be used to support the | |
275 | full-screen DGA-like mode. */ | |
1da177e4 LT |
276 | _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ |
277 | _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ | |
c60ce623 | 278 | }; |
1da177e4 | 279 | |
1da177e4 LT |
280 | /** |
281 | * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. | |
b5e89ed5 | 282 | * |
1da177e4 LT |
283 | * \sa drmGetLock() and drmUnlock(). |
284 | */ | |
c60ce623 | 285 | struct drm_lock { |
b5e89ed5 | 286 | int context; |
c60ce623 DA |
287 | enum drm_lock_flags flags; |
288 | }; | |
1da177e4 | 289 | |
1da177e4 LT |
290 | /** |
291 | * DMA flags | |
292 | * | |
b5e89ed5 | 293 | * \warning |
1da177e4 LT |
294 | * These values \e must match xf86drm.h. |
295 | * | |
296 | * \sa drm_dma. | |
297 | */ | |
c60ce623 | 298 | enum drm_dma_flags { |
b5e89ed5 DA |
299 | /* Flags for DMA buffer dispatch */ |
300 | _DRM_DMA_BLOCK = 0x01, /**< | |
1da177e4 | 301 | * Block until buffer dispatched. |
b5e89ed5 | 302 | * |
1da177e4 LT |
303 | * \note The buffer may not yet have |
304 | * been processed by the hardware -- | |
305 | * getting a hardware lock with the | |
306 | * hardware quiescent will ensure | |
307 | * that the buffer has been | |
308 | * processed. | |
309 | */ | |
310 | _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ | |
b5e89ed5 | 311 | _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ |
1da177e4 | 312 | |
b5e89ed5 DA |
313 | /* Flags for DMA buffer request */ |
314 | _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ | |
315 | _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ | |
316 | _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ | |
c60ce623 | 317 | }; |
1da177e4 | 318 | |
1da177e4 LT |
319 | /** |
320 | * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. | |
321 | * | |
322 | * \sa drmAddBufs(). | |
323 | */ | |
c60ce623 | 324 | struct drm_buf_desc { |
b5e89ed5 DA |
325 | int count; /**< Number of buffers of this size */ |
326 | int size; /**< Size in bytes */ | |
327 | int low_mark; /**< Low water mark */ | |
328 | int high_mark; /**< High water mark */ | |
1da177e4 | 329 | enum { |
b5e89ed5 DA |
330 | _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ |
331 | _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ | |
332 | _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ | |
3417f33e GS |
333 | _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ |
334 | _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ | |
b5e89ed5 DA |
335 | } flags; |
336 | unsigned long agp_start; /**< | |
1da177e4 LT |
337 | * Start address of where the AGP buffers are |
338 | * in the AGP aperture | |
339 | */ | |
c60ce623 | 340 | }; |
1da177e4 | 341 | |
1da177e4 LT |
342 | /** |
343 | * DRM_IOCTL_INFO_BUFS ioctl argument type. | |
344 | */ | |
c60ce623 | 345 | struct drm_buf_info { |
b5e89ed5 | 346 | int count; /**< Entries in list */ |
c60ce623 DA |
347 | struct drm_buf_desc __user *list; |
348 | }; | |
1da177e4 | 349 | |
1da177e4 LT |
350 | /** |
351 | * DRM_IOCTL_FREE_BUFS ioctl argument type. | |
352 | */ | |
c60ce623 | 353 | struct drm_buf_free { |
b5e89ed5 DA |
354 | int count; |
355 | int __user *list; | |
c60ce623 | 356 | }; |
1da177e4 | 357 | |
1da177e4 LT |
358 | /** |
359 | * Buffer information | |
360 | * | |
361 | * \sa drm_buf_map. | |
362 | */ | |
c60ce623 | 363 | struct drm_buf_pub { |
b5e89ed5 DA |
364 | int idx; /**< Index into the master buffer list */ |
365 | int total; /**< Buffer size */ | |
366 | int used; /**< Amount of buffer in use (for DMA) */ | |
367 | void __user *address; /**< Address of buffer */ | |
c60ce623 | 368 | }; |
1da177e4 | 369 | |
1da177e4 LT |
370 | /** |
371 | * DRM_IOCTL_MAP_BUFS ioctl argument type. | |
372 | */ | |
c60ce623 | 373 | struct drm_buf_map { |
b5e89ed5 DA |
374 | int count; /**< Length of the buffer list */ |
375 | void __user *virtual; /**< Mmap'd area in user-virtual */ | |
c60ce623 DA |
376 | struct drm_buf_pub __user *list; /**< Buffer information */ |
377 | }; | |
1da177e4 | 378 | |
1da177e4 LT |
379 | /** |
380 | * DRM_IOCTL_DMA ioctl argument type. | |
381 | * | |
382 | * Indices here refer to the offset into the buffer list in drm_buf_get. | |
383 | * | |
384 | * \sa drmDMA(). | |
385 | */ | |
c60ce623 | 386 | struct drm_dma { |
b5e89ed5 DA |
387 | int context; /**< Context handle */ |
388 | int send_count; /**< Number of buffers to send */ | |
389 | int __user *send_indices; /**< List of handles to buffers */ | |
390 | int __user *send_sizes; /**< Lengths of data to send */ | |
c60ce623 | 391 | enum drm_dma_flags flags; /**< Flags */ |
b5e89ed5 DA |
392 | int request_count; /**< Number of buffers requested */ |
393 | int request_size; /**< Desired size for buffers */ | |
394 | int __user *request_indices; /**< Buffer information */ | |
395 | int __user *request_sizes; | |
396 | int granted_count; /**< Number of buffers granted */ | |
c60ce623 | 397 | }; |
1da177e4 | 398 | |
c60ce623 | 399 | enum drm_ctx_flags { |
1da177e4 | 400 | _DRM_CONTEXT_PRESERVED = 0x01, |
b5e89ed5 | 401 | _DRM_CONTEXT_2DONLY = 0x02 |
c60ce623 | 402 | }; |
1da177e4 | 403 | |
1da177e4 LT |
404 | /** |
405 | * DRM_IOCTL_ADD_CTX ioctl argument type. | |
406 | * | |
407 | * \sa drmCreateContext() and drmDestroyContext(). | |
408 | */ | |
c60ce623 | 409 | struct drm_ctx { |
b5e89ed5 | 410 | drm_context_t handle; |
c60ce623 DA |
411 | enum drm_ctx_flags flags; |
412 | }; | |
1da177e4 | 413 | |
1da177e4 LT |
414 | /** |
415 | * DRM_IOCTL_RES_CTX ioctl argument type. | |
416 | */ | |
c60ce623 | 417 | struct drm_ctx_res { |
b5e89ed5 | 418 | int count; |
c60ce623 DA |
419 | struct drm_ctx __user *contexts; |
420 | }; | |
1da177e4 | 421 | |
1da177e4 LT |
422 | /** |
423 | * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. | |
424 | */ | |
c60ce623 | 425 | struct drm_draw { |
b5e89ed5 | 426 | drm_drawable_t handle; |
c60ce623 | 427 | }; |
1da177e4 | 428 | |
bea5679f MCA |
429 | /** |
430 | * DRM_IOCTL_UPDATE_DRAW ioctl argument type. | |
431 | */ | |
432 | typedef enum { | |
433 | DRM_DRAWABLE_CLIPRECTS, | |
434 | } drm_drawable_info_type_t; | |
435 | ||
c60ce623 | 436 | struct drm_update_draw { |
bea5679f MCA |
437 | drm_drawable_t handle; |
438 | unsigned int type; | |
439 | unsigned int num; | |
440 | unsigned long long data; | |
c60ce623 | 441 | }; |
bea5679f | 442 | |
1da177e4 LT |
443 | /** |
444 | * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. | |
445 | */ | |
c60ce623 | 446 | struct drm_auth { |
b5e89ed5 | 447 | drm_magic_t magic; |
c60ce623 | 448 | }; |
1da177e4 | 449 | |
1da177e4 LT |
450 | /** |
451 | * DRM_IOCTL_IRQ_BUSID ioctl argument type. | |
452 | * | |
453 | * \sa drmGetInterruptFromBusID(). | |
454 | */ | |
c60ce623 | 455 | struct drm_irq_busid { |
1da177e4 LT |
456 | int irq; /**< IRQ number */ |
457 | int busnum; /**< bus number */ | |
458 | int devnum; /**< device number */ | |
459 | int funcnum; /**< function number */ | |
c60ce623 | 460 | }; |
1da177e4 | 461 | |
c60ce623 | 462 | enum drm_vblank_seq_type { |
b5e89ed5 DA |
463 | _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ |
464 | _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ | |
51eab416 DA |
465 | /* bits 1-6 are reserved for high crtcs */ |
466 | _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, | |
c9a9c5e0 | 467 | _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ |
0a3e67a4 | 468 | _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ |
ab285d74 | 469 | _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ |
776c9443 | 470 | _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ |
30b23634 | 471 | _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ |
c60ce623 | 472 | }; |
51eab416 | 473 | #define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 |
1da177e4 | 474 | |
776c9443 | 475 | #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) |
c9a9c5e0 KH |
476 | #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ |
477 | _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) | |
1da177e4 | 478 | |
1da177e4 | 479 | struct drm_wait_vblank_request { |
c60ce623 | 480 | enum drm_vblank_seq_type type; |
1da177e4 LT |
481 | unsigned int sequence; |
482 | unsigned long signal; | |
483 | }; | |
484 | ||
1da177e4 | 485 | struct drm_wait_vblank_reply { |
c60ce623 | 486 | enum drm_vblank_seq_type type; |
1da177e4 LT |
487 | unsigned int sequence; |
488 | long tval_sec; | |
489 | long tval_usec; | |
490 | }; | |
491 | ||
1da177e4 LT |
492 | /** |
493 | * DRM_IOCTL_WAIT_VBLANK ioctl argument type. | |
494 | * | |
495 | * \sa drmWaitVBlank(). | |
496 | */ | |
c60ce623 | 497 | union drm_wait_vblank { |
1da177e4 LT |
498 | struct drm_wait_vblank_request request; |
499 | struct drm_wait_vblank_reply reply; | |
c60ce623 | 500 | }; |
1da177e4 | 501 | |
0a3e67a4 JB |
502 | #define _DRM_PRE_MODESET 1 |
503 | #define _DRM_POST_MODESET 2 | |
504 | ||
505 | /** | |
506 | * DRM_IOCTL_MODESET_CTL ioctl argument type | |
507 | * | |
508 | * \sa drmModesetCtl(). | |
509 | */ | |
510 | struct drm_modeset_ctl { | |
1d7f83d5 AB |
511 | __u32 crtc; |
512 | __u32 cmd; | |
0a3e67a4 JB |
513 | }; |
514 | ||
1da177e4 LT |
515 | /** |
516 | * DRM_IOCTL_AGP_ENABLE ioctl argument type. | |
517 | * | |
518 | * \sa drmAgpEnable(). | |
519 | */ | |
c60ce623 | 520 | struct drm_agp_mode { |
1da177e4 | 521 | unsigned long mode; /**< AGP mode */ |
c60ce623 | 522 | }; |
1da177e4 | 523 | |
1da177e4 LT |
524 | /** |
525 | * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. | |
526 | * | |
527 | * \sa drmAgpAlloc() and drmAgpFree(). | |
528 | */ | |
c60ce623 | 529 | struct drm_agp_buffer { |
1da177e4 LT |
530 | unsigned long size; /**< In bytes -- will round to page boundary */ |
531 | unsigned long handle; /**< Used for binding / unbinding */ | |
b5e89ed5 DA |
532 | unsigned long type; /**< Type of memory to allocate */ |
533 | unsigned long physical; /**< Physical used by i810 */ | |
c60ce623 | 534 | }; |
1da177e4 | 535 | |
1da177e4 LT |
536 | /** |
537 | * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. | |
538 | * | |
539 | * \sa drmAgpBind() and drmAgpUnbind(). | |
540 | */ | |
c60ce623 | 541 | struct drm_agp_binding { |
b5e89ed5 | 542 | unsigned long handle; /**< From drm_agp_buffer */ |
1da177e4 | 543 | unsigned long offset; /**< In bytes -- will round to page boundary */ |
c60ce623 | 544 | }; |
1da177e4 | 545 | |
1da177e4 LT |
546 | /** |
547 | * DRM_IOCTL_AGP_INFO ioctl argument type. | |
548 | * | |
549 | * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), | |
550 | * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), | |
551 | * drmAgpVendorId() and drmAgpDeviceId(). | |
552 | */ | |
c60ce623 | 553 | struct drm_agp_info { |
b5e89ed5 DA |
554 | int agp_version_major; |
555 | int agp_version_minor; | |
556 | unsigned long mode; | |
557 | unsigned long aperture_base; /* physical address */ | |
558 | unsigned long aperture_size; /* bytes */ | |
559 | unsigned long memory_allowed; /* bytes */ | |
560 | unsigned long memory_used; | |
561 | ||
562 | /* PCI information */ | |
1da177e4 LT |
563 | unsigned short id_vendor; |
564 | unsigned short id_device; | |
c60ce623 | 565 | }; |
1da177e4 | 566 | |
1da177e4 LT |
567 | /** |
568 | * DRM_IOCTL_SG_ALLOC ioctl argument type. | |
569 | */ | |
c60ce623 | 570 | struct drm_scatter_gather { |
1da177e4 LT |
571 | unsigned long size; /**< In bytes -- will round to page boundary */ |
572 | unsigned long handle; /**< Used for mapping / unmapping */ | |
c60ce623 | 573 | }; |
1da177e4 LT |
574 | |
575 | /** | |
576 | * DRM_IOCTL_SET_VERSION ioctl argument type. | |
577 | */ | |
c60ce623 | 578 | struct drm_set_version { |
1da177e4 LT |
579 | int drm_di_major; |
580 | int drm_di_minor; | |
581 | int drm_dd_major; | |
582 | int drm_dd_minor; | |
c60ce623 | 583 | }; |
1da177e4 | 584 | |
673a394b EA |
585 | /** DRM_IOCTL_GEM_CLOSE ioctl argument type */ |
586 | struct drm_gem_close { | |
587 | /** Handle of the object to be closed. */ | |
1d7f83d5 AB |
588 | __u32 handle; |
589 | __u32 pad; | |
673a394b EA |
590 | }; |
591 | ||
592 | /** DRM_IOCTL_GEM_FLINK ioctl argument type */ | |
593 | struct drm_gem_flink { | |
594 | /** Handle for the object being named */ | |
1d7f83d5 | 595 | __u32 handle; |
673a394b EA |
596 | |
597 | /** Returned global name */ | |
1d7f83d5 | 598 | __u32 name; |
673a394b EA |
599 | }; |
600 | ||
601 | /** DRM_IOCTL_GEM_OPEN ioctl argument type */ | |
602 | struct drm_gem_open { | |
603 | /** Name of object being opened */ | |
1d7f83d5 | 604 | __u32 name; |
673a394b EA |
605 | |
606 | /** Returned handle for the object */ | |
1d7f83d5 | 607 | __u32 handle; |
673a394b EA |
608 | |
609 | /** Returned size of the object */ | |
1d7f83d5 | 610 | __u64 size; |
673a394b EA |
611 | }; |
612 | ||
a99b57db DL |
613 | #define DRM_CAP_DUMB_BUFFER 0x1 |
614 | #define DRM_CAP_VBLANK_HIGH_CRTC 0x2 | |
615 | #define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 | |
616 | #define DRM_CAP_DUMB_PREFER_SHADOW 0x4 | |
617 | #define DRM_CAP_PRIME 0x5 | |
618 | #define DRM_PRIME_CAP_IMPORT 0x1 | |
619 | #define DRM_PRIME_CAP_EXPORT 0x2 | |
620 | #define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 | |
621 | #define DRM_CAP_ASYNC_PAGE_FLIP 0x7 | |
8716ed4e AD |
622 | #define DRM_CAP_CURSOR_WIDTH 0x8 |
623 | #define DRM_CAP_CURSOR_HEIGHT 0x9 | |
a99b57db | 624 | |
9f35421e BS |
625 | /** DRM_IOCTL_GET_CAP ioctl argument type */ |
626 | struct drm_get_cap { | |
627 | __u64 capability; | |
628 | __u64 value; | |
629 | }; | |
630 | ||
61d8e328 DL |
631 | /** |
632 | * DRM_CLIENT_CAP_STEREO_3D | |
633 | * | |
634 | * if set to 1, the DRM core will expose the stereo 3D capabilities of the | |
635 | * monitor by advertising the supported 3D layouts in the flags of struct | |
636 | * drm_mode_modeinfo. | |
637 | */ | |
638 | #define DRM_CLIENT_CAP_STEREO_3D 1 | |
639 | ||
1c0814fe DL |
640 | /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ |
641 | struct drm_set_client_cap { | |
642 | __u64 capability; | |
643 | __u64 value; | |
644 | }; | |
645 | ||
3248877e DA |
646 | #define DRM_CLOEXEC O_CLOEXEC |
647 | struct drm_prime_handle { | |
648 | __u32 handle; | |
649 | ||
650 | /** Flags.. only applicable for handle->fd */ | |
651 | __u32 flags; | |
652 | ||
653 | /** Returned dmabuf file descriptor */ | |
654 | __s32 fd; | |
655 | }; | |
656 | ||
a1ce3928 | 657 | #include <drm/drm_mode.h> |
f453ba04 | 658 | |
1da177e4 LT |
659 | #define DRM_IOCTL_BASE 'd' |
660 | #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) | |
661 | #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) | |
662 | #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) | |
663 | #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) | |
664 | ||
c60ce623 DA |
665 | #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) |
666 | #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) | |
667 | #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) | |
668 | #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) | |
669 | #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) | |
670 | #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) | |
671 | #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) | |
672 | #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) | |
0a3e67a4 | 673 | #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) |
673a394b EA |
674 | #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) |
675 | #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) | |
676 | #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) | |
9f35421e | 677 | #define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) |
1c0814fe | 678 | #define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap) |
c60ce623 DA |
679 | |
680 | #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) | |
681 | #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) | |
682 | #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) | |
683 | #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) | |
684 | #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) | |
685 | #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) | |
686 | #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) | |
687 | #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) | |
688 | #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) | |
689 | #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) | |
690 | #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) | |
691 | ||
692 | #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) | |
693 | ||
694 | #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) | |
695 | #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) | |
696 | ||
7c1c2871 DA |
697 | #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) |
698 | #define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) | |
699 | ||
c60ce623 DA |
700 | #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) |
701 | #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) | |
702 | #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) | |
703 | #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) | |
704 | #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) | |
705 | #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) | |
706 | #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) | |
707 | #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) | |
708 | #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) | |
709 | #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) | |
710 | #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) | |
711 | #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) | |
712 | #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) | |
1da177e4 | 713 | |
3248877e DA |
714 | #define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) |
715 | #define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) | |
ba4420c2 | 716 | |
1da177e4 LT |
717 | #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) |
718 | #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) | |
c60ce623 DA |
719 | #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) |
720 | #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) | |
721 | #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) | |
722 | #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) | |
723 | #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) | |
724 | #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) | |
1da177e4 | 725 | |
b5543059 | 726 | #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) |
c60ce623 | 727 | #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) |
1da177e4 | 728 | |
c60ce623 | 729 | #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) |
1da177e4 | 730 | |
c60ce623 | 731 | #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) |
bea5679f | 732 | |
f453ba04 DA |
733 | #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) |
734 | #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) | |
735 | #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) | |
736 | #define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) | |
737 | #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) | |
738 | #define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) | |
739 | #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) | |
740 | #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) | |
c55b6b3d VS |
741 | #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */ |
742 | #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */ | |
f453ba04 DA |
743 | |
744 | #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) | |
745 | #define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) | |
746 | #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) | |
747 | #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) | |
748 | #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) | |
749 | #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) | |
d91d8a3f | 750 | #define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) |
884840aa | 751 | #define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) |
f453ba04 | 752 | |
ff72145b DA |
753 | #define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) |
754 | #define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) | |
755 | #define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) | |
8cf5c917 JB |
756 | #define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) |
757 | #define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) | |
758 | #define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) | |
308e5bcb | 759 | #define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) |
c543188a PZ |
760 | #define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) |
761 | #define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) | |
4c813d4d | 762 | #define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) |
ff72145b | 763 | |
1da177e4 LT |
764 | /** |
765 | * Device specific ioctls should only be in their respective headers | |
99da6d86 TH |
766 | * The device specific ioctl range is from 0x40 to 0x99. |
767 | * Generic IOCTLS restart at 0xA0. | |
1da177e4 LT |
768 | * |
769 | * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and | |
770 | * drmCommandReadWrite(). | |
771 | */ | |
772 | #define DRM_COMMAND_BASE 0x40 | |
99da6d86 | 773 | #define DRM_COMMAND_END 0xA0 |
1da177e4 | 774 | |
c9a9c5e0 KH |
775 | /** |
776 | * Header for events written back to userspace on the drm fd. The | |
777 | * type defines the type of event, the length specifies the total | |
778 | * length of the event (including the header), and user_data is | |
779 | * typically a 64 bit value passed with the ioctl that triggered the | |
780 | * event. A read on the drm fd will always only return complete | |
781 | * events, that is, if for example the read buffer is 100 bytes, and | |
782 | * there are two 64 byte events pending, only one will be returned. | |
783 | * | |
784 | * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and | |
785 | * up are chipset specific. | |
786 | */ | |
787 | struct drm_event { | |
788 | __u32 type; | |
789 | __u32 length; | |
790 | }; | |
791 | ||
792 | #define DRM_EVENT_VBLANK 0x01 | |
7bd4d7be | 793 | #define DRM_EVENT_FLIP_COMPLETE 0x02 |
c9a9c5e0 KH |
794 | |
795 | struct drm_event_vblank { | |
796 | struct drm_event base; | |
797 | __u64 user_data; | |
798 | __u32 tv_sec; | |
799 | __u32 tv_usec; | |
800 | __u32 sequence; | |
801 | __u32 reserved; | |
802 | }; | |
803 | ||
c60ce623 DA |
804 | /* typedef area */ |
805 | #ifndef __KERNEL__ | |
806 | typedef struct drm_clip_rect drm_clip_rect_t; | |
807 | typedef struct drm_drawable_info drm_drawable_info_t; | |
808 | typedef struct drm_tex_region drm_tex_region_t; | |
809 | typedef struct drm_hw_lock drm_hw_lock_t; | |
810 | typedef struct drm_version drm_version_t; | |
811 | typedef struct drm_unique drm_unique_t; | |
812 | typedef struct drm_list drm_list_t; | |
813 | typedef struct drm_block drm_block_t; | |
814 | typedef struct drm_control drm_control_t; | |
815 | typedef enum drm_map_type drm_map_type_t; | |
816 | typedef enum drm_map_flags drm_map_flags_t; | |
817 | typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; | |
818 | typedef struct drm_map drm_map_t; | |
819 | typedef struct drm_client drm_client_t; | |
820 | typedef enum drm_stat_type drm_stat_type_t; | |
821 | typedef struct drm_stats drm_stats_t; | |
822 | typedef enum drm_lock_flags drm_lock_flags_t; | |
823 | typedef struct drm_lock drm_lock_t; | |
824 | typedef enum drm_dma_flags drm_dma_flags_t; | |
825 | typedef struct drm_buf_desc drm_buf_desc_t; | |
826 | typedef struct drm_buf_info drm_buf_info_t; | |
827 | typedef struct drm_buf_free drm_buf_free_t; | |
828 | typedef struct drm_buf_pub drm_buf_pub_t; | |
829 | typedef struct drm_buf_map drm_buf_map_t; | |
830 | typedef struct drm_dma drm_dma_t; | |
831 | typedef union drm_wait_vblank drm_wait_vblank_t; | |
832 | typedef struct drm_agp_mode drm_agp_mode_t; | |
833 | typedef enum drm_ctx_flags drm_ctx_flags_t; | |
834 | typedef struct drm_ctx drm_ctx_t; | |
835 | typedef struct drm_ctx_res drm_ctx_res_t; | |
836 | typedef struct drm_draw drm_draw_t; | |
837 | typedef struct drm_update_draw drm_update_draw_t; | |
838 | typedef struct drm_auth drm_auth_t; | |
839 | typedef struct drm_irq_busid drm_irq_busid_t; | |
840 | typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; | |
841 | ||
842 | typedef struct drm_agp_buffer drm_agp_buffer_t; | |
843 | typedef struct drm_agp_binding drm_agp_binding_t; | |
844 | typedef struct drm_agp_info drm_agp_info_t; | |
845 | typedef struct drm_scatter_gather drm_scatter_gather_t; | |
846 | typedef struct drm_set_version drm_set_version_t; | |
847 | #endif | |
848 | ||
1da177e4 | 849 | #endif |