[deliverable/linux.git] / include / uapi / drm / r128_drm.h

/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*-
 * Created: Wed Apr  5 19:24:19 2000 by kevin@precisioninsight.com
 */
/*
 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Gareth Hughes <gareth@valinux.com>
 *    Kevin E. Martin <martin@valinux.com>
 */

#ifndef __R128_DRM_H__
#define __R128_DRM_H__

#include "drm.h"

/* WARNING: If you change any of these defines, make sure to change the
 * defines in the X server file (r128_sarea.h)
 */
#ifndef __R128_SAREA_DEFINES__
#define __R128_SAREA_DEFINES__

/* What needs to be changed for the current vertex buffer?
 */
#define R128_UPLOAD_CONTEXT		0x001
#define R128_UPLOAD_SETUP		0x002
#define R128_UPLOAD_TEX0		0x004
#define R128_UPLOAD_TEX1		0x008
#define R128_UPLOAD_TEX0IMAGES		0x010
#define R128_UPLOAD_TEX1IMAGES		0x020
#define R128_UPLOAD_CORE		0x040
#define R128_UPLOAD_MASKS		0x080
#define R128_UPLOAD_WINDOW		0x100
#define R128_UPLOAD_CLIPRECTS		0x200	/* handled client-side */
#define R128_REQUIRE_QUIESCENCE		0x400
#define R128_UPLOAD_ALL			0x7ff

#define R128_FRONT			0x1
#define R128_BACK			0x2
#define R128_DEPTH			0x4

/* Primitive types
 */
#define R128_POINTS			0x1
#define R128_LINES			0x2
#define R128_LINE_STRIP			0x3
#define R128_TRIANGLES			0x4
#define R128_TRIANGLE_FAN		0x5
#define R128_TRIANGLE_STRIP		0x6

/* Vertex/indirect buffer size
 */
#define R128_BUFFER_SIZE		16384

/* Byte offsets for indirect buffer data
 */
#define R128_INDEX_PRIM_OFFSET		20
#define R128_HOSTDATA_BLIT_OFFSET	32

/* Keep these small for testing.
 */
#define R128_NR_SAREA_CLIPRECTS		12

/* There are 2 heaps (local/AGP).  Each region within a heap is a
 *  minimum of 64k, and there are at most 64 of them per heap.
 */
#define R128_LOCAL_TEX_HEAP		0
#define R128_AGP_TEX_HEAP		1
#define R128_NR_TEX_HEAPS		2
#define R128_NR_TEX_REGIONS		64
#define R128_LOG_TEX_GRANULARITY	16

#define R128_NR_CONTEXT_REGS		12

#define R128_MAX_TEXTURE_LEVELS		11
#define R128_MAX_TEXTURE_UNITS		2

#endif				/* __R128_SAREA_DEFINES__ */

typedef struct {
	/* Context state - can be written in one large chunk */
	unsigned int dst_pitch_offset_c;
	unsigned int dp_gui_master_cntl_c;
	unsigned int sc_top_left_c;
	unsigned int sc_bottom_right_c;
	unsigned int z_offset_c;
	unsigned int z_pitch_c;
	unsigned int z_sten_cntl_c;
	unsigned int tex_cntl_c;
	unsigned int misc_3d_state_cntl_reg;
	unsigned int texture_clr_cmp_clr_c;
	unsigned int texture_clr_cmp_msk_c;
	unsigned int fog_color_c;

	/* Texture state */
	unsigned int tex_size_pitch_c;
	unsigned int constant_color_c;

	/* Setup state */
	unsigned int pm4_vc_fpu_setup;
	unsigned int setup_cntl;

	/* Mask state */
	unsigned int dp_write_mask;
	unsigned int sten_ref_mask_c;
	unsigned int plane_3d_mask_c;

	/* Window state */
	unsigned int window_xy_offset;

	/* Core state */
	unsigned int scale_3d_cntl;
} drm_r128_context_regs_t;

/* Setup registers for each texture unit
 */
typedef struct {
	unsigned int tex_cntl;
	unsigned int tex_combine_cntl;
	unsigned int tex_size_pitch;
	unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
	unsigned int tex_border_color;
} drm_r128_texture_regs_t;

typedef struct drm_r128_sarea {
	/* The channel for communication of state information to the kernel
	 * on firing a vertex buffer.
	 */
	drm_r128_context_regs_t context_state;
	drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
	unsigned int dirty;
	unsigned int vertsize;
	unsigned int vc_format;

	/* The current cliprects, or a subset thereof.
	 */
	struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
	unsigned int nbox;

	/* Counters for client-side throttling of rendering clients.
	 */
	unsigned int last_frame;
	unsigned int last_dispatch;

	struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
	unsigned int tex_age[R128_NR_TEX_HEAPS];
	int ctx_owner;
	int pfAllowPageFlip;	/* number of 3d windows (0,1,2 or more) */
	int pfCurrentPage;	/* which buffer is being displayed? */
} drm_r128_sarea_t;

/* WARNING: If you change any of these defines, make sure to change the
 * defines in the Xserver file (xf86drmR128.h)
 */

/* Rage 128 specific ioctls
 * The device specific ioctl range is 0x40 to 0x79.
 */
#define DRM_R128_INIT       0x00
#define DRM_R128_CCE_START  0x01
#define DRM_R128_CCE_STOP   0x02
#define DRM_R128_CCE_RESET  0x03
#define DRM_R128_CCE_IDLE   0x04
/* 0x05 not used */
#define DRM_R128_RESET      0x06
#define DRM_R128_SWAP       0x07
#define DRM_R128_CLEAR      0x08
#define DRM_R128_VERTEX     0x09
#define DRM_R128_INDICES    0x0a
#define DRM_R128_BLIT       0x0b
#define DRM_R128_DEPTH      0x0c
#define DRM_R128_STIPPLE    0x0d
/* 0x0e not used */
#define DRM_R128_INDIRECT   0x0f
#define DRM_R128_FULLSCREEN 0x10
#define DRM_R128_CLEAR2     0x11
#define DRM_R128_GETPARAM   0x12
#define DRM_R128_FLIP       0x13

#define DRM_IOCTL_R128_INIT       DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
#define DRM_IOCTL_R128_CCE_START  DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_START)
#define DRM_IOCTL_R128_CCE_STOP   DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
#define DRM_IOCTL_R128_CCE_RESET  DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
#define DRM_IOCTL_R128_CCE_IDLE   DRM_IO(  DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
/* 0x05 not used */
#define DRM_IOCTL_R128_RESET      DRM_IO(  DRM_COMMAND_BASE + DRM_R128_RESET)
#define DRM_IOCTL_R128_SWAP       DRM_IO(  DRM_COMMAND_BASE + DRM_R128_SWAP)
#define DRM_IOCTL_R128_CLEAR      DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
#define DRM_IOCTL_R128_VERTEX     DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
#define DRM_IOCTL_R128_INDICES    DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
#define DRM_IOCTL_R128_BLIT       DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
#define DRM_IOCTL_R128_DEPTH      DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
#define DRM_IOCTL_R128_STIPPLE    DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
/* 0x0e not used */
#define DRM_IOCTL_R128_INDIRECT   DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
#define DRM_IOCTL_R128_CLEAR2     DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
#define DRM_IOCTL_R128_GETPARAM   DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
#define DRM_IOCTL_R128_FLIP       DRM_IO(  DRM_COMMAND_BASE + DRM_R128_FLIP)

typedef struct drm_r128_init {
	enum {
		R128_INIT_CCE = 0x01,
		R128_CLEANUP_CCE = 0x02
	} func;
	unsigned long sarea_priv_offset;
	int is_pci;
	int cce_mode;
	int cce_secure;
	int ring_size;
	int usec_timeout;

	unsigned int fb_bpp;
	unsigned int front_offset, front_pitch;
	unsigned int back_offset, back_pitch;
	unsigned int depth_bpp;
	unsigned int depth_offset, depth_pitch;
	unsigned int span_offset;

	unsigned long fb_offset;
	unsigned long mmio_offset;
	unsigned long ring_offset;
	unsigned long ring_rptr_offset;
	unsigned long buffers_offset;
	unsigned long agp_textures_offset;
} drm_r128_init_t;

typedef struct drm_r128_cce_stop {
	int flush;
	int idle;
} drm_r128_cce_stop_t;

typedef struct drm_r128_clear {
	unsigned int flags;
	unsigned int clear_color;
	unsigned int clear_depth;
	unsigned int color_mask;
	unsigned int depth_mask;
} drm_r128_clear_t;

typedef struct drm_r128_vertex {
	int prim;
	int idx;		/* Index of vertex buffer */
	int count;		/* Number of vertices in buffer */
	int discard;		/* Client finished with buffer? */
} drm_r128_vertex_t;

typedef struct drm_r128_indices {
	int prim;
	int idx;
	int start;
	int end;
	int discard;		/* Client finished with buffer? */
} drm_r128_indices_t;

typedef struct drm_r128_blit {
	int idx;
	int pitch;
	int offset;
	int format;
	unsigned short x, y;
	unsigned short width, height;
} drm_r128_blit_t;

typedef struct drm_r128_depth {
	enum {
		R128_WRITE_SPAN = 0x01,
		R128_WRITE_PIXELS = 0x02,
		R128_READ_SPAN = 0x03,
		R128_READ_PIXELS = 0x04
	} func;
	int n;
	int __user *x;
	int __user *y;
	unsigned int __user *buffer;
	unsigned char __user *mask;
} drm_r128_depth_t;

typedef struct drm_r128_stipple {
	unsigned int __user *mask;
} drm_r128_stipple_t;

typedef struct drm_r128_indirect {
	int idx;
	int start;
	int end;
	int discard;
} drm_r128_indirect_t;

typedef struct drm_r128_fullscreen {
	enum {
		R128_INIT_FULLSCREEN = 0x01,
		R128_CLEANUP_FULLSCREEN = 0x02
	} func;
} drm_r128_fullscreen_t;

/* 2.3: An ioctl to get parameters that aren't available to the 3d
 * client any other way.
 */
#define R128_PARAM_IRQ_NR            1

typedef struct drm_r128_getparam {
	int param;
	void __user *value;
} drm_r128_getparam_t;

#endif
Commit	Line	Data
1da177e4 LT	1	/* r128_drm.h -- Public header for the r128 driver -- linux-c --
1da177e4 LT	2	* Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
f26c473c	3	*/
83a9e29b DA	4	/*
83a9e29b DA	5	* Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
1da177e4 LT	6	* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
	7	* All rights reserved.
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a
	10	* copy of this software and associated documentation files (the "Software"),
	11	* to deal in the Software without restriction, including without limitation
	12	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	13	* and/or sell copies of the Software, and to permit persons to whom the
	14	* Software is furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice (including the next
	17	* paragraph) shall be included in all copies or substantial portions of the
	18	* Software.
	19	*
	20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	21	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	22	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	23	* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	24	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	25	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	26	* DEALINGS IN THE SOFTWARE.
	27	*
	28	* Authors:
	29	* Gareth Hughes <gareth@valinux.com>
	30	* Kevin E. Martin <martin@valinux.com>
	31	*/
	32
	33	#ifndef __R128_DRM_H__
	34	#define __R128_DRM_H__
	35
355f4780	36	#include "drm.h"
0aa4a4b8	37
1da177e4 LT	38	/* WARNING: If you change any of these defines, make sure to change the
	39	* defines in the X server file (r128_sarea.h)
	40	*/
	41	#ifndef __R128_SAREA_DEFINES__
	42	#define __R128_SAREA_DEFINES__
	43
	44	/* What needs to be changed for the current vertex buffer?
	45	*/
	46	#define R128_UPLOAD_CONTEXT 0x001
	47	#define R128_UPLOAD_SETUP 0x002
	48	#define R128_UPLOAD_TEX0 0x004
	49	#define R128_UPLOAD_TEX1 0x008
	50	#define R128_UPLOAD_TEX0IMAGES 0x010
	51	#define R128_UPLOAD_TEX1IMAGES 0x020
	52	#define R128_UPLOAD_CORE 0x040
	53	#define R128_UPLOAD_MASKS 0x080
	54	#define R128_UPLOAD_WINDOW 0x100
	55	#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */
	56	#define R128_REQUIRE_QUIESCENCE 0x400
	57	#define R128_UPLOAD_ALL 0x7ff
	58
	59	#define R128_FRONT 0x1
	60	#define R128_BACK 0x2
	61	#define R128_DEPTH 0x4
	62
	63	/* Primitive types
	64	*/
	65	#define R128_POINTS 0x1
	66	#define R128_LINES 0x2
	67	#define R128_LINE_STRIP 0x3
	68	#define R128_TRIANGLES 0x4
	69	#define R128_TRIANGLE_FAN 0x5
	70	#define R128_TRIANGLE_STRIP 0x6
	71
	72	/* Vertex/indirect buffer size
	73	*/
	74	#define R128_BUFFER_SIZE 16384
	75
	76	/* Byte offsets for indirect buffer data
	77	*/
	78	#define R128_INDEX_PRIM_OFFSET 20
	79	#define R128_HOSTDATA_BLIT_OFFSET 32
	80
	81	/* Keep these small for testing.
	82	*/
	83	#define R128_NR_SAREA_CLIPRECTS 12
	84
	85	/* There are 2 heaps (local/AGP). Each region within a heap is a
	86	* minimum of 64k, and there are at most 64 of them per heap.
	87	*/
	88	#define R128_LOCAL_TEX_HEAP 0
	89	#define R128_AGP_TEX_HEAP 1
	90	#define R128_NR_TEX_HEAPS 2
	91	#define R128_NR_TEX_REGIONS 64
	92	#define R128_LOG_TEX_GRANULARITY 16
	93
	94	#define R128_NR_CONTEXT_REGS 12
	95
	96	#define R128_MAX_TEXTURE_LEVELS 11
	97	#define R128_MAX_TEXTURE_UNITS 2
	98
b5e89ed5	99	#endif /* __R128_SAREA_DEFINES__ */
1da177e4 LT	100
	101	typedef struct {
	102	/* Context state - can be written in one large chunk */
	103	unsigned int dst_pitch_offset_c;
	104	unsigned int dp_gui_master_cntl_c;
	105	unsigned int sc_top_left_c;
	106	unsigned int sc_bottom_right_c;
	107	unsigned int z_offset_c;
	108	unsigned int z_pitch_c;
	109	unsigned int z_sten_cntl_c;
	110	unsigned int tex_cntl_c;
	111	unsigned int misc_3d_state_cntl_reg;
	112	unsigned int texture_clr_cmp_clr_c;
	113	unsigned int texture_clr_cmp_msk_c;
	114	unsigned int fog_color_c;
	115
	116	/* Texture state */
	117	unsigned int tex_size_pitch_c;
	118	unsigned int constant_color_c;
	119
	120	/* Setup state */
	121	unsigned int pm4_vc_fpu_setup;
	122	unsigned int setup_cntl;
	123
	124	/* Mask state */
	125	unsigned int dp_write_mask;
	126	unsigned int sten_ref_mask_c;
	127	unsigned int plane_3d_mask_c;
	128
	129	/* Window state */
	130	unsigned int window_xy_offset;
	131
	132	/* Core state */
	133	unsigned int scale_3d_cntl;
	134	} drm_r128_context_regs_t;
	135
	136	/* Setup registers for each texture unit
	137	*/
	138	typedef struct {
	139	unsigned int tex_cntl;
	140	unsigned int tex_combine_cntl;
	141	unsigned int tex_size_pitch;
	142	unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
	143	unsigned int tex_border_color;
	144	} drm_r128_texture_regs_t;
	145
1da177e4 LT	146	typedef struct drm_r128_sarea {
	147	/* The channel for communication of state information to the kernel
	148	* on firing a vertex buffer.
	149	*/
	150	drm_r128_context_regs_t context_state;
	151	drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
	152	unsigned int dirty;
	153	unsigned int vertsize;
	154	unsigned int vc_format;
	155
	156	/* The current cliprects, or a subset thereof.
	157	*/
eddca551	158	struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
1da177e4 LT	159	unsigned int nbox;
	160
	161	/* Counters for client-side throttling of rendering clients.
	162	*/
	163	unsigned int last_frame;
	164	unsigned int last_dispatch;
	165
eddca551	166	struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
1da177e4 LT	167	unsigned int tex_age[R128_NR_TEX_HEAPS];
1da177e4 LT	168	int ctx_owner;
b5e89ed5 DA	169	int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */
b5e89ed5 DA	170	int pfCurrentPage; /* which buffer is being displayed? */
1da177e4 LT	171	} drm_r128_sarea_t;
1da177e4 LT	172
1da177e4 LT	173	/* WARNING: If you change any of these defines, make sure to change the
	174	* defines in the Xserver file (xf86drmR128.h)
	175	*/
	176
	177	/* Rage 128 specific ioctls
	178	* The device specific ioctl range is 0x40 to 0x79.
	179	*/
	180	#define DRM_R128_INIT 0x00
	181	#define DRM_R128_CCE_START 0x01
	182	#define DRM_R128_CCE_STOP 0x02
	183	#define DRM_R128_CCE_RESET 0x03
	184	#define DRM_R128_CCE_IDLE 0x04
	185	/* 0x05 not used */
	186	#define DRM_R128_RESET 0x06
	187	#define DRM_R128_SWAP 0x07
	188	#define DRM_R128_CLEAR 0x08
	189	#define DRM_R128_VERTEX 0x09
	190	#define DRM_R128_INDICES 0x0a
	191	#define DRM_R128_BLIT 0x0b
	192	#define DRM_R128_DEPTH 0x0c
	193	#define DRM_R128_STIPPLE 0x0d
	194	/* 0x0e not used */
	195	#define DRM_R128_INDIRECT 0x0f
	196	#define DRM_R128_FULLSCREEN 0x10
	197	#define DRM_R128_CLEAR2 0x11
	198	#define DRM_R128_GETPARAM 0x12
	199	#define DRM_R128_FLIP 0x13
	200
	201	#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
	202	#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START)
	203	#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
	204	#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
	205	#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
	206	/* 0x05 not used */
	207	#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET)
	208	#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP)
	209	#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
	210	#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
	211	#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
	212	#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
	213	#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
	214	#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
	215	/* 0x0e not used */
	216	#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
	217	#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
	218	#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
24d10942	219	#define DRM_IOCTL_R128_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
1da177e4 LT	220	#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP)
	221
	222	typedef struct drm_r128_init {
	223	enum {
b5e89ed5	224	R128_INIT_CCE = 0x01,
1da177e4 LT	225	R128_CLEANUP_CCE = 0x02
1da177e4 LT	226	} func;
1da177e4	227	unsigned long sarea_priv_offset;
1da177e4 LT	228	int is_pci;
	229	int cce_mode;
	230	int cce_secure;
	231	int ring_size;
	232	int usec_timeout;
	233
	234	unsigned int fb_bpp;
	235	unsigned int front_offset, front_pitch;
	236	unsigned int back_offset, back_pitch;
	237	unsigned int depth_bpp;
	238	unsigned int depth_offset, depth_pitch;
	239	unsigned int span_offset;
	240
1da177e4 LT	241	unsigned long fb_offset;
	242	unsigned long mmio_offset;
	243	unsigned long ring_offset;
	244	unsigned long ring_rptr_offset;
	245	unsigned long buffers_offset;
	246	unsigned long agp_textures_offset;
1da177e4 LT	247	} drm_r128_init_t;
	248
	249	typedef struct drm_r128_cce_stop {
	250	int flush;
	251	int idle;
	252	} drm_r128_cce_stop_t;
	253
	254	typedef struct drm_r128_clear {
	255	unsigned int flags;
1da177e4 LT	256	unsigned int clear_color;
1da177e4 LT	257	unsigned int clear_depth;
1da177e4 LT	258	unsigned int color_mask;
1da177e4 LT	259	unsigned int depth_mask;
1da177e4 LT	260	} drm_r128_clear_t;
	261
	262	typedef struct drm_r128_vertex {
	263	int prim;
b5e89ed5 DA	264	int idx; /* Index of vertex buffer */
	265	int count; /* Number of vertices in buffer */
	266	int discard; /* Client finished with buffer? */
1da177e4 LT	267	} drm_r128_vertex_t;
	268
	269	typedef struct drm_r128_indices {
	270	int prim;
	271	int idx;
	272	int start;
	273	int end;
b5e89ed5	274	int discard; /* Client finished with buffer? */
1da177e4 LT	275	} drm_r128_indices_t;
	276
	277	typedef struct drm_r128_blit {
	278	int idx;
	279	int pitch;
	280	int offset;
	281	int format;
	282	unsigned short x, y;
	283	unsigned short width, height;
	284	} drm_r128_blit_t;
	285
	286	typedef struct drm_r128_depth {
	287	enum {
b5e89ed5 DA	288	R128_WRITE_SPAN = 0x01,
	289	R128_WRITE_PIXELS = 0x02,
	290	R128_READ_SPAN = 0x03,
	291	R128_READ_PIXELS = 0x04
1da177e4 LT	292	} func;
	293	int n;
	294	int __user *x;
	295	int __user *y;
	296	unsigned int __user *buffer;
	297	unsigned char __user *mask;
	298	} drm_r128_depth_t;
	299
	300	typedef struct drm_r128_stipple {
	301	unsigned int __user *mask;
	302	} drm_r128_stipple_t;
	303
	304	typedef struct drm_r128_indirect {
	305	int idx;
	306	int start;
	307	int end;
	308	int discard;
	309	} drm_r128_indirect_t;
	310
	311	typedef struct drm_r128_fullscreen {
	312	enum {
b5e89ed5	313	R128_INIT_FULLSCREEN = 0x01,
1da177e4 LT	314	R128_CLEANUP_FULLSCREEN = 0x02
	315	} func;
	316	} drm_r128_fullscreen_t;
	317
	318	/* 2.3: An ioctl to get parameters that aren't available to the 3d
b5e89ed5	319	* client any other way.
1da177e4 LT	320	*/
	321	#define R128_PARAM_IRQ_NR 1
	322
	323	typedef struct drm_r128_getparam {
	324	int param;
	325	void __user *value;
	326	} drm_r128_getparam_t;
	327
	328	#endif