[deliverable/linux.git] / include / uapi / drm / vc4_drm.h

/*
 * Copyright © 2014-2015 Broadcom
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#ifndef _UAPI_VC4_DRM_H_
#define _UAPI_VC4_DRM_H_

#include "drm.h"

#if defined(__cplusplus)
extern "C" {
#endif

#define DRM_VC4_SUBMIT_CL                         0x00
#define DRM_VC4_WAIT_SEQNO                        0x01
#define DRM_VC4_WAIT_BO                           0x02
#define DRM_VC4_CREATE_BO                         0x03
#define DRM_VC4_MMAP_BO                           0x04
#define DRM_VC4_CREATE_SHADER_BO                  0x05
#define DRM_VC4_GET_HANG_STATE                    0x06

#define DRM_IOCTL_VC4_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
#define DRM_IOCTL_VC4_WAIT_SEQNO          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
#define DRM_IOCTL_VC4_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
#define DRM_IOCTL_VC4_CREATE_BO           DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
#define DRM_IOCTL_VC4_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
#define DRM_IOCTL_VC4_CREATE_SHADER_BO    DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
#define DRM_IOCTL_VC4_GET_HANG_STATE      DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)

struct drm_vc4_submit_rcl_surface {
	__u32 hindex; /* Handle index, or ~0 if not present. */
	__u32 offset; /* Offset to start of buffer. */
	/*
	 * Bits for either render config (color_write) or load/store packet.
	 * Bits should all be 0 for MSAA load/stores.
	 */
	__u16 bits;

#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES		(1 << 0)
	__u16 flags;
};

/**
 * struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D
 * engine.
 *
 * Drivers typically use GPU BOs to store batchbuffers / command lists and
 * their associated state.  However, because the VC4 lacks an MMU, we have to
 * do validation of memory accesses by the GPU commands.  If we were to store
 * our commands in BOs, we'd need to do uncached readback from them to do the
 * validation process, which is too expensive.  Instead, userspace accumulates
 * commands and associated state in plain memory, then the kernel copies the
 * data to its own address space, and then validates and stores it in a GPU
 * BO.
 */
struct drm_vc4_submit_cl {
	/* Pointer to the binner command list.
	 *
	 * This is the first set of commands executed, which runs the
	 * coordinate shader to determine where primitives land on the screen,
	 * then writes out the state updates and draw calls necessary per tile
	 * to the tile allocation BO.
	 */
	__u64 bin_cl;

	/* Pointer to the shader records.
	 *
	 * Shader records are the structures read by the hardware that contain
	 * pointers to uniforms, shaders, and vertex attributes.  The
	 * reference to the shader record has enough information to determine
	 * how many pointers are necessary (fixed number for shaders/uniforms,
	 * and an attribute count), so those BO indices into bo_handles are
	 * just stored as __u32s before each shader record passed in.
	 */
	__u64 shader_rec;

	/* Pointer to uniform data and texture handles for the textures
	 * referenced by the shader.
	 *
	 * For each shader state record, there is a set of uniform data in the
	 * order referenced by the record (FS, VS, then CS).  Each set of
	 * uniform data has a __u32 index into bo_handles per texture
	 * sample operation, in the order the QPU_W_TMUn_S writes appear in
	 * the program.  Following the texture BO handle indices is the actual
	 * uniform data.
	 *
	 * The individual uniform state blocks don't have sizes passed in,
	 * because the kernel has to determine the sizes anyway during shader
	 * code validation.
	 */
	__u64 uniforms;
	__u64 bo_handles;

	/* Size in bytes of the binner command list. */
	__u32 bin_cl_size;
	/* Size in bytes of the set of shader records. */
	__u32 shader_rec_size;
	/* Number of shader records.
	 *
	 * This could just be computed from the contents of shader_records and
	 * the address bits of references to them from the bin CL, but it
	 * keeps the kernel from having to resize some allocations it makes.
	 */
	__u32 shader_rec_count;
	/* Size in bytes of the uniform state. */
	__u32 uniforms_size;

	/* Number of BO handles passed in (size is that times 4). */
	__u32 bo_handle_count;

	/* RCL setup: */
	__u16 width;
	__u16 height;
	__u8 min_x_tile;
	__u8 min_y_tile;
	__u8 max_x_tile;
	__u8 max_y_tile;
	struct drm_vc4_submit_rcl_surface color_read;
	struct drm_vc4_submit_rcl_surface color_write;
	struct drm_vc4_submit_rcl_surface zs_read;
	struct drm_vc4_submit_rcl_surface zs_write;
	struct drm_vc4_submit_rcl_surface msaa_color_write;
	struct drm_vc4_submit_rcl_surface msaa_zs_write;
	__u32 clear_color[2];
	__u32 clear_z;
	__u8 clear_s;

	__u32 pad:24;

#define VC4_SUBMIT_CL_USE_CLEAR_COLOR			(1 << 0)
	__u32 flags;

	/* Returned value of the seqno of this render job (for the
	 * wait ioctl).
	 */
	__u64 seqno;
};

/**
 * struct drm_vc4_wait_seqno - ioctl argument for waiting for
 * DRM_VC4_SUBMIT_CL completion using its returned seqno.
 *
 * timeout_ns is the timeout in nanoseconds, where "0" means "don't
 * block, just return the status."
 */
struct drm_vc4_wait_seqno {
	__u64 seqno;
	__u64 timeout_ns;
};

/**
 * struct drm_vc4_wait_bo - ioctl argument for waiting for
 * completion of the last DRM_VC4_SUBMIT_CL on a BO.
 *
 * This is useful for cases where multiple processes might be
 * rendering to a BO and you want to wait for all rendering to be
 * completed.
 */
struct drm_vc4_wait_bo {
	__u32 handle;
	__u32 pad;
	__u64 timeout_ns;
};

/**
 * struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs.
 *
 * There are currently no values for the flags argument, but it may be
 * used in a future extension.
 */
struct drm_vc4_create_bo {
	__u32 size;
	__u32 flags;
	/** Returned GEM handle for the BO. */
	__u32 handle;
	__u32 pad;
};

/**
 * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
 *
 * This doesn't actually perform an mmap.  Instead, it returns the
 * offset you need to use in an mmap on the DRM device node.  This
 * means that tools like valgrind end up knowing about the mapped
 * memory.
 *
 * There are currently no values for the flags argument, but it may be
 * used in a future extension.
 */
struct drm_vc4_mmap_bo {
	/** Handle for the object being mapped. */
	__u32 handle;
	__u32 flags;
	/** offset into the drm node to use for subsequent mmap call. */
	__u64 offset;
};

/**
 * struct drm_vc4_create_shader_bo - ioctl argument for creating VC4
 * shader BOs.
 *
 * Since allowing a shader to be overwritten while it's also being
 * executed from would allow privlege escalation, shaders must be
 * created using this ioctl, and they can't be mmapped later.
 */
struct drm_vc4_create_shader_bo {
	/* Size of the data argument. */
	__u32 size;
	/* Flags, currently must be 0. */
	__u32 flags;

	/* Pointer to the data. */
	__u64 data;

	/** Returned GEM handle for the BO. */
	__u32 handle;
	/* Pad, must be 0. */
	__u32 pad;
};

struct drm_vc4_get_hang_state_bo {
	__u32 handle;
	__u32 paddr;
	__u32 size;
	__u32 pad;
};

/**
 * struct drm_vc4_hang_state - ioctl argument for collecting state
 * from a GPU hang for analysis.
*/
struct drm_vc4_get_hang_state {
	/** Pointer to array of struct drm_vc4_get_hang_state_bo. */
	__u64 bo;
	/**
	 * On input, the size of the bo array.  Output is the number
	 * of bos to be returned.
	 */
	__u32 bo_count;

	__u32 start_bin, start_render;

	__u32 ct0ca, ct0ea;
	__u32 ct1ca, ct1ea;
	__u32 ct0cs, ct1cs;
	__u32 ct0ra0, ct1ra0;

	__u32 bpca, bpcs;
	__u32 bpoa, bpos;

	__u32 vpmbase;

	__u32 dbge;
	__u32 fdbgo;
	__u32 fdbgb;
	__u32 fdbgr;
	__u32 fdbgs;
	__u32 errstat;

	/* Pad that we may save more registers into in the future. */
	__u32 pad[16];
};

#if defined(__cplusplus)
}
#endif

#endif /* _UAPI_VC4_DRM_H_ */
Commit	Line	Data
d5bc60f6 EA	1	/*
	2	* Copyright © 2014-2015 Broadcom
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*/
	23
	24	#ifndef _UAPI_VC4_DRM_H_
	25	#define _UAPI_VC4_DRM_H_
	26
	27	#include "drm.h"
	28
6a982350 EV	29	#if defined(__cplusplus)
	30	extern "C" {
	31	#endif
	32
d5b1a78a EA	33	#define DRM_VC4_SUBMIT_CL 0x00
	34	#define DRM_VC4_WAIT_SEQNO 0x01
	35	#define DRM_VC4_WAIT_BO 0x02
d5bc60f6 EA	36	#define DRM_VC4_CREATE_BO 0x03
d5bc60f6 EA	37	#define DRM_VC4_MMAP_BO 0x04
463873d5	38	#define DRM_VC4_CREATE_SHADER_BO 0x05
21461365	39	#define DRM_VC4_GET_HANG_STATE 0x06
d5bc60f6	40
d5b1a78a EA	41	#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
	42	#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
	43	#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
d5bc60f6 EA	44	#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
d5bc60f6 EA	45	#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
463873d5	46	#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
21461365	47	#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
d5bc60f6	48
d5b1a78a EA	49	struct drm_vc4_submit_rcl_surface {
	50	__u32 hindex; /* Handle index, or ~0 if not present. */
	51	__u32 offset; /* Offset to start of buffer. */
	52	/*
	53	* Bits for either render config (color_write) or load/store packet.
	54	* Bits should all be 0 for MSAA load/stores.
	55	*/
	56	__u16 bits;
	57
	58	#define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
	59	__u16 flags;
	60	};
	61
	62	/**
	63	* struct drm_vc4_submit_cl - ioctl argument for submitting commands to the 3D
	64	* engine.
	65	*
	66	* Drivers typically use GPU BOs to store batchbuffers / command lists and
	67	* their associated state. However, because the VC4 lacks an MMU, we have to
	68	* do validation of memory accesses by the GPU commands. If we were to store
	69	* our commands in BOs, we'd need to do uncached readback from them to do the
	70	* validation process, which is too expensive. Instead, userspace accumulates
	71	* commands and associated state in plain memory, then the kernel copies the
	72	* data to its own address space, and then validates and stores it in a GPU
	73	* BO.
	74	*/
	75	struct drm_vc4_submit_cl {
	76	/* Pointer to the binner command list.
	77	*
	78	* This is the first set of commands executed, which runs the
	79	* coordinate shader to determine where primitives land on the screen,
	80	* then writes out the state updates and draw calls necessary per tile
	81	* to the tile allocation BO.
	82	*/
	83	__u64 bin_cl;
	84
	85	/* Pointer to the shader records.
	86	*
	87	* Shader records are the structures read by the hardware that contain
	88	* pointers to uniforms, shaders, and vertex attributes. The
	89	* reference to the shader record has enough information to determine
	90	* how many pointers are necessary (fixed number for shaders/uniforms,
	91	* and an attribute count), so those BO indices into bo_handles are
	92	* just stored as __u32s before each shader record passed in.
	93	*/
	94	__u64 shader_rec;
	95
	96	/* Pointer to uniform data and texture handles for the textures
	97	* referenced by the shader.
	98	*
	99	* For each shader state record, there is a set of uniform data in the
	100	* order referenced by the record (FS, VS, then CS). Each set of
	101	* uniform data has a __u32 index into bo_handles per texture
	102	* sample operation, in the order the QPU_W_TMUn_S writes appear in
	103	* the program. Following the texture BO handle indices is the actual
	104	* uniform data.
	105	*
	106	* The individual uniform state blocks don't have sizes passed in,
	107	* because the kernel has to determine the sizes anyway during shader
	108	* code validation.
	109	*/
	110	__u64 uniforms;
	111	__u64 bo_handles;
	112
113	/* Size in bytes of the binner command list. */
114	__u32 bin_cl_size;
115	/* Size in bytes of the set of shader records. */
116	__u32 shader_rec_size;
117	/* Number of shader records.
118	*
119	* This could just be computed from the contents of shader_records and
120	* the address bits of references to them from the bin CL, but it
121	* keeps the kernel from having to resize some allocations it makes.
122	*/
123	__u32 shader_rec_count;
124	/* Size in bytes of the uniform state. */
125	__u32 uniforms_size;
126
127	/* Number of BO handles passed in (size is that times 4). */
128	__u32 bo_handle_count;
129
130	/* RCL setup: */
131	__u16 width;
132	__u16 height;
133	__u8 min_x_tile;
134	__u8 min_y_tile;
135	__u8 max_x_tile;
136	__u8 max_y_tile;
137	struct drm_vc4_submit_rcl_surface color_read;
138	struct drm_vc4_submit_rcl_surface color_write;
139	struct drm_vc4_submit_rcl_surface zs_read;
140	struct drm_vc4_submit_rcl_surface zs_write;
141	struct drm_vc4_submit_rcl_surface msaa_color_write;
142	struct drm_vc4_submit_rcl_surface msaa_zs_write;
143	__u32 clear_color[2];
144	__u32 clear_z;
145	__u8 clear_s;
146
147	__u32 pad:24;
148
149	#define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
150	__u32 flags;
151
152	/* Returned value of the seqno of this render job (for the
153	* wait ioctl).
154	*/
155	__u64 seqno;
156	};
157
158	/**
159	* struct drm_vc4_wait_seqno - ioctl argument for waiting for
160	* DRM_VC4_SUBMIT_CL completion using its returned seqno.
161	*
162	* timeout_ns is the timeout in nanoseconds, where "0" means "don't
163	* block, just return the status."
164	*/
165	struct drm_vc4_wait_seqno {
166	__u64 seqno;
167	__u64 timeout_ns;
168	};
169
170	/**
171	* struct drm_vc4_wait_bo - ioctl argument for waiting for
172	* completion of the last DRM_VC4_SUBMIT_CL on a BO.
173	*
174	* This is useful for cases where multiple processes might be
175	* rendering to a BO and you want to wait for all rendering to be
176	* completed.
177	*/
178	struct drm_vc4_wait_bo {
179	__u32 handle;
180	__u32 pad;
181	__u64 timeout_ns;
182	};
183
d5bc60f6 EA	184	/**
	185	* struct drm_vc4_create_bo - ioctl argument for creating VC4 BOs.
	186	*
	187	* There are currently no values for the flags argument, but it may be
	188	* used in a future extension.
	189	*/
	190	struct drm_vc4_create_bo {
	191	__u32 size;
	192	__u32 flags;
	193	/** Returned GEM handle for the BO. */
	194	__u32 handle;
	195	__u32 pad;
	196	};
	197
	198	/**
	199	* struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
	200	*
	201	* This doesn't actually perform an mmap. Instead, it returns the
	202	* offset you need to use in an mmap on the DRM device node. This
	203	* means that tools like valgrind end up knowing about the mapped
	204	* memory.
	205	*
	206	* There are currently no values for the flags argument, but it may be
	207	* used in a future extension.
	208	*/
	209	struct drm_vc4_mmap_bo {
	210	/** Handle for the object being mapped. */
	211	__u32 handle;
	212	__u32 flags;
	213	/** offset into the drm node to use for subsequent mmap call. */
	214	__u64 offset;
	215	};
	216
463873d5 EA	217	/**
	218	* struct drm_vc4_create_shader_bo - ioctl argument for creating VC4
	219	* shader BOs.
	220	*
	221	* Since allowing a shader to be overwritten while it's also being
	222	* executed from would allow privlege escalation, shaders must be
	223	* created using this ioctl, and they can't be mmapped later.
	224	*/
	225	struct drm_vc4_create_shader_bo {
	226	/* Size of the data argument. */
	227	__u32 size;
	228	/* Flags, currently must be 0. */
	229	__u32 flags;
	230
	231	/* Pointer to the data. */
	232	__u64 data;
	233
	234	/** Returned GEM handle for the BO. */
	235	__u32 handle;
	236	/* Pad, must be 0. */
	237	__u32 pad;
	238	};
	239
21461365 EA	240	struct drm_vc4_get_hang_state_bo {
	241	__u32 handle;
	242	__u32 paddr;
	243	__u32 size;
	244	__u32 pad;
	245	};
	246
	247	/**
	248	* struct drm_vc4_hang_state - ioctl argument for collecting state
	249	* from a GPU hang for analysis.
	250	*/
	251	struct drm_vc4_get_hang_state {
	252	/** Pointer to array of struct drm_vc4_get_hang_state_bo. */
	253	__u64 bo;
	254	/**
	255	* On input, the size of the bo array. Output is the number
	256	* of bos to be returned.
	257	*/
	258	__u32 bo_count;
	259
	260	__u32 start_bin, start_render;
	261
	262	__u32 ct0ca, ct0ea;
	263	__u32 ct1ca, ct1ea;
	264	__u32 ct0cs, ct1cs;
	265	__u32 ct0ra0, ct1ra0;
	266
	267	__u32 bpca, bpcs;
	268	__u32 bpoa, bpos;
	269
	270	__u32 vpmbase;
	271
	272	__u32 dbge;
	273	__u32 fdbgo;
	274	__u32 fdbgb;
	275	__u32 fdbgr;
	276	__u32 fdbgs;
	277	__u32 errstat;
	278
	279	/* Pad that we may save more registers into in the future. */
	280	__u32 pad[16];
	281	};
	282
6a982350 EV	283	#if defined(__cplusplus)
	284	}
	285	#endif
	286
d5bc60f6	287	#endif /* _UAPI_VC4_DRM_H_ */