[deliverable/linux.git] / include / uapi / drm / virtgpu_drm.h

/*
 * Copyright 2013 Red Hat
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */
#ifndef VIRTGPU_DRM_H
#define VIRTGPU_DRM_H

#include "drm.h"

/* Please note that modifications to all structs defined here are
 * subject to backwards-compatibility constraints.
 *
 * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
 * compatibility Keep fields aligned to their size
 */

#define DRM_VIRTGPU_MAP         0x01
#define DRM_VIRTGPU_EXECBUFFER  0x02
#define DRM_VIRTGPU_GETPARAM    0x03
#define DRM_VIRTGPU_RESOURCE_CREATE 0x04
#define DRM_VIRTGPU_RESOURCE_INFO     0x05
#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
#define DRM_VIRTGPU_WAIT     0x08
#define DRM_VIRTGPU_GET_CAPS  0x09

struct drm_virtgpu_map {
	__u64 offset; /* use for mmap system call */
	__u32 handle;
	__u32 pad;
};

struct drm_virtgpu_execbuffer {
	__u32		flags;		/* for future use */
	__u32 size;
	__u64 command; /* void* */
	__u64 bo_handles;
	__u32 num_bo_handles;
	__u32 pad;
};

#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */

struct drm_virtgpu_getparam {
	__u64 param;
	__u64 value;
};

/* NO_BO flags? NO resource flag? */
/* resource flag for y_0_top */
struct drm_virtgpu_resource_create {
	__u32 target;
	__u32 format;
	__u32 bind;
	__u32 width;
	__u32 height;
	__u32 depth;
	__u32 array_size;
	__u32 last_level;
	__u32 nr_samples;
	__u32 flags;
	__u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
	__u32 res_handle;  /* returned by kernel */
	__u32 size;        /* validate transfer in the host */
	__u32 stride;      /* validate transfer in the host */
};

struct drm_virtgpu_resource_info {
	__u32 bo_handle;
	__u32 res_handle;
	__u32 size;
	__u32 stride;
};

struct drm_virtgpu_3d_box {
	__u32 x;
	__u32 y;
	__u32 z;
	__u32 w;
	__u32 h;
	__u32 d;
};

struct drm_virtgpu_3d_transfer_to_host {
	__u32 bo_handle;
	struct drm_virtgpu_3d_box box;
	__u32 level;
	__u32 offset;
};

struct drm_virtgpu_3d_transfer_from_host {
	__u32 bo_handle;
	struct drm_virtgpu_3d_box box;
	__u32 level;
	__u32 offset;
};

#define VIRTGPU_WAIT_NOWAIT 1 /* like it */
struct drm_virtgpu_3d_wait {
	__u32 handle; /* 0 is an invalid handle */
	__u32 flags;
};

struct drm_virtgpu_get_caps {
	__u32 cap_set_id;
	__u32 cap_set_ver;
	__u64 addr;
	__u32 size;
	__u32 pad;
};

#define DRM_IOCTL_VIRTGPU_MAP \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)

#define DRM_IOCTL_VIRTGPU_EXECBUFFER \
	DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
		struct drm_virtgpu_execbuffer)

#define DRM_IOCTL_VIRTGPU_GETPARAM \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\
		struct drm_virtgpu_getparam)

#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE			\
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE,	\
		struct drm_virtgpu_resource_create)

#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \
		 struct drm_virtgpu_resource_info)

#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST,	\
		struct drm_virtgpu_3d_transfer_from_host)

#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST,	\
		struct drm_virtgpu_3d_transfer_to_host)

#define DRM_IOCTL_VIRTGPU_WAIT				\
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT,	\
		struct drm_virtgpu_3d_wait)

#define DRM_IOCTL_VIRTGPU_GET_CAPS \
	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
	struct drm_virtgpu_get_caps)

#endif
Commit	Line	Data
62fb7a5e GH	1	/*
	2	* Copyright 2013 Red Hat
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*/
	24	#ifndef VIRTGPU_DRM_H
	25	#define VIRTGPU_DRM_H
	26
6e82e9c8	27	#include "drm.h"
62fb7a5e GH	28
	29	/* Please note that modifications to all structs defined here are
	30	* subject to backwards-compatibility constraints.
	31	*
29e08b05	32	* Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
62fb7a5e GH	33	* compatibility Keep fields aligned to their size
	34	*/
	35
	36	#define DRM_VIRTGPU_MAP 0x01
	37	#define DRM_VIRTGPU_EXECBUFFER 0x02
	38	#define DRM_VIRTGPU_GETPARAM 0x03
	39	#define DRM_VIRTGPU_RESOURCE_CREATE 0x04
	40	#define DRM_VIRTGPU_RESOURCE_INFO 0x05
	41	#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
	42	#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
	43	#define DRM_VIRTGPU_WAIT 0x08
	44	#define DRM_VIRTGPU_GET_CAPS 0x09
	45
	46	struct drm_virtgpu_map {
29e08b05 GL	47	__u64 offset; /* use for mmap system call */
	48	__u32 handle;
	49	__u32 pad;
62fb7a5e GH	50	};
	51
	52	struct drm_virtgpu_execbuffer {
29e08b05 GL	53	__u32 flags; /* for future use */
	54	__u32 size;
	55	__u64 command; /* void* */
	56	__u64 bo_handles;
	57	__u32 num_bo_handles;
	58	__u32 pad;
62fb7a5e GH	59	};
	60
	61	#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
	62
	63	struct drm_virtgpu_getparam {
29e08b05 GL	64	__u64 param;
29e08b05 GL	65	__u64 value;
62fb7a5e GH	66	};
	67
	68	/* NO_BO flags? NO resource flag? */
	69	/* resource flag for y_0_top */
	70	struct drm_virtgpu_resource_create {
29e08b05 GL	71	__u32 target;
	72	__u32 format;
	73	__u32 bind;
	74	__u32 width;
	75	__u32 height;
	76	__u32 depth;
	77	__u32 array_size;
	78	__u32 last_level;
	79	__u32 nr_samples;
	80	__u32 flags;
	81	__u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
	82	__u32 res_handle; /* returned by kernel */
	83	__u32 size; /* validate transfer in the host */
	84	__u32 stride; /* validate transfer in the host */
62fb7a5e GH	85	};
	86
	87	struct drm_virtgpu_resource_info {
29e08b05 GL	88	__u32 bo_handle;
	89	__u32 res_handle;
	90	__u32 size;
	91	__u32 stride;
62fb7a5e GH	92	};
	93
	94	struct drm_virtgpu_3d_box {
29e08b05 GL	95	__u32 x;
	96	__u32 y;
	97	__u32 z;
	98	__u32 w;
	99	__u32 h;
	100	__u32 d;
62fb7a5e GH	101	};
	102
	103	struct drm_virtgpu_3d_transfer_to_host {
29e08b05	104	__u32 bo_handle;
62fb7a5e	105	struct drm_virtgpu_3d_box box;
29e08b05 GL	106	__u32 level;
29e08b05 GL	107	__u32 offset;
62fb7a5e GH	108	};
	109
	110	struct drm_virtgpu_3d_transfer_from_host {
29e08b05	111	__u32 bo_handle;
62fb7a5e	112	struct drm_virtgpu_3d_box box;
29e08b05 GL	113	__u32 level;
29e08b05 GL	114	__u32 offset;
62fb7a5e GH	115	};
	116
	117	#define VIRTGPU_WAIT_NOWAIT 1 /* like it */
	118	struct drm_virtgpu_3d_wait {
29e08b05 GL	119	__u32 handle; /* 0 is an invalid handle */
29e08b05 GL	120	__u32 flags;
62fb7a5e GH	121	};
	122
	123	struct drm_virtgpu_get_caps {
29e08b05 GL	124	__u32 cap_set_id;
	125	__u32 cap_set_ver;
	126	__u64 addr;
	127	__u32 size;
	128	__u32 pad;
62fb7a5e GH	129	};
	130
	131	#define DRM_IOCTL_VIRTGPU_MAP \
	132	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
	133
	134	#define DRM_IOCTL_VIRTGPU_EXECBUFFER \
	135	DRM_IOW(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
	136	struct drm_virtgpu_execbuffer)
	137
	138	#define DRM_IOCTL_VIRTGPU_GETPARAM \
	139	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\
	140	struct drm_virtgpu_getparam)
	141
	142	#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \
	143	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \
	144	struct drm_virtgpu_resource_create)
	145
	146	#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \
	147	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \
	148	struct drm_virtgpu_resource_info)
	149
	150	#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \
	151	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \
	152	struct drm_virtgpu_3d_transfer_from_host)
	153
	154	#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \
	155	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \
	156	struct drm_virtgpu_3d_transfer_to_host)
	157
	158	#define DRM_IOCTL_VIRTGPU_WAIT \
	159	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \
	160	struct drm_virtgpu_3d_wait)
	161
	162	#define DRM_IOCTL_VIRTGPU_GET_CAPS \
	163	DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
	164	struct drm_virtgpu_get_caps)
	165
	166	#endif