[deliverable/linux.git] / include / uapi / linux / kfd_ioctl.h

/*
 * Copyright 2014 Advanced Micro Devices, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 */

#ifndef KFD_IOCTL_H_INCLUDED
#define KFD_IOCTL_H_INCLUDED

#include <linux/types.h>
#include <linux/ioctl.h>

#define KFD_IOCTL_MAJOR_VERSION 1
#define KFD_IOCTL_MINOR_VERSION 1

struct kfd_ioctl_get_version_args {
	uint32_t major_version;	/* from KFD */
	uint32_t minor_version;	/* from KFD */
};

/* For kfd_ioctl_create_queue_args.queue_type. */
#define KFD_IOC_QUEUE_TYPE_COMPUTE	0
#define KFD_IOC_QUEUE_TYPE_SDMA		1
#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL	2

#define KFD_MAX_QUEUE_PERCENTAGE	100
#define KFD_MAX_QUEUE_PRIORITY		15

struct kfd_ioctl_create_queue_args {
	uint64_t ring_base_address;	/* to KFD */
	uint64_t write_pointer_address;	/* from KFD */
	uint64_t read_pointer_address;	/* from KFD */
	uint64_t doorbell_offset;	/* from KFD */

	uint32_t ring_size;		/* to KFD */
	uint32_t gpu_id;		/* to KFD */
	uint32_t queue_type;		/* to KFD */
	uint32_t queue_percentage;	/* to KFD */
	uint32_t queue_priority;	/* to KFD */
	uint32_t queue_id;		/* from KFD */

	uint64_t eop_buffer_address;	/* to KFD */
	uint64_t eop_buffer_size;	/* to KFD */
	uint64_t ctx_save_restore_address; /* to KFD */
	uint64_t ctx_save_restore_size;	/* to KFD */
};

struct kfd_ioctl_destroy_queue_args {
	uint32_t queue_id;		/* to KFD */
	uint32_t pad;
};

struct kfd_ioctl_update_queue_args {
	uint64_t ring_base_address;	/* to KFD */

	uint32_t queue_id;		/* to KFD */
	uint32_t ring_size;		/* to KFD */
	uint32_t queue_percentage;	/* to KFD */
	uint32_t queue_priority;	/* to KFD */
};

/* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
#define KFD_IOC_CACHE_POLICY_COHERENT 0
#define KFD_IOC_CACHE_POLICY_NONCOHERENT 1

struct kfd_ioctl_set_memory_policy_args {
	uint64_t alternate_aperture_base;	/* to KFD */
	uint64_t alternate_aperture_size;	/* to KFD */

	uint32_t gpu_id;			/* to KFD */
	uint32_t default_policy;		/* to KFD */
	uint32_t alternate_policy;		/* to KFD */
	uint32_t pad;
};

/*
 * All counters are monotonic. They are used for profiling of compute jobs.
 * The profiling is done by userspace.
 *
 * In case of GPU reset, the counter should not be affected.
 */

struct kfd_ioctl_get_clock_counters_args {
	uint64_t gpu_clock_counter;	/* from KFD */
	uint64_t cpu_clock_counter;	/* from KFD */
	uint64_t system_clock_counter;	/* from KFD */
	uint64_t system_clock_freq;	/* from KFD */

	uint32_t gpu_id;		/* to KFD */
	uint32_t pad;
};

#define NUM_OF_SUPPORTED_GPUS 7

struct kfd_process_device_apertures {
	uint64_t lds_base;		/* from KFD */
	uint64_t lds_limit;		/* from KFD */
	uint64_t scratch_base;		/* from KFD */
	uint64_t scratch_limit;		/* from KFD */
	uint64_t gpuvm_base;		/* from KFD */
	uint64_t gpuvm_limit;		/* from KFD */
	uint32_t gpu_id;		/* from KFD */
	uint32_t pad;
};

struct kfd_ioctl_get_process_apertures_args {
	struct kfd_process_device_apertures
			process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */

	/* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */
	uint32_t num_of_nodes;
	uint32_t pad;
};

#define MAX_ALLOWED_NUM_POINTS    100
#define MAX_ALLOWED_AW_BUFF_SIZE 4096
#define MAX_ALLOWED_WAC_BUFF_SIZE  128

struct kfd_ioctl_dbg_register_args {
	uint32_t gpu_id;		/* to KFD */
	uint32_t pad;
};

struct kfd_ioctl_dbg_unregister_args {
	uint32_t gpu_id;		/* to KFD */
	uint32_t pad;
};

struct kfd_ioctl_dbg_address_watch_args {
	uint64_t content_ptr;		/* a pointer to the actual content */
	uint32_t gpu_id;		/* to KFD */
	uint32_t buf_size_in_bytes;	/*including gpu_id and buf_size */
};

struct kfd_ioctl_dbg_wave_control_args {
	uint64_t content_ptr;		/* a pointer to the actual content */
	uint32_t gpu_id;		/* to KFD */
	uint32_t buf_size_in_bytes;	/*including gpu_id and buf_size */
};

/* Matching HSA_EVENTTYPE */
#define KFD_IOC_EVENT_SIGNAL			0
#define KFD_IOC_EVENT_NODECHANGE		1
#define KFD_IOC_EVENT_DEVICESTATECHANGE		2
#define KFD_IOC_EVENT_HW_EXCEPTION		3
#define KFD_IOC_EVENT_SYSTEM_EVENT		4
#define KFD_IOC_EVENT_DEBUG_EVENT		5
#define KFD_IOC_EVENT_PROFILE_EVENT		6
#define KFD_IOC_EVENT_QUEUE_EVENT		7
#define KFD_IOC_EVENT_MEMORY			8

#define KFD_IOC_WAIT_RESULT_COMPLETE		0
#define KFD_IOC_WAIT_RESULT_TIMEOUT		1
#define KFD_IOC_WAIT_RESULT_FAIL		2

#define KFD_SIGNAL_EVENT_LIMIT			256

struct kfd_ioctl_create_event_args {
	uint64_t event_page_offset;	/* from KFD */
	uint32_t event_trigger_data;	/* from KFD - signal events only */
	uint32_t event_type;		/* to KFD */
	uint32_t auto_reset;		/* to KFD */
	uint32_t node_id;		/* to KFD - only valid for certain
							event types */
	uint32_t event_id;		/* from KFD */
	uint32_t event_slot_index;	/* from KFD */
};

struct kfd_ioctl_destroy_event_args {
	uint32_t event_id;		/* to KFD */
	uint32_t pad;
};

struct kfd_ioctl_set_event_args {
	uint32_t event_id;		/* to KFD */
	uint32_t pad;
};

struct kfd_ioctl_reset_event_args {
	uint32_t event_id;		/* to KFD */
	uint32_t pad;
};

struct kfd_memory_exception_failure {
	uint32_t NotPresent;	/* Page not present or supervisor privilege */
	uint32_t ReadOnly;	/* Write access to a read-only page */
	uint32_t NoExecute;	/* Execute access to a page marked NX */
	uint32_t pad;
};

/* memory exception data*/
struct kfd_hsa_memory_exception_data {
	struct kfd_memory_exception_failure failure;
	uint64_t va;
	uint32_t gpu_id;
	uint32_t pad;
};

/* Event data*/
struct kfd_event_data {
	union {
		struct kfd_hsa_memory_exception_data memory_exception_data;
	};				/* From KFD */
	uint64_t kfd_event_data_ext;	/* pointer to an extension structure
					   for future exception types */
	uint32_t event_id;		/* to KFD */
	uint32_t pad;
};

struct kfd_ioctl_wait_events_args {
	uint64_t events_ptr;		/* pointed to struct
					   kfd_event_data array, to KFD */
	uint32_t num_events;		/* to KFD */
	uint32_t wait_for_all;		/* to KFD */
	uint32_t timeout;		/* to KFD */
	uint32_t wait_result;		/* from KFD */
};

#define AMDKFD_IOCTL_BASE 'K'
#define AMDKFD_IO(nr)			_IO(AMDKFD_IOCTL_BASE, nr)
#define AMDKFD_IOR(nr, type)		_IOR(AMDKFD_IOCTL_BASE, nr, type)
#define AMDKFD_IOW(nr, type)		_IOW(AMDKFD_IOCTL_BASE, nr, type)
#define AMDKFD_IOWR(nr, type)		_IOWR(AMDKFD_IOCTL_BASE, nr, type)

#define AMDKFD_IOC_GET_VERSION			\
		AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args)

#define AMDKFD_IOC_CREATE_QUEUE			\
		AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args)

#define AMDKFD_IOC_DESTROY_QUEUE		\
		AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args)

#define AMDKFD_IOC_SET_MEMORY_POLICY		\
		AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args)

#define AMDKFD_IOC_GET_CLOCK_COUNTERS		\
		AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args)

#define AMDKFD_IOC_GET_PROCESS_APERTURES	\
		AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args)

#define AMDKFD_IOC_UPDATE_QUEUE			\
		AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args)

#define AMDKFD_IOC_CREATE_EVENT			\
		AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args)

#define AMDKFD_IOC_DESTROY_EVENT		\
		AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args)

#define AMDKFD_IOC_SET_EVENT			\
		AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args)

#define AMDKFD_IOC_RESET_EVENT			\
		AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args)

#define AMDKFD_IOC_WAIT_EVENTS			\
		AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)

#define AMDKFD_IOC_DBG_REGISTER			\
		AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)

#define AMDKFD_IOC_DBG_UNREGISTER		\
		AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)

#define AMDKFD_IOC_DBG_ADDRESS_WATCH		\
		AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)

#define AMDKFD_IOC_DBG_WAVE_CONTROL		\
		AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)

#define AMDKFD_COMMAND_START		0x01
#define AMDKFD_COMMAND_END		0x11

#endif
Commit	Line	Data
b7facbae OG	1	/*
	2	* Copyright 2014 Advanced Micro Devices, Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*/
	22
	23	#ifndef KFD_IOCTL_H_INCLUDED
	24	#define KFD_IOCTL_H_INCLUDED
	25
	26	#include <linux/types.h>
	27	#include <linux/ioctl.h>
	28
	29	#define KFD_IOCTL_MAJOR_VERSION 1
29a5d3eb	30	#define KFD_IOCTL_MINOR_VERSION 1
b7facbae OG	31
	32	struct kfd_ioctl_get_version_args {
	33	uint32_t major_version; /* from KFD */
	34	uint32_t minor_version; /* from KFD */
	35	};
	36
	37	/* For kfd_ioctl_create_queue_args.queue_type. */
	38	#define KFD_IOC_QUEUE_TYPE_COMPUTE 0
	39	#define KFD_IOC_QUEUE_TYPE_SDMA 1
	40	#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 2
	41
	42	#define KFD_MAX_QUEUE_PERCENTAGE 100
	43	#define KFD_MAX_QUEUE_PRIORITY 15
	44
	45	struct kfd_ioctl_create_queue_args {
	46	uint64_t ring_base_address; /* to KFD */
	47	uint64_t write_pointer_address; /* from KFD */
	48	uint64_t read_pointer_address; /* from KFD */
	49	uint64_t doorbell_offset; /* from KFD */
	50
	51	uint32_t ring_size; /* to KFD */
	52	uint32_t gpu_id; /* to KFD */
	53	uint32_t queue_type; /* to KFD */
	54	uint32_t queue_percentage; /* to KFD */
	55	uint32_t queue_priority; /* to KFD */
	56	uint32_t queue_id; /* from KFD */
	57
	58	uint64_t eop_buffer_address; /* to KFD */
	59	uint64_t eop_buffer_size; /* to KFD */
	60	uint64_t ctx_save_restore_address; /* to KFD */
	61	uint64_t ctx_save_restore_size; /* to KFD */
	62	};
	63
	64	struct kfd_ioctl_destroy_queue_args {
	65	uint32_t queue_id; /* to KFD */
	66	uint32_t pad;
	67	};
	68
	69	struct kfd_ioctl_update_queue_args {
	70	uint64_t ring_base_address; /* to KFD */
	71
	72	uint32_t queue_id; /* to KFD */
	73	uint32_t ring_size; /* to KFD */
	74	uint32_t queue_percentage; /* to KFD */
	75	uint32_t queue_priority; /* to KFD */
	76	};
	77
	78	/* For kfd_ioctl_set_memory_policy_args.default_policy and alternate_policy */
	79	#define KFD_IOC_CACHE_POLICY_COHERENT 0
	80	#define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
	81
	82	struct kfd_ioctl_set_memory_policy_args {
	83	uint64_t alternate_aperture_base; /* to KFD */
	84	uint64_t alternate_aperture_size; /* to KFD */
	85
	86	uint32_t gpu_id; /* to KFD */
	87	uint32_t default_policy; /* to KFD */
	88	uint32_t alternate_policy; /* to KFD */
	89	uint32_t pad;
	90	};
	91
	92	/*
	93	* All counters are monotonic. They are used for profiling of compute jobs.
	94	* The profiling is done by userspace.
95	*
96	* In case of GPU reset, the counter should not be affected.
97	*/
98
99	struct kfd_ioctl_get_clock_counters_args {
100	uint64_t gpu_clock_counter; /* from KFD */
101	uint64_t cpu_clock_counter; /* from KFD */
102	uint64_t system_clock_counter; /* from KFD */
103	uint64_t system_clock_freq; /* from KFD */
104
105	uint32_t gpu_id; /* to KFD */
106	uint32_t pad;
107	};
108
109	#define NUM_OF_SUPPORTED_GPUS 7
110
111	struct kfd_process_device_apertures {
112	uint64_t lds_base; /* from KFD */
113	uint64_t lds_limit; /* from KFD */
114	uint64_t scratch_base; /* from KFD */
115	uint64_t scratch_limit; /* from KFD */
116	uint64_t gpuvm_base; /* from KFD */
117	uint64_t gpuvm_limit; /* from KFD */
118	uint32_t gpu_id; /* from KFD */
119	uint32_t pad;
120	};
121
122	struct kfd_ioctl_get_process_apertures_args {
123	struct kfd_process_device_apertures
124	process_apertures[NUM_OF_SUPPORTED_GPUS];/* from KFD */
125
126	/* from KFD, should be in the range [1 - NUM_OF_SUPPORTED_GPUS] */
127	uint32_t num_of_nodes;
128	uint32_t pad;
129	};
130
aef11009 YS	131	#define MAX_ALLOWED_NUM_POINTS 100
	132	#define MAX_ALLOWED_AW_BUFF_SIZE 4096
	133	#define MAX_ALLOWED_WAC_BUFF_SIZE 128
	134
	135	struct kfd_ioctl_dbg_register_args {
	136	uint32_t gpu_id; /* to KFD */
	137	uint32_t pad;
	138	};
	139
	140	struct kfd_ioctl_dbg_unregister_args {
	141	uint32_t gpu_id; /* to KFD */
	142	uint32_t pad;
	143	};
	144
	145	struct kfd_ioctl_dbg_address_watch_args {
	146	uint64_t content_ptr; /* a pointer to the actual content */
	147	uint32_t gpu_id; /* to KFD */
	148	uint32_t buf_size_in_bytes; /including gpu_id and buf_size /
	149	};
	150
	151	struct kfd_ioctl_dbg_wave_control_args {
	152	uint64_t content_ptr; /* a pointer to the actual content */
	153	uint32_t gpu_id; /* to KFD */
	154	uint32_t buf_size_in_bytes; /including gpu_id and buf_size /
	155	};
	156
29a5d3eb AL	157	/* Matching HSA_EVENTTYPE */
	158	#define KFD_IOC_EVENT_SIGNAL 0
	159	#define KFD_IOC_EVENT_NODECHANGE 1
	160	#define KFD_IOC_EVENT_DEVICESTATECHANGE 2
	161	#define KFD_IOC_EVENT_HW_EXCEPTION 3
	162	#define KFD_IOC_EVENT_SYSTEM_EVENT 4
	163	#define KFD_IOC_EVENT_DEBUG_EVENT 5
	164	#define KFD_IOC_EVENT_PROFILE_EVENT 6
	165	#define KFD_IOC_EVENT_QUEUE_EVENT 7
	166	#define KFD_IOC_EVENT_MEMORY 8
	167
	168	#define KFD_IOC_WAIT_RESULT_COMPLETE 0
	169	#define KFD_IOC_WAIT_RESULT_TIMEOUT 1
	170	#define KFD_IOC_WAIT_RESULT_FAIL 2
	171
	172	#define KFD_SIGNAL_EVENT_LIMIT 256
	173
	174	struct kfd_ioctl_create_event_args {
	175	uint64_t event_page_offset; /* from KFD */
	176	uint32_t event_trigger_data; /* from KFD - signal events only */
	177	uint32_t event_type; /* to KFD */
	178	uint32_t auto_reset; /* to KFD */
	179	uint32_t node_id; /* to KFD - only valid for certain
	180	event types */
	181	uint32_t event_id; /* from KFD */
	182	uint32_t event_slot_index; /* from KFD */
	183	};
	184
	185	struct kfd_ioctl_destroy_event_args {
	186	uint32_t event_id; /* to KFD */
	187	uint32_t pad;
	188	};
	189
	190	struct kfd_ioctl_set_event_args {
	191	uint32_t event_id; /* to KFD */
	192	uint32_t pad;
	193	};
	194
	195	struct kfd_ioctl_reset_event_args {
	196	uint32_t event_id; /* to KFD */
	197	uint32_t pad;
	198	};
	199
	200	struct kfd_memory_exception_failure {
	201	uint32_t NotPresent; /* Page not present or supervisor privilege */
	202	uint32_t ReadOnly; /* Write access to a read-only page */
	203	uint32_t NoExecute; /* Execute access to a page marked NX */
	204	uint32_t pad;
	205	};
	206
	207	/* memory exception data*/
	208	struct kfd_hsa_memory_exception_data {
	209	struct kfd_memory_exception_failure failure;
	210	uint64_t va;
	211	uint32_t gpu_id;
	212	uint32_t pad;
	213	};
	214
	215	/* Event data*/
	216	struct kfd_event_data {
	217	union {
	218	struct kfd_hsa_memory_exception_data memory_exception_data;
	219	}; /* From KFD */
	220	uint64_t kfd_event_data_ext; /* pointer to an extension structure
221	for future exception types */
222	uint32_t event_id; /* to KFD */
223	uint32_t pad;
224	};
225
226	struct kfd_ioctl_wait_events_args {
aef11009 YS	227	uint64_t events_ptr; /* pointed to struct
aef11009 YS	228	kfd_event_data array, to KFD */
29a5d3eb AL	229	uint32_t num_events; /* to KFD */
	230	uint32_t wait_for_all; /* to KFD */
	231	uint32_t timeout; /* to KFD */
	232	uint32_t wait_result; /* from KFD */
	233	};
	234
b81c55db OG	235	#define AMDKFD_IOCTL_BASE 'K'
	236	#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
	237	#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
	238	#define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type)
	239	#define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type)
b7facbae	240
b81c55db OG	241	#define AMDKFD_IOC_GET_VERSION \
b81c55db OG	242	AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args)
b7facbae	243
b81c55db OG	244	#define AMDKFD_IOC_CREATE_QUEUE \
b81c55db OG	245	AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args)
b7facbae	246
b81c55db OG	247	#define AMDKFD_IOC_DESTROY_QUEUE \
b81c55db OG	248	AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args)
b7facbae	249
b81c55db OG	250	#define AMDKFD_IOC_SET_MEMORY_POLICY \
b81c55db OG	251	AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args)
b7facbae	252
b81c55db OG	253	#define AMDKFD_IOC_GET_CLOCK_COUNTERS \
b81c55db OG	254	AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args)
b7facbae	255
b81c55db OG	256	#define AMDKFD_IOC_GET_PROCESS_APERTURES \
b81c55db OG	257	AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args)
b7facbae	258
b81c55db OG	259	#define AMDKFD_IOC_UPDATE_QUEUE \
	260	AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args)
	261
29a5d3eb AL	262	#define AMDKFD_IOC_CREATE_EVENT \
	263	AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args)
	264
	265	#define AMDKFD_IOC_DESTROY_EVENT \
	266	AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args)
	267
	268	#define AMDKFD_IOC_SET_EVENT \
	269	AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args)
	270
	271	#define AMDKFD_IOC_RESET_EVENT \
	272	AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args)
	273
	274	#define AMDKFD_IOC_WAIT_EVENTS \
	275	AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)
	276
aef11009 YS	277	#define AMDKFD_IOC_DBG_REGISTER \
	278	AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)
	279
	280	#define AMDKFD_IOC_DBG_UNREGISTER \
	281	AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)
	282
	283	#define AMDKFD_IOC_DBG_ADDRESS_WATCH \
	284	AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)
	285
	286	#define AMDKFD_IOC_DBG_WAVE_CONTROL \
	287	AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)
	288
b81c55db	289	#define AMDKFD_COMMAND_START 0x01
aef11009	290	#define AMDKFD_COMMAND_END 0x11
b7facbae OG	291
b7facbae OG	292	#endif