[deliverable/linux.git] / include / uapi / linux / nvme.h

/*
 * Definitions for the NVM Express interface
 * Copyright (c) 2011-2014, Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 */

#ifndef _UAPI_LINUX_NVME_H
#define _UAPI_LINUX_NVME_H

#include <linux/types.h>

struct nvme_id_power_state {
	__le16			max_power;	/* centiwatts */
	__u8			rsvd2;
	__u8			flags;
	__le32			entry_lat;	/* microseconds */
	__le32			exit_lat;	/* microseconds */
	__u8			read_tput;
	__u8			read_lat;
	__u8			write_tput;
	__u8			write_lat;
	__u8			rsvd16[16];
};

enum {
	NVME_PS_FLAGS_MAX_POWER_SCALE	= 1 << 0,
	NVME_PS_FLAGS_NON_OP_STATE	= 1 << 1,
};

struct nvme_id_ctrl {
	__le16			vid;
	__le16			ssvid;
	char			sn[20];
	char			mn[40];
	char			fr[8];
	__u8			rab;
	__u8			ieee[3];
	__u8			mic;
	__u8			mdts;
	__u8			rsvd78[178];
	__le16			oacs;
	__u8			acl;
	__u8			aerl;
	__u8			frmw;
	__u8			lpa;
	__u8			elpe;
	__u8			npss;
	__u8			rsvd264[248];
	__u8			sqes;
	__u8			cqes;
	__u8			rsvd514[2];
	__le32			nn;
	__le16			oncs;
	__le16			fuses;
	__u8			fna;
	__u8			vwc;
	__le16			awun;
	__le16			awupf;
	__u8			rsvd530[1518];
	struct nvme_id_power_state	psd[32];
	__u8			vs[1024];
};

enum {
	NVME_CTRL_ONCS_COMPARE			= 1 << 0,
	NVME_CTRL_ONCS_WRITE_UNCORRECTABLE	= 1 << 1,
	NVME_CTRL_ONCS_DSM			= 1 << 2,
	NVME_CTRL_VWC_PRESENT			= 1 << 0,
};

struct nvme_lbaf {
	__le16			ms;
	__u8			ds;
	__u8			rp;
};

struct nvme_id_ns {
	__le64			nsze;
	__le64			ncap;
	__le64			nuse;
	__u8			nsfeat;
	__u8			nlbaf;
	__u8			flbas;
	__u8			mc;
	__u8			dpc;
	__u8			dps;
	__u8			rsvd30[98];
	struct nvme_lbaf	lbaf[16];
	__u8			rsvd192[192];
	__u8			vs[3712];
};

enum {
	NVME_NS_FEAT_THIN	= 1 << 0,
	NVME_LBAF_RP_BEST	= 0,
	NVME_LBAF_RP_BETTER	= 1,
	NVME_LBAF_RP_GOOD	= 2,
	NVME_LBAF_RP_DEGRADED	= 3,
};

struct nvme_smart_log {
	__u8			critical_warning;
	__u8			temperature[2];
	__u8			avail_spare;
	__u8			spare_thresh;
	__u8			percent_used;
	__u8			rsvd6[26];
	__u8			data_units_read[16];
	__u8			data_units_written[16];
	__u8			host_reads[16];
	__u8			host_writes[16];
	__u8			ctrl_busy_time[16];
	__u8			power_cycles[16];
	__u8			power_on_hours[16];
	__u8			unsafe_shutdowns[16];
	__u8			media_errors[16];
	__u8			num_err_log_entries[16];
	__u8			rsvd192[320];
};

enum {
	NVME_SMART_CRIT_SPARE		= 1 << 0,
	NVME_SMART_CRIT_TEMPERATURE	= 1 << 1,
	NVME_SMART_CRIT_RELIABILITY	= 1 << 2,
	NVME_SMART_CRIT_MEDIA		= 1 << 3,
	NVME_SMART_CRIT_VOLATILE_MEMORY	= 1 << 4,
};

struct nvme_lba_range_type {
	__u8			type;
	__u8			attributes;
	__u8			rsvd2[14];
	__u64			slba;
	__u64			nlb;
	__u8			guid[16];
	__u8			rsvd48[16];
};

enum {
	NVME_LBART_TYPE_FS	= 0x01,
	NVME_LBART_TYPE_RAID	= 0x02,
	NVME_LBART_TYPE_CACHE	= 0x03,
	NVME_LBART_TYPE_SWAP	= 0x04,

	NVME_LBART_ATTRIB_TEMP	= 1 << 0,
	NVME_LBART_ATTRIB_HIDE	= 1 << 1,
};

/* I/O commands */

enum nvme_opcode {
	nvme_cmd_flush		= 0x00,
	nvme_cmd_write		= 0x01,
	nvme_cmd_read		= 0x02,
	nvme_cmd_write_uncor	= 0x04,
	nvme_cmd_compare	= 0x05,
	nvme_cmd_dsm		= 0x09,
};

struct nvme_common_command {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__le32			cdw2[2];
	__le64			metadata;
	__le64			prp1;
	__le64			prp2;
	__le32			cdw10[6];
};

struct nvme_rw_command {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2;
	__le64			metadata;
	__le64			prp1;
	__le64			prp2;
	__le64			slba;
	__le16			length;
	__le16			control;
	__le32			dsmgmt;
	__le32			reftag;
	__le16			apptag;
	__le16			appmask;
};

enum {
	NVME_RW_LR			= 1 << 15,
	NVME_RW_FUA			= 1 << 14,
	NVME_RW_DSM_FREQ_UNSPEC		= 0,
	NVME_RW_DSM_FREQ_TYPICAL	= 1,
	NVME_RW_DSM_FREQ_RARE		= 2,
	NVME_RW_DSM_FREQ_READS		= 3,
	NVME_RW_DSM_FREQ_WRITES		= 4,
	NVME_RW_DSM_FREQ_RW		= 5,
	NVME_RW_DSM_FREQ_ONCE		= 6,
	NVME_RW_DSM_FREQ_PREFETCH	= 7,
	NVME_RW_DSM_FREQ_TEMP		= 8,
	NVME_RW_DSM_LATENCY_NONE	= 0 << 4,
	NVME_RW_DSM_LATENCY_IDLE	= 1 << 4,
	NVME_RW_DSM_LATENCY_NORM	= 2 << 4,
	NVME_RW_DSM_LATENCY_LOW		= 3 << 4,
	NVME_RW_DSM_SEQ_REQ		= 1 << 6,
	NVME_RW_DSM_COMPRESSED		= 1 << 7,
};

struct nvme_dsm_cmd {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[2];
	__le64			prp1;
	__le64			prp2;
	__le32			nr;
	__le32			attributes;
	__u32			rsvd12[4];
};

enum {
	NVME_DSMGMT_IDR		= 1 << 0,
	NVME_DSMGMT_IDW		= 1 << 1,
	NVME_DSMGMT_AD		= 1 << 2,
};

struct nvme_dsm_range {
	__le32			cattr;
	__le32			nlb;
	__le64			slba;
};

/* Admin commands */

enum nvme_admin_opcode {
	nvme_admin_delete_sq		= 0x00,
	nvme_admin_create_sq		= 0x01,
	nvme_admin_get_log_page		= 0x02,
	nvme_admin_delete_cq		= 0x04,
	nvme_admin_create_cq		= 0x05,
	nvme_admin_identify		= 0x06,
	nvme_admin_abort_cmd		= 0x08,
	nvme_admin_set_features		= 0x09,
	nvme_admin_get_features		= 0x0a,
	nvme_admin_async_event		= 0x0c,
	nvme_admin_activate_fw		= 0x10,
	nvme_admin_download_fw		= 0x11,
	nvme_admin_format_nvm		= 0x80,
	nvme_admin_security_send	= 0x81,
	nvme_admin_security_recv	= 0x82,
};

enum {
	NVME_QUEUE_PHYS_CONTIG	= (1 << 0),
	NVME_CQ_IRQ_ENABLED	= (1 << 1),
	NVME_SQ_PRIO_URGENT	= (0 << 1),
	NVME_SQ_PRIO_HIGH	= (1 << 1),
	NVME_SQ_PRIO_MEDIUM	= (2 << 1),
	NVME_SQ_PRIO_LOW	= (3 << 1),
	NVME_FEAT_ARBITRATION	= 0x01,
	NVME_FEAT_POWER_MGMT	= 0x02,
	NVME_FEAT_LBA_RANGE	= 0x03,
	NVME_FEAT_TEMP_THRESH	= 0x04,
	NVME_FEAT_ERR_RECOVERY	= 0x05,
	NVME_FEAT_VOLATILE_WC	= 0x06,
	NVME_FEAT_NUM_QUEUES	= 0x07,
	NVME_FEAT_IRQ_COALESCE	= 0x08,
	NVME_FEAT_IRQ_CONFIG	= 0x09,
	NVME_FEAT_WRITE_ATOMIC	= 0x0a,
	NVME_FEAT_ASYNC_EVENT	= 0x0b,
	NVME_FEAT_SW_PROGRESS	= 0x0c,
	NVME_FWACT_REPL		= (0 << 3),
	NVME_FWACT_REPL_ACTV	= (1 << 3),
	NVME_FWACT_ACTV		= (2 << 3),
};

struct nvme_identify {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[2];
	__le64			prp1;
	__le64			prp2;
	__le32			cns;
	__u32			rsvd11[5];
};

struct nvme_features {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[2];
	__le64			prp1;
	__le64			prp2;
	__le32			fid;
	__le32			dword11;
	__u32			rsvd12[4];
};

struct nvme_create_cq {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[5];
	__le64			prp1;
	__u64			rsvd8;
	__le16			cqid;
	__le16			qsize;
	__le16			cq_flags;
	__le16			irq_vector;
	__u32			rsvd12[4];
};

struct nvme_create_sq {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[5];
	__le64			prp1;
	__u64			rsvd8;
	__le16			sqid;
	__le16			qsize;
	__le16			sq_flags;
	__le16			cqid;
	__u32			rsvd12[4];
};

struct nvme_delete_queue {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[9];
	__le16			qid;
	__u16			rsvd10;
	__u32			rsvd11[5];
};

struct nvme_abort_cmd {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[9];
	__le16			sqid;
	__u16			cid;
	__u32			rsvd11[5];
};

struct nvme_download_firmware {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__u32			rsvd1[5];
	__le64			prp1;
	__le64			prp2;
	__le32			numd;
	__le32			offset;
	__u32			rsvd12[4];
};

struct nvme_format_cmd {
	__u8			opcode;
	__u8			flags;
	__u16			command_id;
	__le32			nsid;
	__u64			rsvd2[4];
	__le32			cdw10;
	__u32			rsvd11[5];
};

struct nvme_command {
	union {
		struct nvme_common_command common;
		struct nvme_rw_command rw;
		struct nvme_identify identify;
		struct nvme_features features;
		struct nvme_create_cq create_cq;
		struct nvme_create_sq create_sq;
		struct nvme_delete_queue delete_queue;
		struct nvme_download_firmware dlfw;
		struct nvme_format_cmd format;
		struct nvme_dsm_cmd dsm;
		struct nvme_abort_cmd abort;
	};
};

enum {
	NVME_SC_SUCCESS			= 0x0,
	NVME_SC_INVALID_OPCODE		= 0x1,
	NVME_SC_INVALID_FIELD		= 0x2,
	NVME_SC_CMDID_CONFLICT		= 0x3,
	NVME_SC_DATA_XFER_ERROR		= 0x4,
	NVME_SC_POWER_LOSS		= 0x5,
	NVME_SC_INTERNAL		= 0x6,
	NVME_SC_ABORT_REQ		= 0x7,
	NVME_SC_ABORT_QUEUE		= 0x8,
	NVME_SC_FUSED_FAIL		= 0x9,
	NVME_SC_FUSED_MISSING		= 0xa,
	NVME_SC_INVALID_NS		= 0xb,
	NVME_SC_CMD_SEQ_ERROR		= 0xc,
	NVME_SC_LBA_RANGE		= 0x80,
	NVME_SC_CAP_EXCEEDED		= 0x81,
	NVME_SC_NS_NOT_READY		= 0x82,
	NVME_SC_CQ_INVALID		= 0x100,
	NVME_SC_QID_INVALID		= 0x101,
	NVME_SC_QUEUE_SIZE		= 0x102,
	NVME_SC_ABORT_LIMIT		= 0x103,
	NVME_SC_ABORT_MISSING		= 0x104,
	NVME_SC_ASYNC_LIMIT		= 0x105,
	NVME_SC_FIRMWARE_SLOT		= 0x106,
	NVME_SC_FIRMWARE_IMAGE		= 0x107,
	NVME_SC_INVALID_VECTOR		= 0x108,
	NVME_SC_INVALID_LOG_PAGE	= 0x109,
	NVME_SC_INVALID_FORMAT		= 0x10a,
	NVME_SC_BAD_ATTRIBUTES		= 0x180,
	NVME_SC_WRITE_FAULT		= 0x280,
	NVME_SC_READ_ERROR		= 0x281,
	NVME_SC_GUARD_CHECK		= 0x282,
	NVME_SC_APPTAG_CHECK		= 0x283,
	NVME_SC_REFTAG_CHECK		= 0x284,
	NVME_SC_COMPARE_FAILED		= 0x285,
	NVME_SC_ACCESS_DENIED		= 0x286,
	NVME_SC_DNR			= 0x4000,
};

struct nvme_completion {
	__le32	result;		/* Used by admin commands to return data */
	__u32	rsvd;
	__le16	sq_head;	/* how much of this queue may be reclaimed */
	__le16	sq_id;		/* submission queue that generated this entry */
	__u16	command_id;	/* of the command which completed */
	__le16	status;		/* did the command fail, and if so, why? */
};

struct nvme_user_io {
	__u8	opcode;
	__u8	flags;
	__u16	control;
	__u16	nblocks;
	__u16	rsvd;
	__u64	metadata;
	__u64	addr;
	__u64	slba;
	__u32	dsmgmt;
	__u32	reftag;
	__u16	apptag;
	__u16	appmask;
};

struct nvme_admin_cmd {
	__u8	opcode;
	__u8	flags;
	__u16	rsvd1;
	__u32	nsid;
	__u32	cdw2;
	__u32	cdw3;
	__u64	metadata;
	__u64	addr;
	__u32	metadata_len;
	__u32	data_len;
	__u32	cdw10;
	__u32	cdw11;
	__u32	cdw12;
	__u32	cdw13;
	__u32	cdw14;
	__u32	cdw15;
	__u32	timeout_ms;
	__u32	result;
};

#define NVME_IOCTL_ID		_IO('N', 0x40)
#define NVME_IOCTL_ADMIN_CMD	_IOWR('N', 0x41, struct nvme_admin_cmd)
#define NVME_IOCTL_SUBMIT_IO	_IOW('N', 0x42, struct nvme_user_io)

#endif /* _UAPI_LINUX_NVME_H */
Commit	Line	Data
42c77683 MW	1	/*
42c77683 MW	2	* Definitions for the NVM Express interface
8757ad65	3	* Copyright (c) 2011-2014, Intel Corporation.
42c77683 MW	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
42c77683 MW	13	*/
	14
	15	#ifndef _UAPI_LINUX_NVME_H
	16	#define _UAPI_LINUX_NVME_H
	17
	18	#include <linux/types.h>
	19
	20	struct nvme_id_power_state {
	21	__le16 max_power; /* centiwatts */
685585c2 KB	22	__u8 rsvd2;
685585c2 KB	23	__u8 flags;
42c77683 MW	24	__le32 entry_lat; /* microseconds */
	25	__le32 exit_lat; /* microseconds */
	26	__u8 read_tput;
	27	__u8 read_lat;
	28	__u8 write_tput;
	29	__u8 write_lat;
	30	__u8 rsvd16[16];
	31	};
	32
685585c2 KB	33	enum {
	34	NVME_PS_FLAGS_MAX_POWER_SCALE = 1 << 0,
	35	NVME_PS_FLAGS_NON_OP_STATE = 1 << 1,
	36	};
	37
42c77683 MW	38	struct nvme_id_ctrl {
	39	__le16 vid;
	40	__le16 ssvid;
	41	char sn[20];
	42	char mn[40];
	43	char fr[8];
	44	__u8 rab;
	45	__u8 ieee[3];
	46	__u8 mic;
	47	__u8 mdts;
	48	__u8 rsvd78[178];
	49	__le16 oacs;
	50	__u8 acl;
	51	__u8 aerl;
	52	__u8 frmw;
	53	__u8 lpa;
	54	__u8 elpe;
	55	__u8 npss;
	56	__u8 rsvd264[248];
	57	__u8 sqes;
	58	__u8 cqes;
	59	__u8 rsvd514[2];
	60	__le32 nn;
	61	__le16 oncs;
	62	__le16 fuses;
	63	__u8 fna;
	64	__u8 vwc;
	65	__le16 awun;
	66	__le16 awupf;
	67	__u8 rsvd530[1518];
	68	struct nvme_id_power_state psd[32];
	69	__u8 vs[1024];
	70	};
	71
	72	enum {
	73	NVME_CTRL_ONCS_COMPARE = 1 << 0,
	74	NVME_CTRL_ONCS_WRITE_UNCORRECTABLE = 1 << 1,
	75	NVME_CTRL_ONCS_DSM = 1 << 2,
a7d2ce28	76	NVME_CTRL_VWC_PRESENT = 1 << 0,
42c77683 MW	77	};
	78
	79	struct nvme_lbaf {
	80	__le16 ms;
	81	__u8 ds;
	82	__u8 rp;
	83	};
	84
	85	struct nvme_id_ns {
	86	__le64 nsze;
	87	__le64 ncap;
	88	__le64 nuse;
	89	__u8 nsfeat;
	90	__u8 nlbaf;
	91	__u8 flbas;
	92	__u8 mc;
	93	__u8 dpc;
	94	__u8 dps;
	95	__u8 rsvd30[98];
	96	struct nvme_lbaf lbaf[16];
	97	__u8 rsvd192[192];
	98	__u8 vs[3712];
	99	};
	100
	101	enum {
	102	NVME_NS_FEAT_THIN = 1 << 0,
	103	NVME_LBAF_RP_BEST = 0,
	104	NVME_LBAF_RP_BETTER = 1,
	105	NVME_LBAF_RP_GOOD = 2,
	106	NVME_LBAF_RP_DEGRADED = 3,
	107	};
	108
	109	struct nvme_smart_log {
	110	__u8 critical_warning;
	111	__u8 temperature[2];
	112	__u8 avail_spare;
	113	__u8 spare_thresh;
	114	__u8 percent_used;
	115	__u8 rsvd6[26];
	116	__u8 data_units_read[16];
	117	__u8 data_units_written[16];
	118	__u8 host_reads[16];
	119	__u8 host_writes[16];
	120	__u8 ctrl_busy_time[16];
	121	__u8 power_cycles[16];
	122	__u8 power_on_hours[16];
	123	__u8 unsafe_shutdowns[16];
	124	__u8 media_errors[16];
	125	__u8 num_err_log_entries[16];
	126	__u8 rsvd192[320];
	127	};
	128
	129	enum {
	130	NVME_SMART_CRIT_SPARE = 1 << 0,
	131	NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
	132	NVME_SMART_CRIT_RELIABILITY = 1 << 2,
	133	NVME_SMART_CRIT_MEDIA = 1 << 3,
	134	NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
	135	};
	136
	137	struct nvme_lba_range_type {
	138	__u8 type;
	139	__u8 attributes;
	140	__u8 rsvd2[14];
141	__u64 slba;
142	__u64 nlb;
143	__u8 guid[16];
144	__u8 rsvd48[16];
145	};
146
147	enum {
148	NVME_LBART_TYPE_FS = 0x01,
149	NVME_LBART_TYPE_RAID = 0x02,
150	NVME_LBART_TYPE_CACHE = 0x03,
151	NVME_LBART_TYPE_SWAP = 0x04,
152
153	NVME_LBART_ATTRIB_TEMP = 1 << 0,
154	NVME_LBART_ATTRIB_HIDE = 1 << 1,
155	};
156
157	/* I/O commands */
158
159	enum nvme_opcode {
160	nvme_cmd_flush = 0x00,
161	nvme_cmd_write = 0x01,
162	nvme_cmd_read = 0x02,
163	nvme_cmd_write_uncor = 0x04,
164	nvme_cmd_compare = 0x05,
165	nvme_cmd_dsm = 0x09,
166	};
167
168	struct nvme_common_command {
169	__u8 opcode;
170	__u8 flags;
171	__u16 command_id;
172	__le32 nsid;
173	__le32 cdw2[2];
174	__le64 metadata;
175	__le64 prp1;
176	__le64 prp2;
177	__le32 cdw10[6];
178	};
179
180	struct nvme_rw_command {
181	__u8 opcode;
182	__u8 flags;
183	__u16 command_id;
184	__le32 nsid;
185	__u64 rsvd2;
186	__le64 metadata;
187	__le64 prp1;
188	__le64 prp2;
189	__le64 slba;
190	__le16 length;
191	__le16 control;
192	__le32 dsmgmt;
193	__le32 reftag;
194	__le16 apptag;
195	__le16 appmask;
196	};
197
198	enum {
199	NVME_RW_LR = 1 << 15,
200	NVME_RW_FUA = 1 << 14,
201	NVME_RW_DSM_FREQ_UNSPEC = 0,
202	NVME_RW_DSM_FREQ_TYPICAL = 1,
203	NVME_RW_DSM_FREQ_RARE = 2,
204	NVME_RW_DSM_FREQ_READS = 3,
205	NVME_RW_DSM_FREQ_WRITES = 4,
206	NVME_RW_DSM_FREQ_RW = 5,
207	NVME_RW_DSM_FREQ_ONCE = 6,
208	NVME_RW_DSM_FREQ_PREFETCH = 7,
209	NVME_RW_DSM_FREQ_TEMP = 8,
210	NVME_RW_DSM_LATENCY_NONE = 0 << 4,
211	NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
212	NVME_RW_DSM_LATENCY_NORM = 2 << 4,
213	NVME_RW_DSM_LATENCY_LOW = 3 << 4,
214	NVME_RW_DSM_SEQ_REQ = 1 << 6,
215	NVME_RW_DSM_COMPRESSED = 1 << 7,
216	};
217
218	struct nvme_dsm_cmd {
219	__u8 opcode;
220	__u8 flags;
221	__u16 command_id;
222	__le32 nsid;
223	__u64 rsvd2[2];
224	__le64 prp1;
225	__le64 prp2;
226	__le32 nr;
227	__le32 attributes;
228	__u32 rsvd12[4];
229	};
230
231	enum {
232	NVME_DSMGMT_IDR = 1 << 0,
233	NVME_DSMGMT_IDW = 1 << 1,
234	NVME_DSMGMT_AD = 1 << 2,
235	};
236
237	struct nvme_dsm_range {
238	__le32 cattr;
239	__le32 nlb;
240	__le64 slba;
241	};
242
243	/* Admin commands */
244
245	enum nvme_admin_opcode {
246	nvme_admin_delete_sq = 0x00,
247	nvme_admin_create_sq = 0x01,
248	nvme_admin_get_log_page = 0x02,
249	nvme_admin_delete_cq = 0x04,
250	nvme_admin_create_cq = 0x05,
251	nvme_admin_identify = 0x06,
252	nvme_admin_abort_cmd = 0x08,
253	nvme_admin_set_features = 0x09,
254	nvme_admin_get_features = 0x0a,
255	nvme_admin_async_event = 0x0c,
256	nvme_admin_activate_fw = 0x10,
257	nvme_admin_download_fw = 0x11,
258	nvme_admin_format_nvm = 0x80,
259	nvme_admin_security_send = 0x81,
260	nvme_admin_security_recv = 0x82,
261	};
262
263	enum {
264	NVME_QUEUE_PHYS_CONTIG = (1 << 0),
265	NVME_CQ_IRQ_ENABLED = (1 << 1),
266	NVME_SQ_PRIO_URGENT = (0 << 1),
267	NVME_SQ_PRIO_HIGH = (1 << 1),
268	NVME_SQ_PRIO_MEDIUM = (2 << 1),
269	NVME_SQ_PRIO_LOW = (3 << 1),
270	NVME_FEAT_ARBITRATION = 0x01,
271	NVME_FEAT_POWER_MGMT = 0x02,
272	NVME_FEAT_LBA_RANGE = 0x03,
273	NVME_FEAT_TEMP_THRESH = 0x04,
274	NVME_FEAT_ERR_RECOVERY = 0x05,
275	NVME_FEAT_VOLATILE_WC = 0x06,
276	NVME_FEAT_NUM_QUEUES = 0x07,
277	NVME_FEAT_IRQ_COALESCE = 0x08,
278	NVME_FEAT_IRQ_CONFIG = 0x09,
279	NVME_FEAT_WRITE_ATOMIC = 0x0a,
280	NVME_FEAT_ASYNC_EVENT = 0x0b,
281	NVME_FEAT_SW_PROGRESS = 0x0c,
282	NVME_FWACT_REPL = (0 << 3),
283	NVME_FWACT_REPL_ACTV = (1 << 3),
284	NVME_FWACT_ACTV = (2 << 3),
285	};
286
287	struct nvme_identify {
288	__u8 opcode;
289	__u8 flags;
290	__u16 command_id;
291	__le32 nsid;
292	__u64 rsvd2[2];
293	__le64 prp1;
294	__le64 prp2;
295	__le32 cns;
296	__u32 rsvd11[5];
297	};
298
299	struct nvme_features {
300	__u8 opcode;
301	__u8 flags;
302	__u16 command_id;
303	__le32 nsid;
304	__u64 rsvd2[2];
305	__le64 prp1;
306	__le64 prp2;
307	__le32 fid;
308	__le32 dword11;
309	__u32 rsvd12[4];
310	};
311
312	struct nvme_create_cq {
313	__u8 opcode;
314	__u8 flags;
315	__u16 command_id;
316	__u32 rsvd1[5];
317	__le64 prp1;
318	__u64 rsvd8;
319	__le16 cqid;
320	__le16 qsize;
321	__le16 cq_flags;
322	__le16 irq_vector;
323	__u32 rsvd12[4];
324	};
325
326	struct nvme_create_sq {
327	__u8 opcode;
328	__u8 flags;
329	__u16 command_id;
330	__u32 rsvd1[5];
331	__le64 prp1;
332	__u64 rsvd8;
333	__le16 sqid;
334	__le16 qsize;
335	__le16 sq_flags;
336	__le16 cqid;
337	__u32 rsvd12[4];
338	};
339
340	struct nvme_delete_queue {
341	__u8 opcode;
342	__u8 flags;
343	__u16 command_id;
344	__u32 rsvd1[9];
345	__le16 qid;
346	__u16 rsvd10;
347	__u32 rsvd11[5];
348	};
349
c30341dc KB	350	struct nvme_abort_cmd {
	351	__u8 opcode;
	352	__u8 flags;
	353	__u16 command_id;
	354	__u32 rsvd1[9];
	355	__le16 sqid;
	356	__u16 cid;
	357	__u32 rsvd11[5];
	358	};
	359
42c77683 MW	360	struct nvme_download_firmware {
	361	__u8 opcode;
	362	__u8 flags;
	363	__u16 command_id;
	364	__u32 rsvd1[5];
	365	__le64 prp1;
	366	__le64 prp2;
	367	__le32 numd;
	368	__le32 offset;
	369	__u32 rsvd12[4];
	370	};
	371
	372	struct nvme_format_cmd {
	373	__u8 opcode;
	374	__u8 flags;
	375	__u16 command_id;
	376	__le32 nsid;
	377	__u64 rsvd2[4];
	378	__le32 cdw10;
	379	__u32 rsvd11[5];
	380	};
	381
	382	struct nvme_command {
	383	union {
	384	struct nvme_common_command common;
	385	struct nvme_rw_command rw;
	386	struct nvme_identify identify;
	387	struct nvme_features features;
	388	struct nvme_create_cq create_cq;
	389	struct nvme_create_sq create_sq;
	390	struct nvme_delete_queue delete_queue;
	391	struct nvme_download_firmware dlfw;
	392	struct nvme_format_cmd format;
	393	struct nvme_dsm_cmd dsm;
c30341dc	394	struct nvme_abort_cmd abort;
42c77683 MW	395	};
	396	};
	397
	398	enum {
	399	NVME_SC_SUCCESS = 0x0,
	400	NVME_SC_INVALID_OPCODE = 0x1,
	401	NVME_SC_INVALID_FIELD = 0x2,
	402	NVME_SC_CMDID_CONFLICT = 0x3,
	403	NVME_SC_DATA_XFER_ERROR = 0x4,
	404	NVME_SC_POWER_LOSS = 0x5,
	405	NVME_SC_INTERNAL = 0x6,
	406	NVME_SC_ABORT_REQ = 0x7,
	407	NVME_SC_ABORT_QUEUE = 0x8,
	408	NVME_SC_FUSED_FAIL = 0x9,
	409	NVME_SC_FUSED_MISSING = 0xa,
	410	NVME_SC_INVALID_NS = 0xb,
	411	NVME_SC_CMD_SEQ_ERROR = 0xc,
	412	NVME_SC_LBA_RANGE = 0x80,
	413	NVME_SC_CAP_EXCEEDED = 0x81,
	414	NVME_SC_NS_NOT_READY = 0x82,
	415	NVME_SC_CQ_INVALID = 0x100,
	416	NVME_SC_QID_INVALID = 0x101,
	417	NVME_SC_QUEUE_SIZE = 0x102,
	418	NVME_SC_ABORT_LIMIT = 0x103,
	419	NVME_SC_ABORT_MISSING = 0x104,
	420	NVME_SC_ASYNC_LIMIT = 0x105,
	421	NVME_SC_FIRMWARE_SLOT = 0x106,
	422	NVME_SC_FIRMWARE_IMAGE = 0x107,
	423	NVME_SC_INVALID_VECTOR = 0x108,
	424	NVME_SC_INVALID_LOG_PAGE = 0x109,
	425	NVME_SC_INVALID_FORMAT = 0x10a,
	426	NVME_SC_BAD_ATTRIBUTES = 0x180,
	427	NVME_SC_WRITE_FAULT = 0x280,
	428	NVME_SC_READ_ERROR = 0x281,
	429	NVME_SC_GUARD_CHECK = 0x282,
	430	NVME_SC_APPTAG_CHECK = 0x283,
	431	NVME_SC_REFTAG_CHECK = 0x284,
	432	NVME_SC_COMPARE_FAILED = 0x285,
	433	NVME_SC_ACCESS_DENIED = 0x286,
edd10d33	434	NVME_SC_DNR = 0x4000,
42c77683 MW	435	};
	436
	437	struct nvme_completion {
	438	__le32 result; /* Used by admin commands to return data */
	439	__u32 rsvd;
	440	__le16 sq_head; /* how much of this queue may be reclaimed */
	441	__le16 sq_id; /* submission queue that generated this entry */
	442	__u16 command_id; /* of the command which completed */
	443	__le16 status; /* did the command fail, and if so, why? */
	444	};
	445
	446	struct nvme_user_io {
	447	__u8 opcode;
	448	__u8 flags;
	449	__u16 control;
	450	__u16 nblocks;
	451	__u16 rsvd;
	452	__u64 metadata;
	453	__u64 addr;
	454	__u64 slba;
	455	__u32 dsmgmt;
	456	__u32 reftag;
	457	__u16 apptag;
	458	__u16 appmask;
	459	};
	460
	461	struct nvme_admin_cmd {
	462	__u8 opcode;
	463	__u8 flags;
	464	__u16 rsvd1;
	465	__u32 nsid;
	466	__u32 cdw2;
	467	__u32 cdw3;
	468	__u64 metadata;
	469	__u64 addr;
	470	__u32 metadata_len;
	471	__u32 data_len;
	472	__u32 cdw10;
	473	__u32 cdw11;
	474	__u32 cdw12;
	475	__u32 cdw13;
	476	__u32 cdw14;
	477	__u32 cdw15;
	478	__u32 timeout_ms;
	479	__u32 result;
	480	};
	481
	482	#define NVME_IOCTL_ID _IO('N', 0x40)
	483	#define NVME_IOCTL_ADMIN_CMD _IOWR('N', 0x41, struct nvme_admin_cmd)
	484	#define NVME_IOCTL_SUBMIT_IO _IOW('N', 0x42, struct nvme_user_io)
	485
	486	#endif /* _UAPI_LINUX_NVME_H */