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ef5fa1a4 | 1 | #ifndef __SOUND_HDSPM_H |
763f356c TI |
2 | #define __SOUND_HDSPM_H |
3 | /* | |
4 | * Copyright (C) 2003 Winfried Ritsch (IEM) | |
5 | * based on hdsp.h from Thomas Charbonnel (thomas@undata.org) | |
0dca1793 AK |
6 | * |
7 | * | |
763f356c TI |
8 | * This program is free software; you can redistribute it and/or modify |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
21 | */ | |
22 | ||
76a3aeac | 23 | #include <linux/types.h> |
76a3aeac | 24 | |
763f356c TI |
25 | /* Maximum channels is 64 even on 56Mode you have 64playbacks to matrix */ |
26 | #define HDSPM_MAX_CHANNELS 64 | |
27 | ||
0dca1793 AK |
28 | enum hdspm_io_type { |
29 | MADI, | |
30 | MADIface, | |
31 | AIO, | |
32 | AES32, | |
33 | RayDAT | |
34 | }; | |
763f356c | 35 | |
0dca1793 AK |
36 | enum hdspm_speed { |
37 | ss, | |
38 | ds, | |
39 | qs | |
40 | }; | |
763f356c | 41 | |
0dca1793 | 42 | /* -------------------- IOCTL Peak/RMS Meters -------------------- */ |
763f356c | 43 | |
0dca1793 | 44 | struct hdspm_peak_rms { |
ffc287c8 MR |
45 | __u32 input_peaks[64]; |
46 | __u32 playback_peaks[64]; | |
47 | __u32 output_peaks[64]; | |
763f356c | 48 | |
ffc287c8 MR |
49 | __u64 input_rms[64]; |
50 | __u64 playback_rms[64]; | |
51 | __u64 output_rms[64]; | |
763f356c | 52 | |
ffc287c8 | 53 | __u8 speed; /* enum {ss, ds, qs} */ |
0dca1793 | 54 | int status2; |
763f356c TI |
55 | }; |
56 | ||
ef5fa1a4 | 57 | #define SNDRV_HDSPM_IOCTL_GET_PEAK_RMS \ |
0dca1793 | 58 | _IOR('H', 0x42, struct hdspm_peak_rms) |
763f356c TI |
59 | |
60 | /* ------------ CONFIG block IOCTL ---------------------- */ | |
61 | ||
0dca1793 | 62 | struct hdspm_config { |
763f356c TI |
63 | unsigned char pref_sync_ref; |
64 | unsigned char wordclock_sync_check; | |
65 | unsigned char madi_sync_check; | |
66 | unsigned int system_sample_rate; | |
67 | unsigned int autosync_sample_rate; | |
68 | unsigned char system_clock_mode; | |
69 | unsigned char clock_source; | |
70 | unsigned char autosync_ref; | |
71 | unsigned char line_out; | |
72 | unsigned int passthru; | |
73 | unsigned int analog_out; | |
74 | }; | |
75 | ||
0dca1793 AK |
76 | #define SNDRV_HDSPM_IOCTL_GET_CONFIG \ |
77 | _IOR('H', 0x41, struct hdspm_config) | |
78 | ||
ddcecf6b | 79 | /* |
0dca1793 AK |
80 | * If there's a TCO (TimeCode Option) board installed, |
81 | * there are further options and status data available. | |
82 | * The hdspm_ltc structure contains the current SMPTE | |
83 | * timecode and some status information and can be | |
84 | * obtained via SNDRV_HDSPM_IOCTL_GET_LTC or in the | |
85 | * hdspm_status struct. | |
ddcecf6b | 86 | */ |
0dca1793 AK |
87 | |
88 | enum hdspm_ltc_format { | |
89 | format_invalid, | |
90 | fps_24, | |
91 | fps_25, | |
92 | fps_2997, | |
93 | fps_30 | |
94 | }; | |
95 | ||
96 | enum hdspm_ltc_frame { | |
97 | frame_invalid, | |
98 | drop_frame, | |
99 | full_frame | |
100 | }; | |
101 | ||
102 | enum hdspm_ltc_input_format { | |
103 | ntsc, | |
104 | pal, | |
105 | no_video | |
106 | }; | |
107 | ||
108 | struct hdspm_ltc { | |
109 | unsigned int ltc; | |
110 | ||
111 | enum hdspm_ltc_format format; | |
112 | enum hdspm_ltc_frame frame; | |
113 | enum hdspm_ltc_input_format input_format; | |
114 | }; | |
115 | ||
b43dd416 | 116 | #define SNDRV_HDSPM_IOCTL_GET_LTC _IOR('H', 0x46, struct hdspm_ltc) |
0dca1793 | 117 | |
ddcecf6b | 118 | /* |
0dca1793 AK |
119 | * The status data reflects the device's current state |
120 | * as determined by the card's configuration and | |
121 | * connection status. | |
ddcecf6b | 122 | */ |
0dca1793 AK |
123 | |
124 | enum hdspm_sync { | |
125 | hdspm_sync_no_lock = 0, | |
126 | hdspm_sync_lock = 1, | |
127 | hdspm_sync_sync = 2 | |
128 | }; | |
129 | ||
130 | enum hdspm_madi_input { | |
131 | hdspm_input_optical = 0, | |
132 | hdspm_input_coax = 1 | |
133 | }; | |
134 | ||
135 | enum hdspm_madi_channel_format { | |
136 | hdspm_format_ch_64 = 0, | |
137 | hdspm_format_ch_56 = 1 | |
138 | }; | |
139 | ||
140 | enum hdspm_madi_frame_format { | |
141 | hdspm_frame_48 = 0, | |
142 | hdspm_frame_96 = 1 | |
143 | }; | |
144 | ||
145 | enum hdspm_syncsource { | |
146 | syncsource_wc = 0, | |
147 | syncsource_madi = 1, | |
148 | syncsource_tco = 2, | |
149 | syncsource_sync = 3, | |
150 | syncsource_none = 4 | |
151 | }; | |
152 | ||
153 | struct hdspm_status { | |
ffc287c8 | 154 | __u8 card_type; /* enum hdspm_io_type */ |
0dca1793 | 155 | enum hdspm_syncsource autosync_source; |
763f356c | 156 | |
ffc287c8 MR |
157 | __u64 card_clock; |
158 | __u32 master_period; | |
0dca1793 AK |
159 | |
160 | union { | |
161 | struct { | |
ffc287c8 MR |
162 | __u8 sync_wc; /* enum hdspm_sync */ |
163 | __u8 sync_madi; /* enum hdspm_sync */ | |
164 | __u8 sync_tco; /* enum hdspm_sync */ | |
165 | __u8 sync_in; /* enum hdspm_sync */ | |
166 | __u8 madi_input; /* enum hdspm_madi_input */ | |
167 | __u8 channel_format; /* enum hdspm_madi_channel_format */ | |
168 | __u8 frame_format; /* enum hdspm_madi_frame_format */ | |
0dca1793 AK |
169 | } madi; |
170 | } card_specific; | |
171 | }; | |
763f356c | 172 | |
0dca1793 AK |
173 | #define SNDRV_HDSPM_IOCTL_GET_STATUS \ |
174 | _IOR('H', 0x47, struct hdspm_status) | |
175 | ||
ddcecf6b | 176 | /* |
0dca1793 | 177 | * Get information about the card and its add-ons. |
ddcecf6b | 178 | */ |
0dca1793 AK |
179 | |
180 | #define HDSPM_ADDON_TCO 1 | |
763f356c | 181 | |
98274f07 | 182 | struct hdspm_version { |
ffc287c8 | 183 | __u8 card_type; /* enum hdspm_io_type */ |
0dca1793 AK |
184 | char cardname[20]; |
185 | unsigned int serial; | |
763f356c | 186 | unsigned short firmware_rev; |
0dca1793 | 187 | int addons; |
763f356c TI |
188 | }; |
189 | ||
0dca1793 | 190 | #define SNDRV_HDSPM_IOCTL_GET_VERSION _IOR('H', 0x48, struct hdspm_version) |
763f356c TI |
191 | |
192 | /* ------------- get Matrix Mixer IOCTL --------------- */ | |
193 | ||
ef5fa1a4 TI |
194 | /* MADI mixer: 64inputs+64playback in 64outputs = 8192 => *4Byte = |
195 | * 32768 Bytes | |
196 | */ | |
763f356c | 197 | |
25985edc | 198 | /* organisation is 64 channelfader in a continuous memory block */ |
ef5fa1a4 TI |
199 | /* equivalent to hardware definition, maybe for future feature of mmap of |
200 | * them | |
201 | */ | |
0dca1793 | 202 | /* each of 64 outputs has 64 infader and 64 outfader: |
763f356c TI |
203 | Ins to Outs mixer[out].in[in], Outstreams to Outs mixer[out].pb[pb] */ |
204 | ||
205 | #define HDSPM_MIXER_CHANNELS HDSPM_MAX_CHANNELS | |
206 | ||
98274f07 | 207 | struct hdspm_channelfader { |
763f356c TI |
208 | unsigned int in[HDSPM_MIXER_CHANNELS]; |
209 | unsigned int pb[HDSPM_MIXER_CHANNELS]; | |
210 | }; | |
211 | ||
98274f07 TI |
212 | struct hdspm_mixer { |
213 | struct hdspm_channelfader ch[HDSPM_MIXER_CHANNELS]; | |
763f356c TI |
214 | }; |
215 | ||
98274f07 TI |
216 | struct hdspm_mixer_ioctl { |
217 | struct hdspm_mixer *mixer; | |
763f356c TI |
218 | }; |
219 | ||
220 | /* use indirect access due to the limit of ioctl bit size */ | |
98274f07 TI |
221 | #define SNDRV_HDSPM_IOCTL_GET_MIXER _IOR('H', 0x44, struct hdspm_mixer_ioctl) |
222 | ||
223 | /* typedefs for compatibility to user-space */ | |
224 | typedef struct hdspm_peak_rms hdspm_peak_rms_t; | |
225 | typedef struct hdspm_config_info hdspm_config_info_t; | |
226 | typedef struct hdspm_version hdspm_version_t; | |
227 | typedef struct hdspm_channelfader snd_hdspm_channelfader_t; | |
228 | typedef struct hdspm_mixer hdspm_mixer_t; | |
763f356c | 229 | |
0dca1793 AK |
230 | |
231 | #endif |