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Merge tag 'dm-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/device-mapper...
[deliverable/linux.git] / include / video / omapdss.h
CommitLineData
559d6701 1/*
559d6701
TV		 2 * Copyright (C) 2008 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
a0b38cc4
TV		 18#ifndef __OMAP_OMAPDSS_H
19#define __OMAP_OMAPDSS_H
559d6701
TV		 20
21#include <linux/list.h>
22#include <linux/kobject.h>
23#include <linux/device.h>
348be69d 24#include <linux/interrupt.h>
559d6701 25
6fcd485b
TV		 26#include <video/videomode.h>
27
559d6701
TV		 28#define DISPC_IRQ_FRAMEDONE (1 << 0)
29#define DISPC_IRQ_VSYNC (1 << 1)
30#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
31#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
32#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
33#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
34#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
35#define DISPC_IRQ_GFX_END_WIN (1 << 7)
36#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
37#define DISPC_IRQ_OCP_ERR (1 << 9)
38#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
39#define DISPC_IRQ_VID1_END_WIN (1 << 11)
40#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
41#define DISPC_IRQ_VID2_END_WIN (1 << 13)
42#define DISPC_IRQ_SYNC_LOST (1 << 14)
43#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
44#define DISPC_IRQ_WAKEUP (1 << 16)
2a205f34
SS		 45#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
46#define DISPC_IRQ_VSYNC2 (1 << 18)
b8c095b4
AT		 47#define DISPC_IRQ_VID3_END_WIN (1 << 19)
48#define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
2a205f34
SS		 49#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
50#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
7f6f3c4b
TV		 51#define DISPC_IRQ_FRAMEDONEWB (1 << 23)
52#define DISPC_IRQ_FRAMEDONETV (1 << 24)
53#define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
14d33d38
CM		 54#define DISPC_IRQ_SYNC_LOST3 (1 << 27)
55#define DISPC_IRQ_VSYNC3 (1 << 28)
56#define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
57#define DISPC_IRQ_FRAMEDONE3 (1 << 30)
559d6701
TV		 58
59struct omap_dss_device;
60struct omap_overlay_manager;
a97a9634 61struct dss_lcd_mgr_config;
9c0b8420
RN		 62struct snd_aes_iec958;
63struct snd_cea_861_aud_if;
8c071caa 64struct hdmi_avi_infoframe;
559d6701
TV		 65
66enum omap_display_type {
67 OMAP_DISPLAY_TYPE_NONE = 0,
68 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
69 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
70 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
71 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
72 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
b119601d 73 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
bc24b8b6 74 OMAP_DISPLAY_TYPE_DVI = 1 << 6,
559d6701
TV		 75};
76
77enum omap_plane {
78 OMAP_DSS_GFX = 0,
79 OMAP_DSS_VIDEO1 = 1,
b8c095b4
AT		 80 OMAP_DSS_VIDEO2 = 2,
81 OMAP_DSS_VIDEO3 = 3,
66a0f9e4 82 OMAP_DSS_WB = 4,
559d6701
TV		 83};
84
85enum omap_channel {
86 OMAP_DSS_CHANNEL_LCD = 0,
87 OMAP_DSS_CHANNEL_DIGIT = 1,
8613b000 88 OMAP_DSS_CHANNEL_LCD2 = 2,
ff6331e2 89 OMAP_DSS_CHANNEL_LCD3 = 3,
559d6701
TV		 90};
91
92enum omap_color_mode {
93 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
94 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
95 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
96 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
97 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
98 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
99 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
100 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
101 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
102 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
103 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
104 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
105 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
106 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
f20e4220
AJ		 107 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
108 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
109 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
110 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
111 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
559d6701
TV		 112};
113
559d6701
TV		 114enum omap_dss_load_mode {
115 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
116 OMAP_DSS_LOAD_CLUT_ONLY = 1,
117 OMAP_DSS_LOAD_FRAME_ONLY = 2,
118 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
119};
120
121enum omap_dss_trans_key_type {
122 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
123 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
124};
125
126enum omap_rfbi_te_mode {
127 OMAP_DSS_RFBI_TE_MODE_1 = 1,
128 OMAP_DSS_RFBI_TE_MODE_2 = 2,
129};
130
a8d5e41c
AT		 131enum omap_dss_signal_level {
132 OMAPDSS_SIG_ACTIVE_HIGH = 0,
133 OMAPDSS_SIG_ACTIVE_LOW = 1,
134};
135
136enum omap_dss_signal_edge {
137 OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
138 OMAPDSS_DRIVE_SIG_RISING_EDGE,
139 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
140};
141
559d6701
TV		 142enum omap_dss_venc_type {
143 OMAP_DSS_VENC_TYPE_COMPOSITE,
144 OMAP_DSS_VENC_TYPE_SVIDEO,
145};
146
a3b3cc2b
AT		 147enum omap_dss_dsi_pixel_format {
148 OMAP_DSS_DSI_FMT_RGB888,
149 OMAP_DSS_DSI_FMT_RGB666,
150 OMAP_DSS_DSI_FMT_RGB666_PACKED,
151 OMAP_DSS_DSI_FMT_RGB565,
152};
153
7e951ee9
AT		 154enum omap_dss_dsi_mode {
155 OMAP_DSS_DSI_CMD_MODE = 0,
156 OMAP_DSS_DSI_VIDEO_MODE,
157};
158
559d6701
TV		 159enum omap_display_caps {
160 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
161 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
162};
163
559d6701
TV		 164enum omap_dss_display_state {
165 OMAP_DSS_DISPLAY_DISABLED = 0,
166 OMAP_DSS_DISPLAY_ACTIVE,
559d6701
TV		 167};
168
9c0b8420
RN		 169enum omap_dss_audio_state {
170 OMAP_DSS_AUDIO_DISABLED = 0,
171 OMAP_DSS_AUDIO_ENABLED,
172 OMAP_DSS_AUDIO_CONFIGURED,
173 OMAP_DSS_AUDIO_PLAYING,
174};
175
0b450c31
TV		 176struct omap_dss_audio {
177 struct snd_aes_iec958 *iec;
178 struct snd_cea_861_aud_if *cea;
179};
180
559d6701 181enum omap_dss_rotation_type {
65e006ff
CM		 182 OMAP_DSS_ROT_DMA = 1 << 0,
183 OMAP_DSS_ROT_VRFB = 1 << 1,
184 OMAP_DSS_ROT_TILER = 1 << 2,
559d6701
TV		 185};
186
187/* clockwise rotation angle */
188enum omap_dss_rotation_angle {
189 OMAP_DSS_ROT_0 = 0,
190 OMAP_DSS_ROT_90 = 1,
191 OMAP_DSS_ROT_180 = 2,
192 OMAP_DSS_ROT_270 = 3,
193};
194
195enum omap_overlay_caps {
196 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
f6dc8150
TV		 197 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
198 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
11354dd5 199 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
d79db853
AT		 200 OMAP_DSS_OVL_CAP_POS = 1 << 4,
201 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
559d6701
TV		 202};
203
204enum omap_overlay_manager_caps {
4a9e78ab 205 OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
559d6701
TV		 206};
207
89a35e51
AT		 208enum omap_dss_clk_source {
209 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
210 * OMAP4: DSS_FCLK */
211 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
212 * OMAP4: PLL1_CLK1 */
213 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
214 * OMAP4: PLL1_CLK2 */
5a8b572d
AT		 215 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
216 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
89a35e51
AT		 217};
218
9a901683
M		 219enum omap_hdmi_flags {
220 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
221};
222
484dc404
AT		 223enum omap_dss_output_id {
224 OMAP_DSS_OUTPUT_DPI = 1 << 0,
225 OMAP_DSS_OUTPUT_DBI = 1 << 1,
226 OMAP_DSS_OUTPUT_SDI = 1 << 2,
227 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
228 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
229 OMAP_DSS_OUTPUT_VENC = 1 << 5,
230 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
231};
232
559d6701
TV		 233/* RFBI */
234
235struct rfbi_timings {
236 int cs_on_time;
237 int cs_off_time;
238 int we_on_time;
239 int we_off_time;
240 int re_on_time;
241 int re_off_time;
242 int we_cycle_time;
243 int re_cycle_time;
244 int cs_pulse_width;
245 int access_time;
246
247 int clk_div;
248
249 u32 tim[5]; /* set by rfbi_convert_timings() */
250
251 int converted;
252};
253
559d6701 254/* DSI */
8af6ff01 255
478d7df8
TV		 256enum omap_dss_dsi_trans_mode {
257 /* Sync Pulses: both sync start and end packets sent */
258 OMAP_DSS_DSI_PULSE_MODE,
259 /* Sync Events: only sync start packets sent */
260 OMAP_DSS_DSI_EVENT_MODE,
261 /* Burst: only sync start packets sent, pixels are time compressed */
262 OMAP_DSS_DSI_BURST_MODE,
263};
264
6b849375 265struct omap_dss_dsi_videomode_timings {
f1e0001f
TV		 266 unsigned long hsclk;
267
268 unsigned ndl;
269 unsigned bitspp;
270
271 /* pixels */
272 u16 hact;
273 /* lines */
274 u16 vact;
275
8af6ff01
AT		 276 /* DSI video mode blanking data */
277 /* Unit: byte clock cycles */
f1e0001f 278 u16 hss;
8af6ff01 279 u16 hsa;
f1e0001f 280 u16 hse;
8af6ff01
AT		 281 u16 hfp;
282 u16 hbp;
283 /* Unit: line clocks */
284 u16 vsa;
285 u16 vfp;
286 u16 vbp;
287
288 /* DSI blanking modes */
289 int blanking_mode;
290 int hsa_blanking_mode;
291 int hbp_blanking_mode;
292 int hfp_blanking_mode;
293
478d7df8 294 enum omap_dss_dsi_trans_mode trans_mode;
8af6ff01
AT		 295
296 bool ddr_clk_always_on;
297 int window_sync;
298};
299
777f05cc
TV		 300struct omap_dss_dsi_config {
301 enum omap_dss_dsi_mode mode;
302 enum omap_dss_dsi_pixel_format pixel_format;
303 const struct omap_video_timings *timings;
777f05cc 304
f1e0001f
TV		 305 unsigned long hs_clk_min, hs_clk_max;
306 unsigned long lp_clk_min, lp_clk_max;
307
308 bool ddr_clk_always_on;
309 enum omap_dss_dsi_trans_mode trans_mode;
777f05cc
TV		 310};
311
acd18af9
TV		 312enum omapdss_version {
313 OMAPDSS_VER_UNKNOWN = 0,
314 OMAPDSS_VER_OMAP24xx,
315 OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */
316 OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */
317 OMAPDSS_VER_OMAP3630,
318 OMAPDSS_VER_AM35xx,
319 OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */
320 OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */
321 OMAPDSS_VER_OMAP4, /* All other OMAP4s */
322 OMAPDSS_VER_OMAP5,
d6279d4a 323 OMAPDSS_VER_AM43xx,
acd18af9
TV		 324};
325
559d6701
TV		 326/* Board specific data */
327struct omap_dss_board_info {
559d6701
TV		 328 int num_devices;
329 struct omap_dss_device **devices;
330 struct omap_dss_device *default_device;
0a200126 331 const char *default_display_name;
5bc416cb
TV		 332 int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
333 void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
62c1dcfc 334 int (*set_min_bus_tput)(struct device *dev, unsigned long r);
acd18af9 335 enum omapdss_version version;
559d6701
TV		 336};
337
b7ee79ab
SS		 338/* Init with the board info */
339extern int omap_display_init(struct omap_dss_board_info *board_data);
ee9dfd82 340/* HDMI mux init*/
9a901683 341extern int omap_hdmi_init(enum omap_hdmi_flags flags);
b7ee79ab 342
559d6701
TV		 343struct omap_video_timings {
344 /* Unit: pixels */
345 u16 x_res;
346 /* Unit: pixels */
347 u16 y_res;
d8d78941
TV		 348 /* Unit: Hz */
349 u32 pixelclock;
559d6701
TV		 350 /* Unit: pixel clocks */
351 u16 hsw; /* Horizontal synchronization pulse width */
352 /* Unit: pixel clocks */
353 u16 hfp; /* Horizontal front porch */
354 /* Unit: pixel clocks */
355 u16 hbp; /* Horizontal back porch */
356 /* Unit: line clocks */
357 u16 vsw; /* Vertical synchronization pulse width */
358 /* Unit: line clocks */
359 u16 vfp; /* Vertical front porch */
360 /* Unit: line clocks */
361 u16 vbp; /* Vertical back porch */
a8d5e41c
AT		 362
363 /* Vsync logic level */
364 enum omap_dss_signal_level vsync_level;
365 /* Hsync logic level */
366 enum omap_dss_signal_level hsync_level;
23c8f88e
AT		 367 /* Interlaced or Progressive timings */
368 bool interlace;
a8d5e41c
AT		 369 /* Pixel clock edge to drive LCD data */
370 enum omap_dss_signal_edge data_pclk_edge;
371 /* Data enable logic level */
372 enum omap_dss_signal_level de_level;
373 /* Pixel clock edges to drive HSYNC and VSYNC signals */
374 enum omap_dss_signal_edge sync_pclk_edge;
559d6701
TV		 375};
376
377#ifdef CONFIG_OMAP2_DSS_VENC
378/* Hardcoded timings for tv modes. Venc only uses these to
379 * identify the mode, and does not actually use the configs
380 * itself. However, the configs should be something that
381 * a normal monitor can also show */
5a1819e3
TK		 382extern const struct omap_video_timings omap_dss_pal_timings;
383extern const struct omap_video_timings omap_dss_ntsc_timings;
559d6701
TV		 384#endif
385
3c07cae2
TV		 386struct omap_dss_cpr_coefs {
387 s16 rr, rg, rb;
388 s16 gr, gg, gb;
389 s16 br, bg, bb;
390};
391
559d6701 392struct omap_overlay_info {
24f13a66
AB		 393 dma_addr_t paddr;
394 dma_addr_t p_uv_addr; /* for NV12 format */
559d6701
TV		 395 u16 screen_width;
396 u16 width;
397 u16 height;
398 enum omap_color_mode color_mode;
399 u8 rotation;
400 enum omap_dss_rotation_type rotation_type;
401 bool mirror;
402
403 u16 pos_x;
404 u16 pos_y;
405 u16 out_width; /* if 0, out_width == width */
406 u16 out_height; /* if 0, out_height == height */
407 u8 global_alpha;
fd28a390 408 u8 pre_mult_alpha;
54128701 409 u8 zorder;
559d6701
TV		 410};
411
412struct omap_overlay {
413 struct kobject kobj;
414 struct list_head list;
415
416 /* static fields */
417 const char *name;
4a9e78ab 418 enum omap_plane id;
559d6701
TV		 419 enum omap_color_mode supported_modes;
420 enum omap_overlay_caps caps;
421
422 /* dynamic fields */
423 struct omap_overlay_manager *manager;
559d6701 424
9d11c321
TV		 425 /*
426 * The following functions do not block:
427 *
428 * is_enabled
429 * set_overlay_info
430 * get_overlay_info
431 *
432 * The rest of the functions may block and cannot be called from
433 * interrupt context
434 */
435
aaa874a9
TV		 436 int (*enable)(struct omap_overlay *ovl);
437 int (*disable)(struct omap_overlay *ovl);
438 bool (*is_enabled)(struct omap_overlay *ovl);
439
559d6701
TV		 440 int (*set_manager)(struct omap_overlay *ovl,
441 struct omap_overlay_manager *mgr);
442 int (*unset_manager)(struct omap_overlay *ovl);
443
444 int (*set_overlay_info)(struct omap_overlay *ovl,
445 struct omap_overlay_info *info);
446 void (*get_overlay_info)(struct omap_overlay *ovl,
447 struct omap_overlay_info *info);
448
449 int (*wait_for_go)(struct omap_overlay *ovl);
794bc4ee
AT		 450
451 struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
559d6701
TV		 452};
453
454struct omap_overlay_manager_info {
455 u32 default_color;
456
457 enum omap_dss_trans_key_type trans_key_type;
458 u32 trans_key;
459 bool trans_enabled;
460
11354dd5 461 bool partial_alpha_enabled;
3c07cae2
TV		 462
463 bool cpr_enable;
464 struct omap_dss_cpr_coefs cpr_coefs;
559d6701
TV		 465};
466
467struct omap_overlay_manager {
468 struct kobject kobj;
559d6701
TV		 469
470 /* static fields */
471 const char *name;
4a9e78ab 472 enum omap_channel id;
559d6701 473 enum omap_overlay_manager_caps caps;
07e327c9 474 struct list_head overlays;
559d6701 475 enum omap_display_type supported_displays;
97f01b3a 476 enum omap_dss_output_id supported_outputs;
559d6701
TV		 477
478 /* dynamic fields */
1f68d9c4 479 struct omap_dss_device *output;
559d6701 480
9d11c321
TV		 481 /*
482 * The following functions do not block:
483 *
484 * set_manager_info
485 * get_manager_info
486 * apply
487 *
488 * The rest of the functions may block and cannot be called from
489 * interrupt context
490 */
491
97f01b3a 492 int (*set_output)(struct omap_overlay_manager *mgr,
1f68d9c4 493 struct omap_dss_device *output);
97f01b3a 494 int (*unset_output)(struct omap_overlay_manager *mgr);
559d6701
TV		 495
496 int (*set_manager_info)(struct omap_overlay_manager *mgr,
497 struct omap_overlay_manager_info *info);
498 void (*get_manager_info)(struct omap_overlay_manager *mgr,
499 struct omap_overlay_manager_info *info);
500
501 int (*apply)(struct omap_overlay_manager *mgr);
502 int (*wait_for_go)(struct omap_overlay_manager *mgr);
3f71cbe7 503 int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
794bc4ee
AT		 504
505 struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
559d6701
TV		 506};
507
e4a9e94c
TV		 508/* 22 pins means 1 clk lane and 10 data lanes */
509#define OMAP_DSS_MAX_DSI_PINS 22
510
511struct omap_dsi_pin_config {
512 int num_pins;
513 /*
514 * pin numbers in the following order:
515 * clk+, clk-
516 * data1+, data1-
517 * data2+, data2-
518 * ...
519 */
520 int pins[OMAP_DSS_MAX_DSI_PINS];
521};
522
749feffa
AT		 523struct omap_dss_writeback_info {
524 u32 paddr;
525 u32 p_uv_addr;
526 u16 buf_width;
527 u16 width;
528 u16 height;
529 enum omap_color_mode color_mode;
530 u8 rotation;
531 enum omap_dss_rotation_type rotation_type;
532 bool mirror;
533 u8 pre_mult_alpha;
534};
535
0b24edb1
TV		 536struct omapdss_dpi_ops {
537 int (*connect)(struct omap_dss_device *dssdev,
538 struct omap_dss_device *dst);
539 void (*disconnect)(struct omap_dss_device *dssdev,
540 struct omap_dss_device *dst);
541
542 int (*enable)(struct omap_dss_device *dssdev);
543 void (*disable)(struct omap_dss_device *dssdev);
544
545 int (*check_timings)(struct omap_dss_device *dssdev,
546 struct omap_video_timings *timings);
547 void (*set_timings)(struct omap_dss_device *dssdev,
548 struct omap_video_timings *timings);
549 void (*get_timings)(struct omap_dss_device *dssdev,
550 struct omap_video_timings *timings);
551
552 void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines);
553};
554
b1082dfd
TV		 555struct omapdss_sdi_ops {
556 int (*connect)(struct omap_dss_device *dssdev,
557 struct omap_dss_device *dst);
558 void (*disconnect)(struct omap_dss_device *dssdev,
559 struct omap_dss_device *dst);
560
561 int (*enable)(struct omap_dss_device *dssdev);
562 void (*disable)(struct omap_dss_device *dssdev);
563
564 int (*check_timings)(struct omap_dss_device *dssdev,
565 struct omap_video_timings *timings);
566 void (*set_timings)(struct omap_dss_device *dssdev,
567 struct omap_video_timings *timings);
568 void (*get_timings)(struct omap_dss_device *dssdev,
569 struct omap_video_timings *timings);
570
571 void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs);
572};
573
7700c2d4
TV		 574struct omapdss_dvi_ops {
575 int (*connect)(struct omap_dss_device *dssdev,
576 struct omap_dss_device *dst);
577 void (*disconnect)(struct omap_dss_device *dssdev,
578 struct omap_dss_device *dst);
579
580 int (*enable)(struct omap_dss_device *dssdev);
581 void (*disable)(struct omap_dss_device *dssdev);
582
583 int (*check_timings)(struct omap_dss_device *dssdev,
584 struct omap_video_timings *timings);
585 void (*set_timings)(struct omap_dss_device *dssdev,
586 struct omap_video_timings *timings);
587 void (*get_timings)(struct omap_dss_device *dssdev,
588 struct omap_video_timings *timings);
589};
590
fb8efa49
TV		 591struct omapdss_atv_ops {
592 int (*connect)(struct omap_dss_device *dssdev,
593 struct omap_dss_device *dst);
594 void (*disconnect)(struct omap_dss_device *dssdev,
595 struct omap_dss_device *dst);
596
597 int (*enable)(struct omap_dss_device *dssdev);
598 void (*disable)(struct omap_dss_device *dssdev);
599
600 int (*check_timings)(struct omap_dss_device *dssdev,
601 struct omap_video_timings *timings);
602 void (*set_timings)(struct omap_dss_device *dssdev,
603 struct omap_video_timings *timings);
604 void (*get_timings)(struct omap_dss_device *dssdev,
605 struct omap_video_timings *timings);
606
607 void (*set_type)(struct omap_dss_device *dssdev,
608 enum omap_dss_venc_type type);
609 void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev,
610 bool invert_polarity);
611
612 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
613 u32 (*get_wss)(struct omap_dss_device *dssdev);
614};
615
0b450c31
TV		 616struct omapdss_hdmi_ops {
617 int (*connect)(struct omap_dss_device *dssdev,
618 struct omap_dss_device *dst);
619 void (*disconnect)(struct omap_dss_device *dssdev,
620 struct omap_dss_device *dst);
621
622 int (*enable)(struct omap_dss_device *dssdev);
623 void (*disable)(struct omap_dss_device *dssdev);
624
625 int (*check_timings)(struct omap_dss_device *dssdev,
626 struct omap_video_timings *timings);
627 void (*set_timings)(struct omap_dss_device *dssdev,
628 struct omap_video_timings *timings);
629 void (*get_timings)(struct omap_dss_device *dssdev,
630 struct omap_video_timings *timings);
631
632 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
633 bool (*detect)(struct omap_dss_device *dssdev);
634
8c071caa
TV		 635 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
636 int (*set_infoframe)(struct omap_dss_device *dssdev,
637 const struct hdmi_avi_infoframe *avi);
638
0b450c31
TV		 639 /*
640 * Note: These functions might sleep. Do not call while
641 * holding a spinlock/readlock.
642 */
643 int (*audio_enable)(struct omap_dss_device *dssdev);
644 void (*audio_disable)(struct omap_dss_device *dssdev);
645 bool (*audio_supported)(struct omap_dss_device *dssdev);
646 int (*audio_config)(struct omap_dss_device *dssdev,
647 struct omap_dss_audio *audio);
648 /* Note: These functions may not sleep */
649 int (*audio_start)(struct omap_dss_device *dssdev);
650 void (*audio_stop)(struct omap_dss_device *dssdev);
651};
652
deb16df8
TV		 653struct omapdss_dsi_ops {
654 int (*connect)(struct omap_dss_device *dssdev,
655 struct omap_dss_device *dst);
656 void (*disconnect)(struct omap_dss_device *dssdev,
657 struct omap_dss_device *dst);
658
659 int (*enable)(struct omap_dss_device *dssdev);
660 void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
661 bool enter_ulps);
662
663 /* bus configuration */
664 int (*set_config)(struct omap_dss_device *dssdev,
665 const struct omap_dss_dsi_config *cfg);
666 int (*configure_pins)(struct omap_dss_device *dssdev,
667 const struct omap_dsi_pin_config *pin_cfg);
668
669 void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
670 bool enable);
671 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
672
673 int (*update)(struct omap_dss_device *dssdev, int channel,
674 void (*callback)(int, void *), void *data);
675
676 void (*bus_lock)(struct omap_dss_device *dssdev);
677 void (*bus_unlock)(struct omap_dss_device *dssdev);
678
679 int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
680 void (*disable_video_output)(struct omap_dss_device *dssdev,
681 int channel);
682
683 int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
684 int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
685 int vc_id);
686 void (*release_vc)(struct omap_dss_device *dssdev, int channel);
687
688 /* data transfer */
689 int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
690 u8 *data, int len);
691 int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
692 u8 *data, int len);
693 int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
694 u8 *data, int len);
695
696 int (*gen_write)(struct omap_dss_device *dssdev, int channel,
697 u8 *data, int len);
698 int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
699 u8 *data, int len);
700 int (*gen_read)(struct omap_dss_device *dssdev, int channel,
701 u8 *reqdata, int reqlen,
702 u8 *data, int len);
703
704 int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
705
706 int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
707 int channel, u16 plen);
708};
709
559d6701 710struct omap_dss_device {
ecc8b370 711 struct device *dev;
559d6701 712
4f3e44ea
TV		 713 struct module *owner;
714
2e7e3dc7
TV		 715 struct list_head panel_list;
716
717 /* alias in the form of "display%d" */
718 char alias[16];
719
559d6701 720 enum omap_display_type type;
1f68d9c4 721 enum omap_display_type output_type;
559d6701
TV		 722
723 union {
724 struct {
725 u8 data_lines;
726 } dpi;
727
728 struct {
729 u8 channel;
730 u8 data_lines;
731 } rfbi;
732
733 struct {
734 u8 datapairs;
735 } sdi;
736
737 struct {
a72b64b9 738 int module;
559d6701
TV		 739 } dsi;
740
741 struct {
742 enum omap_dss_venc_type type;
743 bool invert_polarity;
744 } venc;
745 } phy;
746
747 struct {
748 struct omap_video_timings timings;
749
a3b3cc2b 750 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
7e951ee9 751 enum omap_dss_dsi_mode dsi_mode;
559d6701
TV		 752 } panel;
753
754 struct {
755 u8 pixel_size;
756 struct rfbi_timings rfbi_timings;
559d6701
TV		 757 } ctrl;
758
559d6701
TV		 759 const char *name;
760
761 /* used to match device to driver */
762 const char *driver_name;
763
764 void *data;
765
766 struct omap_dss_driver *driver;
767
0b24edb1
TV		 768 union {
769 const struct omapdss_dpi_ops *dpi;
b1082dfd 770 const struct omapdss_sdi_ops *sdi;
7700c2d4 771 const struct omapdss_dvi_ops *dvi;
0b450c31 772 const struct omapdss_hdmi_ops *hdmi;
fb8efa49 773 const struct omapdss_atv_ops *atv;
deb16df8 774 const struct omapdss_dsi_ops *dsi;
0b24edb1
TV		 775 } ops;
776
559d6701
TV		 777 /* helper variable for driver suspend/resume */
778 bool activate_after_resume;
779
780 enum omap_display_caps caps;
781
a73fdc64 782 struct omap_dss_device *src;
559d6701
TV		 783
784 enum omap_dss_display_state state;
785
9c0b8420
RN		 786 enum omap_dss_audio_state audio_state;
787
1f68d9c4
TV		 788 /* OMAP DSS output specific fields */
789
790 struct list_head list;
791
792 /* DISPC channel for this output */
793 enum omap_channel dispc_channel;
794
795 /* output instance */
796 enum omap_dss_output_id id;
797
798 /* dynamic fields */
799 struct omap_overlay_manager *manager;
800
9560dc10 801 struct omap_dss_device *dst;
559d6701
TV		 802};
803
c49d005b
TV		 804struct omap_dss_hdmi_data
805{
cca35017
TV		 806 int ct_cp_hpd_gpio;
807 int ls_oe_gpio;
c49d005b
TV		 808 int hpd_gpio;
809};
810
559d6701 811struct omap_dss_driver {
559d6701
TV		 812 int (*probe)(struct omap_dss_device *);
813 void (*remove)(struct omap_dss_device *);
814
a7e71e7f
TV		 815 int (*connect)(struct omap_dss_device *dssdev);
816 void (*disconnect)(struct omap_dss_device *dssdev);
817
559d6701
TV		 818 int (*enable)(struct omap_dss_device *display);
819 void (*disable)(struct omap_dss_device *display);
559d6701
TV		 820 int (*run_test)(struct omap_dss_device *display, int test);
821
18946f62
TV		 822 int (*update)(struct omap_dss_device *dssdev,
823 u16 x, u16 y, u16 w, u16 h);
824 int (*sync)(struct omap_dss_device *dssdev);
825
559d6701 826 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
225b650d 827 int (*get_te)(struct omap_dss_device *dssdev);
559d6701
TV		 828
829 u8 (*get_rotate)(struct omap_dss_device *dssdev);
830 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
831
832 bool (*get_mirror)(struct omap_dss_device *dssdev);
833 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
834
835 int (*memory_read)(struct omap_dss_device *dssdev,
836 void *buf, size_t size,
837 u16 x, u16 y, u16 w, u16 h);
96adcece
TV		 838
839 void (*get_resolution)(struct omap_dss_device *dssdev,
840 u16 *xres, u16 *yres);
7a0987bf
JN		 841 void (*get_dimensions)(struct omap_dss_device *dssdev,
842 u32 *width, u32 *height);
a2699504 843 int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
36511312 844
69b2048f
TV		 845 int (*check_timings)(struct omap_dss_device *dssdev,
846 struct omap_video_timings *timings);
847 void (*set_timings)(struct omap_dss_device *dssdev,
848 struct omap_video_timings *timings);
849 void (*get_timings)(struct omap_dss_device *dssdev,
850 struct omap_video_timings *timings);
851
36511312
TV		 852 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
853 u32 (*get_wss)(struct omap_dss_device *dssdev);
3d5e0ef7
TV		 854
855 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
df4769c9 856 bool (*detect)(struct omap_dss_device *dssdev);
9c0b8420 857
8c071caa
TV		 858 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
859 int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev,
860 const struct hdmi_avi_infoframe *avi);
861
9c0b8420
RN		 862 /*
863 * For display drivers that support audio. This encompasses
864 * HDMI and DisplayPort at the moment.
865 */
866 /*
867 * Note: These functions might sleep. Do not call while
868 * holding a spinlock/readlock.
869 */
870 int (*audio_enable)(struct omap_dss_device *dssdev);
871 void (*audio_disable)(struct omap_dss_device *dssdev);
872 bool (*audio_supported)(struct omap_dss_device *dssdev);
873 int (*audio_config)(struct omap_dss_device *dssdev,
874 struct omap_dss_audio *audio);
875 /* Note: These functions may not sleep */
876 int (*audio_start)(struct omap_dss_device *dssdev);
877 void (*audio_stop)(struct omap_dss_device *dssdev);
878
559d6701
TV		 879};
880
b2c7d54f 881enum omapdss_version omapdss_get_version(void);
591a0ac7 882bool omapdss_is_initialized(void);
b2c7d54f 883
559d6701
TV		 884int omap_dss_register_driver(struct omap_dss_driver *);
885void omap_dss_unregister_driver(struct omap_dss_driver *);
886
2e7e3dc7
TV		 887int omapdss_register_display(struct omap_dss_device *dssdev);
888void omapdss_unregister_display(struct omap_dss_device *dssdev);
889
d35317a4 890struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev);
559d6701
TV		 891void omap_dss_put_device(struct omap_dss_device *dssdev);
892#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
893struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
894struct omap_dss_device *omap_dss_find_device(void *data,
895 int (*match)(struct omap_dss_device *dssdev, void *data));
2bbcce5e 896const char *omapdss_get_default_display_name(void);
559d6701 897
6fcd485b
TV		 898void videomode_to_omap_video_timings(const struct videomode *vm,
899 struct omap_video_timings *ovt);
900void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
901 struct videomode *vm);
902
eda34273
TV		 903int dss_feat_get_num_mgrs(void);
904int dss_feat_get_num_ovls(void);
905enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
906enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
907enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
908
909
910
559d6701
TV		 911int omap_dss_get_num_overlay_managers(void);
912struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
913
914int omap_dss_get_num_overlays(void);
915struct omap_overlay *omap_dss_get_overlay(int num);
916
5d47dbc8
TV		 917int omapdss_register_output(struct omap_dss_device *output);
918void omapdss_unregister_output(struct omap_dss_device *output);
1f68d9c4
TV		 919struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
920struct omap_dss_device *omap_dss_find_output(const char *name);
921struct omap_dss_device *omap_dss_find_output_by_node(struct device_node *node);
922int omapdss_output_set_device(struct omap_dss_device *out,
6d71b923 923 struct omap_dss_device *dssdev);
1f68d9c4 924int omapdss_output_unset_device(struct omap_dss_device *out);
484dc404 925
1f68d9c4 926struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
be8e8e1c
TV		 927struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev);
928
96adcece
TV		 929void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
930 u16 *xres, u16 *yres);
a2699504 931int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
4b6430fc
GI		 932void omapdss_default_get_timings(struct omap_dss_device *dssdev,
933 struct omap_video_timings *timings);
a2699504 934
559d6701
TV		 935typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
936int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
937int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
938
348be69d
TV		 939u32 dispc_read_irqstatus(void);
940void dispc_clear_irqstatus(u32 mask);
941u32 dispc_read_irqenable(void);
942void dispc_write_irqenable(u32 mask);
943
944int dispc_request_irq(irq_handler_t handler, void *dev_id);
945void dispc_free_irq(void *dev_id);
946
947int dispc_runtime_get(void);
948void dispc_runtime_put(void);
949
950void dispc_mgr_enable(enum omap_channel channel, bool enable);
951bool dispc_mgr_is_enabled(enum omap_channel channel);
952u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
953u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
954u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
955bool dispc_mgr_go_busy(enum omap_channel channel);
956void dispc_mgr_go(enum omap_channel channel);
957void dispc_mgr_set_lcd_config(enum omap_channel channel,
958 const struct dss_lcd_mgr_config *config);
959void dispc_mgr_set_timings(enum omap_channel channel,
960 const struct omap_video_timings *timings);
961void dispc_mgr_setup(enum omap_channel channel,
962 const struct omap_overlay_manager_info *info);
963
964int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
965 const struct omap_overlay_info *oi,
966 const struct omap_video_timings *timings,
967 int *x_predecim, int *y_predecim);
968
969int dispc_ovl_enable(enum omap_plane plane, bool enable);
970bool dispc_ovl_enabled(enum omap_plane plane);
971void dispc_ovl_set_channel_out(enum omap_plane plane,
972 enum omap_channel channel);
973int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
974 bool replication, const struct omap_video_timings *mgr_timings,
975 bool mem_to_mem);
976
8dd2491a
TV		 977int omapdss_compat_init(void);
978void omapdss_compat_uninit(void);
979
a97a9634 980struct dss_mgr_ops {
a7e71e7f 981 int (*connect)(struct omap_overlay_manager *mgr,
1f68d9c4 982 struct omap_dss_device *dst);
a7e71e7f 983 void (*disconnect)(struct omap_overlay_manager *mgr,
1f68d9c4 984 struct omap_dss_device *dst);
a7e71e7f 985
a97a9634
TV		 986 void (*start_update)(struct omap_overlay_manager *mgr);
987 int (*enable)(struct omap_overlay_manager *mgr);
988 void (*disable)(struct omap_overlay_manager *mgr);
989 void (*set_timings)(struct omap_overlay_manager *mgr,
990 const struct omap_video_timings *timings);
991 void (*set_lcd_config)(struct omap_overlay_manager *mgr,
992 const struct dss_lcd_mgr_config *config);
993 int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
994 void (*handler)(void *), void *data);
995 void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
996 void (*handler)(void *), void *data);
997};
998
999int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
1000void dss_uninstall_mgr_ops(void);
1001
a7e71e7f 1002int dss_mgr_connect(struct omap_overlay_manager *mgr,
1f68d9c4 1003 struct omap_dss_device *dst);
a7e71e7f 1004void dss_mgr_disconnect(struct omap_overlay_manager *mgr,
1f68d9c4 1005 struct omap_dss_device *dst);
a97a9634
TV		 1006void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
1007 const struct omap_video_timings *timings);
1008void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
1009 const struct dss_lcd_mgr_config *config);
1010int dss_mgr_enable(struct omap_overlay_manager *mgr);
1011void dss_mgr_disable(struct omap_overlay_manager *mgr);
1012void dss_mgr_start_update(struct omap_overlay_manager *mgr);
1013int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
1014 void (*handler)(void *), void *data);
1015void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
1016 void (*handler)(void *), void *data);
a7e71e7f
TV		 1017
1018static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
1019{
a73fdc64 1020 return dssdev->src;
a7e71e7f
TV		 1021}
1022
1023static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
1024{
1025 return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
1026}
1027
4e7470dd
TV		 1028struct device_node *
1029omapdss_of_get_next_port(const struct device_node *parent,
1030 struct device_node *prev);
1031
1032struct device_node *
1033omapdss_of_get_next_endpoint(const struct device_node *parent,
1034 struct device_node *prev);
1035
1036struct device_node *
1037omapdss_of_get_first_endpoint(const struct device_node *parent);
1038
1039struct omap_dss_device *
1040omapdss_of_find_source_for_first_ep(struct device_node *node);
1041
559d6701 1042#endif
Linux kernel - Deliverables
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