[deliverable/linux.git] / include / video / omapdss.h

/*
 * Copyright (C) 2008 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __OMAP_OMAPDSS_H
#define __OMAP_OMAPDSS_H

#include <linux/list.h>
#include <linux/kobject.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <asm/atomic.h>

#define DISPC_IRQ_FRAMEDONE		(1 << 0)
#define DISPC_IRQ_VSYNC			(1 << 1)
#define DISPC_IRQ_EVSYNC_EVEN		(1 << 2)
#define DISPC_IRQ_EVSYNC_ODD		(1 << 3)
#define DISPC_IRQ_ACBIAS_COUNT_STAT	(1 << 4)
#define DISPC_IRQ_PROG_LINE_NUM		(1 << 5)
#define DISPC_IRQ_GFX_FIFO_UNDERFLOW	(1 << 6)
#define DISPC_IRQ_GFX_END_WIN		(1 << 7)
#define DISPC_IRQ_PAL_GAMMA_MASK	(1 << 8)
#define DISPC_IRQ_OCP_ERR		(1 << 9)
#define DISPC_IRQ_VID1_FIFO_UNDERFLOW	(1 << 10)
#define DISPC_IRQ_VID1_END_WIN		(1 << 11)
#define DISPC_IRQ_VID2_FIFO_UNDERFLOW	(1 << 12)
#define DISPC_IRQ_VID2_END_WIN		(1 << 13)
#define DISPC_IRQ_SYNC_LOST		(1 << 14)
#define DISPC_IRQ_SYNC_LOST_DIGIT	(1 << 15)
#define DISPC_IRQ_WAKEUP		(1 << 16)
#define DISPC_IRQ_SYNC_LOST2		(1 << 17)
#define DISPC_IRQ_VSYNC2		(1 << 18)
#define DISPC_IRQ_ACBIAS_COUNT_STAT2	(1 << 21)
#define DISPC_IRQ_FRAMEDONE2		(1 << 22)

struct omap_dss_device;
struct omap_overlay_manager;

enum omap_display_type {
	OMAP_DISPLAY_TYPE_NONE		= 0,
	OMAP_DISPLAY_TYPE_DPI		= 1 << 0,
	OMAP_DISPLAY_TYPE_DBI		= 1 << 1,
	OMAP_DISPLAY_TYPE_SDI		= 1 << 2,
	OMAP_DISPLAY_TYPE_DSI		= 1 << 3,
	OMAP_DISPLAY_TYPE_VENC		= 1 << 4,
	OMAP_DISPLAY_TYPE_HDMI		= 1 << 5,
};

enum omap_plane {
	OMAP_DSS_GFX	= 0,
	OMAP_DSS_VIDEO1	= 1,
	OMAP_DSS_VIDEO2	= 2
};

enum omap_channel {
	OMAP_DSS_CHANNEL_LCD	= 0,
	OMAP_DSS_CHANNEL_DIGIT	= 1,
	OMAP_DSS_CHANNEL_LCD2	= 2,
};

enum omap_color_mode {
	OMAP_DSS_COLOR_CLUT1	= 1 << 0,  /* BITMAP 1 */
	OMAP_DSS_COLOR_CLUT2	= 1 << 1,  /* BITMAP 2 */
	OMAP_DSS_COLOR_CLUT4	= 1 << 2,  /* BITMAP 4 */
	OMAP_DSS_COLOR_CLUT8	= 1 << 3,  /* BITMAP 8 */
	OMAP_DSS_COLOR_RGB12U	= 1 << 4,  /* RGB12, 16-bit container */
	OMAP_DSS_COLOR_ARGB16	= 1 << 5,  /* ARGB16 */
	OMAP_DSS_COLOR_RGB16	= 1 << 6,  /* RGB16 */
	OMAP_DSS_COLOR_RGB24U	= 1 << 7,  /* RGB24, 32-bit container */
	OMAP_DSS_COLOR_RGB24P	= 1 << 8,  /* RGB24, 24-bit container */
	OMAP_DSS_COLOR_YUV2	= 1 << 9,  /* YUV2 4:2:2 co-sited */
	OMAP_DSS_COLOR_UYVY	= 1 << 10, /* UYVY 4:2:2 co-sited */
	OMAP_DSS_COLOR_ARGB32	= 1 << 11, /* ARGB32 */
	OMAP_DSS_COLOR_RGBA32	= 1 << 12, /* RGBA32 */
	OMAP_DSS_COLOR_RGBX32	= 1 << 13, /* RGBx32 */
};

enum omap_lcd_display_type {
	OMAP_DSS_LCD_DISPLAY_STN,
	OMAP_DSS_LCD_DISPLAY_TFT,
};

enum omap_dss_load_mode {
	OMAP_DSS_LOAD_CLUT_AND_FRAME	= 0,
	OMAP_DSS_LOAD_CLUT_ONLY		= 1,
	OMAP_DSS_LOAD_FRAME_ONLY	= 2,
	OMAP_DSS_LOAD_CLUT_ONCE_FRAME	= 3,
};

enum omap_dss_trans_key_type {
	OMAP_DSS_COLOR_KEY_GFX_DST = 0,
	OMAP_DSS_COLOR_KEY_VID_SRC = 1,
};

enum omap_rfbi_te_mode {
	OMAP_DSS_RFBI_TE_MODE_1 = 1,
	OMAP_DSS_RFBI_TE_MODE_2 = 2,
};

enum omap_panel_config {
	OMAP_DSS_LCD_IVS		= 1<<0,
	OMAP_DSS_LCD_IHS		= 1<<1,
	OMAP_DSS_LCD_IPC		= 1<<2,
	OMAP_DSS_LCD_IEO		= 1<<3,
	OMAP_DSS_LCD_RF			= 1<<4,
	OMAP_DSS_LCD_ONOFF		= 1<<5,

	OMAP_DSS_LCD_TFT		= 1<<20,
};

enum omap_dss_venc_type {
	OMAP_DSS_VENC_TYPE_COMPOSITE,
	OMAP_DSS_VENC_TYPE_SVIDEO,
};

enum omap_display_caps {
	OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE	= 1 << 0,
	OMAP_DSS_DISPLAY_CAP_TEAR_ELIM		= 1 << 1,
};

enum omap_dss_update_mode {
	OMAP_DSS_UPDATE_DISABLED = 0,
	OMAP_DSS_UPDATE_AUTO,
	OMAP_DSS_UPDATE_MANUAL,
};

enum omap_dss_display_state {
	OMAP_DSS_DISPLAY_DISABLED = 0,
	OMAP_DSS_DISPLAY_ACTIVE,
	OMAP_DSS_DISPLAY_SUSPENDED,
};

/* XXX perhaps this should be removed */
enum omap_dss_overlay_managers {
	OMAP_DSS_OVL_MGR_LCD,
	OMAP_DSS_OVL_MGR_TV,
	OMAP_DSS_OVL_MGR_LCD2,
};

enum omap_dss_rotation_type {
	OMAP_DSS_ROT_DMA = 0,
	OMAP_DSS_ROT_VRFB = 1,
};

/* clockwise rotation angle */
enum omap_dss_rotation_angle {
	OMAP_DSS_ROT_0   = 0,
	OMAP_DSS_ROT_90  = 1,
	OMAP_DSS_ROT_180 = 2,
	OMAP_DSS_ROT_270 = 3,
};

enum omap_overlay_caps {
	OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
	OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
};

enum omap_overlay_manager_caps {
	OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
};

enum omap_dss_clk_source {
	OMAP_DSS_CLK_SRC_FCK = 0,		/* OMAP2/3: DSS1_ALWON_FCLK
						 * OMAP4: DSS_FCLK */
	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,	/* OMAP3: DSI1_PLL_FCLK
						 * OMAP4: PLL1_CLK1 */
	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,	/* OMAP3: DSI2_PLL_FCLK
						 * OMAP4: PLL1_CLK2 */
};

/* RFBI */

struct rfbi_timings {
	int cs_on_time;
	int cs_off_time;
	int we_on_time;
	int we_off_time;
	int re_on_time;
	int re_off_time;
	int we_cycle_time;
	int re_cycle_time;
	int cs_pulse_width;
	int access_time;

	int clk_div;

	u32 tim[5];             /* set by rfbi_convert_timings() */

	int converted;
};

void omap_rfbi_write_command(const void *buf, u32 len);
void omap_rfbi_read_data(void *buf, u32 len);
void omap_rfbi_write_data(const void *buf, u32 len);
void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
		u16 x, u16 y,
		u16 w, u16 h);
int omap_rfbi_enable_te(bool enable, unsigned line);
int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
			     unsigned hs_pulse_time, unsigned vs_pulse_time,
			     int hs_pol_inv, int vs_pol_inv, int extif_div);

/* DSI */
void dsi_bus_lock(struct omap_dss_device *dssdev);
void dsi_bus_unlock(struct omap_dss_device *dssdev);
int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
		int len);
int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel,
		u8 dcs_cmd);
int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 param);
int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
		u8 *data, int len);
int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 *buf, int buflen);
int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 *data);
int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 *data1, u8 *data2);
int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
		u16 len);
int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);

/* Board specific data */
struct omap_dss_board_info {
	int (*get_last_off_on_transaction_id)(struct device *dev);
	int num_devices;
	struct omap_dss_device **devices;
	struct omap_dss_device *default_device;
	void (*dsi_mux_pads)(bool enable);
};

#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
/* Init with the board info */
extern int omap_display_init(struct omap_dss_board_info *board_data);
#else
static inline int omap_display_init(struct omap_dss_board_info *board_data)
{
	return 0;
}
#endif

struct omap_display_platform_data {
	struct omap_dss_board_info *board_data;
	/* TODO: Additional members to be added when PM is considered */

	bool (*opt_clock_available)(const char *clk_role);
};

struct omap_video_timings {
	/* Unit: pixels */
	u16 x_res;
	/* Unit: pixels */
	u16 y_res;
	/* Unit: KHz */
	u32 pixel_clock;
	/* Unit: pixel clocks */
	u16 hsw;	/* Horizontal synchronization pulse width */
	/* Unit: pixel clocks */
	u16 hfp;	/* Horizontal front porch */
	/* Unit: pixel clocks */
	u16 hbp;	/* Horizontal back porch */
	/* Unit: line clocks */
	u16 vsw;	/* Vertical synchronization pulse width */
	/* Unit: line clocks */
	u16 vfp;	/* Vertical front porch */
	/* Unit: line clocks */
	u16 vbp;	/* Vertical back porch */
};

#ifdef CONFIG_OMAP2_DSS_VENC
/* Hardcoded timings for tv modes. Venc only uses these to
 * identify the mode, and does not actually use the configs
 * itself. However, the configs should be something that
 * a normal monitor can also show */
extern const struct omap_video_timings omap_dss_pal_timings;
extern const struct omap_video_timings omap_dss_ntsc_timings;
#endif

struct omap_overlay_info {
	bool enabled;

	u32 paddr;
	void __iomem *vaddr;
	u16 screen_width;
	u16 width;
	u16 height;
	enum omap_color_mode color_mode;
	u8 rotation;
	enum omap_dss_rotation_type rotation_type;
	bool mirror;

	u16 pos_x;
	u16 pos_y;
	u16 out_width;	/* if 0, out_width == width */
	u16 out_height;	/* if 0, out_height == height */
	u8 global_alpha;
	u8 pre_mult_alpha;
};

struct omap_overlay {
	struct kobject kobj;
	struct list_head list;

	/* static fields */
	const char *name;
	int id;
	enum omap_color_mode supported_modes;
	enum omap_overlay_caps caps;

	/* dynamic fields */
	struct omap_overlay_manager *manager;
	struct omap_overlay_info info;

	/* if true, info has been changed, but not applied() yet */
	bool info_dirty;

	int (*set_manager)(struct omap_overlay *ovl,
		struct omap_overlay_manager *mgr);
	int (*unset_manager)(struct omap_overlay *ovl);

	int (*set_overlay_info)(struct omap_overlay *ovl,
			struct omap_overlay_info *info);
	void (*get_overlay_info)(struct omap_overlay *ovl,
			struct omap_overlay_info *info);

	int (*wait_for_go)(struct omap_overlay *ovl);
};

struct omap_overlay_manager_info {
	u32 default_color;

	enum omap_dss_trans_key_type trans_key_type;
	u32 trans_key;
	bool trans_enabled;

	bool alpha_enabled;
};

struct omap_overlay_manager {
	struct kobject kobj;
	struct list_head list;

	/* static fields */
	const char *name;
	int id;
	enum omap_overlay_manager_caps caps;
	int num_overlays;
	struct omap_overlay **overlays;
	enum omap_display_type supported_displays;

	/* dynamic fields */
	struct omap_dss_device *device;
	struct omap_overlay_manager_info info;

	bool device_changed;
	/* if true, info has been changed but not applied() yet */
	bool info_dirty;

	int (*set_device)(struct omap_overlay_manager *mgr,
		struct omap_dss_device *dssdev);
	int (*unset_device)(struct omap_overlay_manager *mgr);

	int (*set_manager_info)(struct omap_overlay_manager *mgr,
			struct omap_overlay_manager_info *info);
	void (*get_manager_info)(struct omap_overlay_manager *mgr,
			struct omap_overlay_manager_info *info);

	int (*apply)(struct omap_overlay_manager *mgr);
	int (*wait_for_go)(struct omap_overlay_manager *mgr);
	int (*wait_for_vsync)(struct omap_overlay_manager *mgr);

	int (*enable)(struct omap_overlay_manager *mgr);
	int (*disable)(struct omap_overlay_manager *mgr);
};

struct omap_dss_device {
	struct device dev;

	enum omap_display_type type;

	enum omap_channel channel;

	union {
		struct {
			u8 data_lines;
		} dpi;

		struct {
			u8 channel;
			u8 data_lines;
		} rfbi;

		struct {
			u8 datapairs;
		} sdi;

		struct {
			u8 clk_lane;
			u8 clk_pol;
			u8 data1_lane;
			u8 data1_pol;
			u8 data2_lane;
			u8 data2_pol;

			int module;

			bool ext_te;
			u8 ext_te_gpio;
		} dsi;

		struct {
			enum omap_dss_venc_type type;
			bool invert_polarity;
		} venc;
	} phy;

	struct {
		struct {
			struct {
				u16 lck_div;
				u16 pck_div;
				enum omap_dss_clk_source lcd_clk_src;
			} channel;

			enum omap_dss_clk_source dispc_fclk_src;
		} dispc;

		struct {
			u16 regn;
			u16 regm;
			u16 regm_dispc;
			u16 regm_dsi;

			u16 lp_clk_div;
			enum omap_dss_clk_source dsi_fclk_src;
		} dsi;

		struct {
			u16 regn;
			u16 regm2;
		} hdmi;
	} clocks;

	struct {
		struct omap_video_timings timings;

		int acbi;	/* ac-bias pin transitions per interrupt */
		/* Unit: line clocks */
		int acb;	/* ac-bias pin frequency */

		enum omap_panel_config config;
	} panel;

	struct {
		u8 pixel_size;
		struct rfbi_timings rfbi_timings;
	} ctrl;

	int reset_gpio;

	int max_backlight_level;

	const char *name;

	/* used to match device to driver */
	const char *driver_name;

	void *data;

	struct omap_dss_driver *driver;

	/* helper variable for driver suspend/resume */
	bool activate_after_resume;

	enum omap_display_caps caps;

	struct omap_overlay_manager *manager;

	enum omap_dss_display_state state;

	/* platform specific  */
	int (*platform_enable)(struct omap_dss_device *dssdev);
	void (*platform_disable)(struct omap_dss_device *dssdev);
	int (*set_backlight)(struct omap_dss_device *dssdev, int level);
	int (*get_backlight)(struct omap_dss_device *dssdev);
};

struct omap_dss_driver {
	struct device_driver driver;

	int (*probe)(struct omap_dss_device *);
	void (*remove)(struct omap_dss_device *);

	int (*enable)(struct omap_dss_device *display);
	void (*disable)(struct omap_dss_device *display);
	int (*suspend)(struct omap_dss_device *display);
	int (*resume)(struct omap_dss_device *display);
	int (*run_test)(struct omap_dss_device *display, int test);

	int (*set_update_mode)(struct omap_dss_device *dssdev,
			enum omap_dss_update_mode);
	enum omap_dss_update_mode (*get_update_mode)(
			struct omap_dss_device *dssdev);

	int (*update)(struct omap_dss_device *dssdev,
			       u16 x, u16 y, u16 w, u16 h);
	int (*sync)(struct omap_dss_device *dssdev);

	int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
	int (*get_te)(struct omap_dss_device *dssdev);

	u8 (*get_rotate)(struct omap_dss_device *dssdev);
	int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);

	bool (*get_mirror)(struct omap_dss_device *dssdev);
	int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);

	int (*memory_read)(struct omap_dss_device *dssdev,
			void *buf, size_t size,
			u16 x, u16 y, u16 w, u16 h);

	void (*get_resolution)(struct omap_dss_device *dssdev,
			u16 *xres, u16 *yres);
	void (*get_dimensions)(struct omap_dss_device *dssdev,
			u32 *width, u32 *height);
	int (*get_recommended_bpp)(struct omap_dss_device *dssdev);

	int (*check_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
	void (*set_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
	void (*get_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);

	int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
	u32 (*get_wss)(struct omap_dss_device *dssdev);
};

int omap_dss_register_driver(struct omap_dss_driver *);
void omap_dss_unregister_driver(struct omap_dss_driver *);

void omap_dss_get_device(struct omap_dss_device *dssdev);
void omap_dss_put_device(struct omap_dss_device *dssdev);
#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
struct omap_dss_device *omap_dss_find_device(void *data,
		int (*match)(struct omap_dss_device *dssdev, void *data));

int omap_dss_start_device(struct omap_dss_device *dssdev);
void omap_dss_stop_device(struct omap_dss_device *dssdev);

int omap_dss_get_num_overlay_managers(void);
struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);

int omap_dss_get_num_overlays(void);
struct omap_overlay *omap_dss_get_overlay(int num);

void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
		u16 *xres, u16 *yres);
int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);

typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);

int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
		unsigned long timeout);

#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)

void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
		bool enable);
int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);

int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
				    u16 *x, u16 *y, u16 *w, u16 *h,
				    bool enlarge_update_area);
int omap_dsi_update(struct omap_dss_device *dssdev,
		int channel,
		u16 x, u16 y, u16 w, u16 h,
		void (*callback)(int, void *), void *data);
int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);

int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
		bool disconnect_lanes, bool enter_ulps);

int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
void dpi_set_timings(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
int dpi_check_timings(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);

int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);

int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
		u16 *x, u16 *y, u16 *w, u16 *h);
int omap_rfbi_update(struct omap_dss_device *dssdev,
		u16 x, u16 y, u16 w, u16 h,
		void (*callback)(void *), void *data);

#endif
Commit	Line	Data
559d6701	1	/*
559d6701 TV	2	* Copyright (C) 2008 Nokia Corporation
	3	* Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published by
	7	* the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
a0b38cc4 TV	18	#ifndef __OMAP_OMAPDSS_H
a0b38cc4 TV	19	#define __OMAP_OMAPDSS_H
559d6701 TV	20
	21	#include <linux/list.h>
	22	#include <linux/kobject.h>
	23	#include <linux/device.h>
b7ee79ab	24	#include <linux/platform_device.h>
559d6701 TV	25	#include <asm/atomic.h>
	26
	27	#define DISPC_IRQ_FRAMEDONE (1 << 0)
	28	#define DISPC_IRQ_VSYNC (1 << 1)
	29	#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
	30	#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
	31	#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
	32	#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
	33	#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
	34	#define DISPC_IRQ_GFX_END_WIN (1 << 7)
	35	#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
	36	#define DISPC_IRQ_OCP_ERR (1 << 9)
	37	#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
	38	#define DISPC_IRQ_VID1_END_WIN (1 << 11)
	39	#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
	40	#define DISPC_IRQ_VID2_END_WIN (1 << 13)
	41	#define DISPC_IRQ_SYNC_LOST (1 << 14)
	42	#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
	43	#define DISPC_IRQ_WAKEUP (1 << 16)
2a205f34 SS	44	#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
	45	#define DISPC_IRQ_VSYNC2 (1 << 18)
	46	#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
	47	#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
559d6701 TV	48
	49	struct omap_dss_device;
	50	struct omap_overlay_manager;
	51
	52	enum omap_display_type {
	53	OMAP_DISPLAY_TYPE_NONE = 0,
	54	OMAP_DISPLAY_TYPE_DPI = 1 << 0,
	55	OMAP_DISPLAY_TYPE_DBI = 1 << 1,
	56	OMAP_DISPLAY_TYPE_SDI = 1 << 2,
	57	OMAP_DISPLAY_TYPE_DSI = 1 << 3,
	58	OMAP_DISPLAY_TYPE_VENC = 1 << 4,
b119601d	59	OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
559d6701 TV	60	};
	61
	62	enum omap_plane {
	63	OMAP_DSS_GFX = 0,
	64	OMAP_DSS_VIDEO1 = 1,
	65	OMAP_DSS_VIDEO2 = 2
	66	};
	67
	68	enum omap_channel {
	69	OMAP_DSS_CHANNEL_LCD = 0,
	70	OMAP_DSS_CHANNEL_DIGIT = 1,
8613b000	71	OMAP_DSS_CHANNEL_LCD2 = 2,
559d6701 TV	72	};
	73
	74	enum omap_color_mode {
	75	OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
	76	OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
	77	OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
	78	OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
	79	OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
	80	OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
	81	OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
	82	OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
	83	OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
	84	OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
	85	OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
	86	OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
	87	OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
	88	OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
559d6701 TV	89	};
	90
	91	enum omap_lcd_display_type {
	92	OMAP_DSS_LCD_DISPLAY_STN,
	93	OMAP_DSS_LCD_DISPLAY_TFT,
	94	};
	95
	96	enum omap_dss_load_mode {
	97	OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
	98	OMAP_DSS_LOAD_CLUT_ONLY = 1,
	99	OMAP_DSS_LOAD_FRAME_ONLY = 2,
	100	OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
	101	};
	102
	103	enum omap_dss_trans_key_type {
	104	OMAP_DSS_COLOR_KEY_GFX_DST = 0,
	105	OMAP_DSS_COLOR_KEY_VID_SRC = 1,
	106	};
	107
	108	enum omap_rfbi_te_mode {
	109	OMAP_DSS_RFBI_TE_MODE_1 = 1,
	110	OMAP_DSS_RFBI_TE_MODE_2 = 2,
	111	};
	112
	113	enum omap_panel_config {
	114	OMAP_DSS_LCD_IVS = 1<<0,
	115	OMAP_DSS_LCD_IHS = 1<<1,
	116	OMAP_DSS_LCD_IPC = 1<<2,
	117	OMAP_DSS_LCD_IEO = 1<<3,
	118	OMAP_DSS_LCD_RF = 1<<4,
	119	OMAP_DSS_LCD_ONOFF = 1<<5,
	120
	121	OMAP_DSS_LCD_TFT = 1<<20,
	122	};
	123
	124	enum omap_dss_venc_type {
	125	OMAP_DSS_VENC_TYPE_COMPOSITE,
	126	OMAP_DSS_VENC_TYPE_SVIDEO,
	127	};
	128
	129	enum omap_display_caps {
	130	OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
	131	OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
	132	};
	133
	134	enum omap_dss_update_mode {
	135	OMAP_DSS_UPDATE_DISABLED = 0,
	136	OMAP_DSS_UPDATE_AUTO,
	137	OMAP_DSS_UPDATE_MANUAL,
	138	};
	139
	140	enum omap_dss_display_state {
	141	OMAP_DSS_DISPLAY_DISABLED = 0,
	142	OMAP_DSS_DISPLAY_ACTIVE,
	143	OMAP_DSS_DISPLAY_SUSPENDED,
	144	};
	145
	146	/* XXX perhaps this should be removed */
	147	enum omap_dss_overlay_managers {
	148	OMAP_DSS_OVL_MGR_LCD,
	149	OMAP_DSS_OVL_MGR_TV,
8613b000	150	OMAP_DSS_OVL_MGR_LCD2,
559d6701 TV	151	};
	152
	153	enum omap_dss_rotation_type {
	154	OMAP_DSS_ROT_DMA = 0,
	155	OMAP_DSS_ROT_VRFB = 1,
	156	};
	157
	158	/* clockwise rotation angle */
	159	enum omap_dss_rotation_angle {
	160	OMAP_DSS_ROT_0 = 0,
	161	OMAP_DSS_ROT_90 = 1,
	162	OMAP_DSS_ROT_180 = 2,
	163	OMAP_DSS_ROT_270 = 3,
	164	};
	165
	166	enum omap_overlay_caps {
	167	OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
	168	OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
	169	};
	170
	171	enum omap_overlay_manager_caps {
	172	OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
	173	};
	174
89a35e51 AT	175	enum omap_dss_clk_source {
	176	OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
	177	* OMAP4: DSS_FCLK */
	178	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
	179	* OMAP4: PLL1_CLK1 */
	180	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
	181	* OMAP4: PLL1_CLK2 */
	182	};
	183
559d6701 TV	184	/* RFBI */
	185
	186	struct rfbi_timings {
	187	int cs_on_time;
	188	int cs_off_time;
	189	int we_on_time;
	190	int we_off_time;
	191	int re_on_time;
	192	int re_off_time;
	193	int we_cycle_time;
	194	int re_cycle_time;
	195	int cs_pulse_width;
	196	int access_time;
	197
	198	int clk_div;
	199
	200	u32 tim[5]; /* set by rfbi_convert_timings() */
	201
	202	int converted;
	203	};
	204
	205	void omap_rfbi_write_command(const void *buf, u32 len);
	206	void omap_rfbi_read_data(void *buf, u32 len);
	207	void omap_rfbi_write_data(const void *buf, u32 len);
	208	void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
	209	u16 x, u16 y,
	210	u16 w, u16 h);
	211	int omap_rfbi_enable_te(bool enable, unsigned line);
	212	int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
	213	unsigned hs_pulse_time, unsigned vs_pulse_time,
	214	int hs_pol_inv, int vs_pol_inv, int extif_div);
	215
	216	/* DSI */
1ffefe75 AT	217	void dsi_bus_lock(struct omap_dss_device *dssdev);
	218	void dsi_bus_unlock(struct omap_dss_device *dssdev);
	219	int dsi_vc_dcs_write(struct omap_dss_device dssdev, int channel, u8 data,
	220	int len);
	221	int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel,
	222	u8 dcs_cmd);
	223	int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
	224	u8 param);
	225	int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
	226	u8 *data, int len);
	227	int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
	228	u8 *buf, int buflen);
	229	int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
	230	u8 *data);
	231	int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
	232	u8 data1, u8 data2);
	233	int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
	234	u16 len);
	235	int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
	236	int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
559d6701 TV	237
	238	/* Board specific data */
	239	struct omap_dss_board_info {
	240	int (get_last_off_on_transaction_id)(struct device dev);
	241	int num_devices;
	242	struct omap_dss_device **devices;
	243	struct omap_dss_device *default_device;
d1f5857e	244	void (*dsi_mux_pads)(bool enable);
559d6701 TV	245	};
559d6701 TV	246
b7ee79ab SS	247	#if defined(CONFIG_OMAP2_DSS_MODULE) \|\| defined(CONFIG_OMAP2_DSS)
	248	/* Init with the board info */
	249	extern int omap_display_init(struct omap_dss_board_info *board_data);
	250	#else
	251	static inline int omap_display_init(struct omap_dss_board_info *board_data)
	252	{
	253	return 0;
	254	}
	255	#endif
	256
cf07f531 SG	257	struct omap_display_platform_data {
	258	struct omap_dss_board_info *board_data;
	259	/* TODO: Additional members to be added when PM is considered */
fd4b34f6 SS	260
fd4b34f6 SS	261	bool (opt_clock_available)(const char clk_role);
cf07f531 SG	262	};
cf07f531 SG	263
559d6701 TV	264	struct omap_video_timings {
	265	/* Unit: pixels */
	266	u16 x_res;
	267	/* Unit: pixels */
	268	u16 y_res;
	269	/* Unit: KHz */
	270	u32 pixel_clock;
	271	/* Unit: pixel clocks */
	272	u16 hsw; /* Horizontal synchronization pulse width */
	273	/* Unit: pixel clocks */
	274	u16 hfp; /* Horizontal front porch */
	275	/* Unit: pixel clocks */
	276	u16 hbp; /* Horizontal back porch */
	277	/* Unit: line clocks */
	278	u16 vsw; /* Vertical synchronization pulse width */
	279	/* Unit: line clocks */
	280	u16 vfp; /* Vertical front porch */
	281	/* Unit: line clocks */
	282	u16 vbp; /* Vertical back porch */
	283	};
	284
	285	#ifdef CONFIG_OMAP2_DSS_VENC
	286	/* Hardcoded timings for tv modes. Venc only uses these to
	287	* identify the mode, and does not actually use the configs
	288	* itself. However, the configs should be something that
	289	* a normal monitor can also show */
5a1819e3 TK	290	extern const struct omap_video_timings omap_dss_pal_timings;
5a1819e3 TK	291	extern const struct omap_video_timings omap_dss_ntsc_timings;
559d6701 TV	292	#endif
	293
	294	struct omap_overlay_info {
	295	bool enabled;
	296
	297	u32 paddr;
	298	void __iomem *vaddr;
	299	u16 screen_width;
	300	u16 width;
	301	u16 height;
	302	enum omap_color_mode color_mode;
	303	u8 rotation;
	304	enum omap_dss_rotation_type rotation_type;
	305	bool mirror;
	306
	307	u16 pos_x;
	308	u16 pos_y;
	309	u16 out_width; /* if 0, out_width == width */
	310	u16 out_height; /* if 0, out_height == height */
	311	u8 global_alpha;
fd28a390	312	u8 pre_mult_alpha;
559d6701 TV	313	};
	314
	315	struct omap_overlay {
	316	struct kobject kobj;
	317	struct list_head list;
	318
	319	/* static fields */
	320	const char *name;
	321	int id;
	322	enum omap_color_mode supported_modes;
	323	enum omap_overlay_caps caps;
	324
	325	/* dynamic fields */
	326	struct omap_overlay_manager *manager;
	327	struct omap_overlay_info info;
	328
	329	/* if true, info has been changed, but not applied() yet */
	330	bool info_dirty;
	331
	332	int (set_manager)(struct omap_overlay ovl,
	333	struct omap_overlay_manager *mgr);
	334	int (unset_manager)(struct omap_overlay ovl);
	335
	336	int (set_overlay_info)(struct omap_overlay ovl,
	337	struct omap_overlay_info *info);
	338	void (get_overlay_info)(struct omap_overlay ovl,
	339	struct omap_overlay_info *info);
	340
	341	int (wait_for_go)(struct omap_overlay ovl);
	342	};
	343
	344	struct omap_overlay_manager_info {
	345	u32 default_color;
	346
	347	enum omap_dss_trans_key_type trans_key_type;
	348	u32 trans_key;
	349	bool trans_enabled;
	350
	351	bool alpha_enabled;
	352	};
	353
	354	struct omap_overlay_manager {
	355	struct kobject kobj;
	356	struct list_head list;
	357
	358	/* static fields */
	359	const char *name;
	360	int id;
	361	enum omap_overlay_manager_caps caps;
	362	int num_overlays;
	363	struct omap_overlay **overlays;
	364	enum omap_display_type supported_displays;
	365
	366	/* dynamic fields */
	367	struct omap_dss_device *device;
	368	struct omap_overlay_manager_info info;
	369
	370	bool device_changed;
	371	/* if true, info has been changed but not applied() yet */
	372	bool info_dirty;
	373
	374	int (set_device)(struct omap_overlay_manager mgr,
	375	struct omap_dss_device *dssdev);
	376	int (unset_device)(struct omap_overlay_manager mgr);
377
378	int (set_manager_info)(struct omap_overlay_manager mgr,
379	struct omap_overlay_manager_info *info);
380	void (get_manager_info)(struct omap_overlay_manager mgr,
381	struct omap_overlay_manager_info *info);
382
383	int (apply)(struct omap_overlay_manager mgr);
384	int (wait_for_go)(struct omap_overlay_manager mgr);
3f71cbe7	385	int (wait_for_vsync)(struct omap_overlay_manager mgr);
a2faee84 TV	386
	387	int (enable)(struct omap_overlay_manager mgr);
	388	int (disable)(struct omap_overlay_manager mgr);
559d6701 TV	389	};
	390
	391	struct omap_dss_device {
	392	struct device dev;
	393
	394	enum omap_display_type type;
	395
18faa1b6 SS	396	enum omap_channel channel;
18faa1b6 SS	397
559d6701 TV	398	union {
	399	struct {
	400	u8 data_lines;
	401	} dpi;
	402
	403	struct {
	404	u8 channel;
	405	u8 data_lines;
	406	} rfbi;
	407
	408	struct {
	409	u8 datapairs;
	410	} sdi;
	411
	412	struct {
	413	u8 clk_lane;
	414	u8 clk_pol;
	415	u8 data1_lane;
	416	u8 data1_pol;
	417	u8 data2_lane;
	418	u8 data2_pol;
	419
a72b64b9 AT	420	int module;
a72b64b9 AT	421
559d6701 TV	422	bool ext_te;
	423	u8 ext_te_gpio;
	424	} dsi;
	425
	426	struct {
	427	enum omap_dss_venc_type type;
	428	bool invert_polarity;
	429	} venc;
	430	} phy;
	431
c6940a3d TV	432	struct {
c6940a3d TV	433	struct {
e8881662 AT	434	struct {
	435	u16 lck_div;
	436	u16 pck_div;
	437	enum omap_dss_clk_source lcd_clk_src;
	438	} channel;
	439
	440	enum omap_dss_clk_source dispc_fclk_src;
c6940a3d TV	441	} dispc;
	442
	443	struct {
	444	u16 regn;
	445	u16 regm;
	446	u16 regm_dispc;
	447	u16 regm_dsi;
	448
	449	u16 lp_clk_div;
e8881662	450	enum omap_dss_clk_source dsi_fclk_src;
c6940a3d	451	} dsi;
6cb07b25 AT	452
	453	struct {
	454	u16 regn;
	455	u16 regm2;
	456	} hdmi;
c6940a3d TV	457	} clocks;
c6940a3d TV	458
559d6701 TV	459	struct {
	460	struct omap_video_timings timings;
	461
	462	int acbi; /* ac-bias pin transitions per interrupt */
	463	/* Unit: line clocks */
	464	int acb; /* ac-bias pin frequency */
	465
	466	enum omap_panel_config config;
559d6701 TV	467	} panel;
	468
	469	struct {
	470	u8 pixel_size;
	471	struct rfbi_timings rfbi_timings;
559d6701 TV	472	} ctrl;
	473
	474	int reset_gpio;
	475
	476	int max_backlight_level;
	477
	478	const char *name;
	479
	480	/* used to match device to driver */
	481	const char *driver_name;
	482
	483	void *data;
	484
	485	struct omap_dss_driver *driver;
	486
	487	/* helper variable for driver suspend/resume */
	488	bool activate_after_resume;
	489
	490	enum omap_display_caps caps;
	491
	492	struct omap_overlay_manager *manager;
	493
	494	enum omap_dss_display_state state;
	495
559d6701 TV	496	/* platform specific */
	497	int (platform_enable)(struct omap_dss_device dssdev);
	498	void (platform_disable)(struct omap_dss_device dssdev);
	499	int (set_backlight)(struct omap_dss_device dssdev, int level);
	500	int (get_backlight)(struct omap_dss_device dssdev);
	501	};
	502
	503	struct omap_dss_driver {
	504	struct device_driver driver;
	505
	506	int (probe)(struct omap_dss_device );
	507	void (remove)(struct omap_dss_device );
	508
	509	int (enable)(struct omap_dss_device display);
	510	void (disable)(struct omap_dss_device display);
	511	int (suspend)(struct omap_dss_device display);
	512	int (resume)(struct omap_dss_device display);
	513	int (run_test)(struct omap_dss_device display, int test);
	514
446f7bff TV	515	int (set_update_mode)(struct omap_dss_device dssdev,
	516	enum omap_dss_update_mode);
	517	enum omap_dss_update_mode (*get_update_mode)(
	518	struct omap_dss_device *dssdev);
559d6701	519
18946f62 TV	520	int (update)(struct omap_dss_device dssdev,
	521	u16 x, u16 y, u16 w, u16 h);
	522	int (sync)(struct omap_dss_device dssdev);
	523
559d6701	524	int (enable_te)(struct omap_dss_device dssdev, bool enable);
225b650d	525	int (get_te)(struct omap_dss_device dssdev);
559d6701 TV	526
	527	u8 (get_rotate)(struct omap_dss_device dssdev);
	528	int (set_rotate)(struct omap_dss_device dssdev, u8 rotate);
	529
	530	bool (get_mirror)(struct omap_dss_device dssdev);
	531	int (set_mirror)(struct omap_dss_device dssdev, bool enable);
	532
	533	int (memory_read)(struct omap_dss_device dssdev,
	534	void *buf, size_t size,
	535	u16 x, u16 y, u16 w, u16 h);
96adcece TV	536
	537	void (get_resolution)(struct omap_dss_device dssdev,
	538	u16 xres, u16 yres);
7a0987bf JN	539	void (get_dimensions)(struct omap_dss_device dssdev,
7a0987bf JN	540	u32 width, u32 height);
a2699504	541	int (get_recommended_bpp)(struct omap_dss_device dssdev);
36511312	542
69b2048f TV	543	int (check_timings)(struct omap_dss_device dssdev,
	544	struct omap_video_timings *timings);
	545	void (set_timings)(struct omap_dss_device dssdev,
	546	struct omap_video_timings *timings);
	547	void (get_timings)(struct omap_dss_device dssdev,
	548	struct omap_video_timings *timings);
	549
36511312 TV	550	int (set_wss)(struct omap_dss_device dssdev, u32 wss);
36511312 TV	551	u32 (get_wss)(struct omap_dss_device dssdev);
559d6701 TV	552	};
	553
	554	int omap_dss_register_driver(struct omap_dss_driver *);
	555	void omap_dss_unregister_driver(struct omap_dss_driver *);
	556
559d6701 TV	557	void omap_dss_get_device(struct omap_dss_device *dssdev);
	558	void omap_dss_put_device(struct omap_dss_device *dssdev);
	559	#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
	560	struct omap_dss_device omap_dss_get_next_device(struct omap_dss_device from);
	561	struct omap_dss_device omap_dss_find_device(void data,
	562	int (match)(struct omap_dss_device dssdev, void *data));
	563
	564	int omap_dss_start_device(struct omap_dss_device *dssdev);
	565	void omap_dss_stop_device(struct omap_dss_device *dssdev);
	566
	567	int omap_dss_get_num_overlay_managers(void);
	568	struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
	569
	570	int omap_dss_get_num_overlays(void);
	571	struct omap_overlay *omap_dss_get_overlay(int num);
	572
96adcece TV	573	void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
96adcece TV	574	u16 xres, u16 yres);
a2699504 TV	575	int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
a2699504 TV	576
559d6701 TV	577	typedef void (omap_dispc_isr_t) (void arg, u32 mask);
	578	int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
	579	int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
	580
	581	int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
	582	int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
	583	unsigned long timeout);
	584
	585	#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
	586	#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
	587
1ffefe75 AT	588	void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
1ffefe75 AT	589	bool enable);
225b650d	590	int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
61140c9a	591
18946f62	592	int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
26a8c250 TV	593	u16 x, u16 y, u16 w, u16 h,
26a8c250 TV	594	bool enlarge_update_area);
18946f62 TV	595	int omap_dsi_update(struct omap_dss_device *dssdev,
	596	int channel,
	597	u16 x, u16 y, u16 w, u16 h,
	598	void (callback)(int, void ), void *data);
5ee3c144 AT	599	int omap_dsi_request_vc(struct omap_dss_device dssdev, int channel);
	600	int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
	601	void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
18946f62	602
37ac60e4	603	int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
2a89dc15	604	void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
22d6d676	605	bool disconnect_lanes, bool enter_ulps);
37ac60e4 TV	606
	607	int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
	608	void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
69b2048f TV	609	void dpi_set_timings(struct omap_dss_device *dssdev,
	610	struct omap_video_timings *timings);
	611	int dpi_check_timings(struct omap_dss_device *dssdev,
	612	struct omap_video_timings *timings);
37ac60e4 TV	613
	614	int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
	615	void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
	616
	617	int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
	618	void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
18946f62 TV	619	int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
	620	u16 x, u16 y, u16 w, u16 h);
	621	int omap_rfbi_update(struct omap_dss_device *dssdev,
	622	u16 x, u16 y, u16 w, u16 h,
	623	void (callback)(void ), void *data);
	624
559d6701	625	#endif