Commit | Line | Data |
---|---|---|
559d6701 | 1 | /* |
559d6701 TV |
2 | * Copyright (C) 2008 Nokia Corporation |
3 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
a0b38cc4 TV |
18 | #ifndef __OMAP_OMAPDSS_H |
19 | #define __OMAP_OMAPDSS_H | |
559d6701 TV |
20 | |
21 | #include <linux/list.h> | |
22 | #include <linux/kobject.h> | |
23 | #include <linux/device.h> | |
348be69d | 24 | #include <linux/interrupt.h> |
559d6701 | 25 | |
6fcd485b TV |
26 | #include <video/videomode.h> |
27 | ||
559d6701 TV |
28 | #define DISPC_IRQ_FRAMEDONE (1 << 0) |
29 | #define DISPC_IRQ_VSYNC (1 << 1) | |
30 | #define DISPC_IRQ_EVSYNC_EVEN (1 << 2) | |
31 | #define DISPC_IRQ_EVSYNC_ODD (1 << 3) | |
32 | #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4) | |
33 | #define DISPC_IRQ_PROG_LINE_NUM (1 << 5) | |
34 | #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6) | |
35 | #define DISPC_IRQ_GFX_END_WIN (1 << 7) | |
36 | #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8) | |
37 | #define DISPC_IRQ_OCP_ERR (1 << 9) | |
38 | #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10) | |
39 | #define DISPC_IRQ_VID1_END_WIN (1 << 11) | |
40 | #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12) | |
41 | #define DISPC_IRQ_VID2_END_WIN (1 << 13) | |
42 | #define DISPC_IRQ_SYNC_LOST (1 << 14) | |
43 | #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15) | |
44 | #define DISPC_IRQ_WAKEUP (1 << 16) | |
2a205f34 SS |
45 | #define DISPC_IRQ_SYNC_LOST2 (1 << 17) |
46 | #define DISPC_IRQ_VSYNC2 (1 << 18) | |
b8c095b4 AT |
47 | #define DISPC_IRQ_VID3_END_WIN (1 << 19) |
48 | #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20) | |
2a205f34 SS |
49 | #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21) |
50 | #define DISPC_IRQ_FRAMEDONE2 (1 << 22) | |
7f6f3c4b TV |
51 | #define DISPC_IRQ_FRAMEDONEWB (1 << 23) |
52 | #define DISPC_IRQ_FRAMEDONETV (1 << 24) | |
53 | #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25) | |
14d33d38 CM |
54 | #define DISPC_IRQ_SYNC_LOST3 (1 << 27) |
55 | #define DISPC_IRQ_VSYNC3 (1 << 28) | |
56 | #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29) | |
57 | #define DISPC_IRQ_FRAMEDONE3 (1 << 30) | |
559d6701 TV |
58 | |
59 | struct omap_dss_device; | |
60 | struct omap_overlay_manager; | |
a97a9634 | 61 | struct dss_lcd_mgr_config; |
9c0b8420 RN |
62 | struct snd_aes_iec958; |
63 | struct snd_cea_861_aud_if; | |
8c071caa | 64 | struct hdmi_avi_infoframe; |
559d6701 TV |
65 | |
66 | enum omap_display_type { | |
67 | OMAP_DISPLAY_TYPE_NONE = 0, | |
68 | OMAP_DISPLAY_TYPE_DPI = 1 << 0, | |
69 | OMAP_DISPLAY_TYPE_DBI = 1 << 1, | |
70 | OMAP_DISPLAY_TYPE_SDI = 1 << 2, | |
71 | OMAP_DISPLAY_TYPE_DSI = 1 << 3, | |
72 | OMAP_DISPLAY_TYPE_VENC = 1 << 4, | |
b119601d | 73 | OMAP_DISPLAY_TYPE_HDMI = 1 << 5, |
bc24b8b6 | 74 | OMAP_DISPLAY_TYPE_DVI = 1 << 6, |
559d6701 TV |
75 | }; |
76 | ||
77 | enum omap_plane { | |
78 | OMAP_DSS_GFX = 0, | |
79 | OMAP_DSS_VIDEO1 = 1, | |
b8c095b4 AT |
80 | OMAP_DSS_VIDEO2 = 2, |
81 | OMAP_DSS_VIDEO3 = 3, | |
66a0f9e4 | 82 | OMAP_DSS_WB = 4, |
559d6701 TV |
83 | }; |
84 | ||
85 | enum omap_channel { | |
86 | OMAP_DSS_CHANNEL_LCD = 0, | |
87 | OMAP_DSS_CHANNEL_DIGIT = 1, | |
8613b000 | 88 | OMAP_DSS_CHANNEL_LCD2 = 2, |
ff6331e2 | 89 | OMAP_DSS_CHANNEL_LCD3 = 3, |
559d6701 TV |
90 | }; |
91 | ||
92 | enum omap_color_mode { | |
93 | OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */ | |
94 | OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */ | |
95 | OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */ | |
96 | OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */ | |
97 | OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */ | |
98 | OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */ | |
99 | OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */ | |
100 | OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */ | |
101 | OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */ | |
102 | OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */ | |
103 | OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */ | |
104 | OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */ | |
105 | OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */ | |
106 | OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */ | |
f20e4220 AJ |
107 | OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */ |
108 | OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */ | |
109 | OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */ | |
110 | OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */ | |
111 | OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */ | |
559d6701 TV |
112 | }; |
113 | ||
559d6701 TV |
114 | enum omap_dss_load_mode { |
115 | OMAP_DSS_LOAD_CLUT_AND_FRAME = 0, | |
116 | OMAP_DSS_LOAD_CLUT_ONLY = 1, | |
117 | OMAP_DSS_LOAD_FRAME_ONLY = 2, | |
118 | OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3, | |
119 | }; | |
120 | ||
121 | enum omap_dss_trans_key_type { | |
122 | OMAP_DSS_COLOR_KEY_GFX_DST = 0, | |
123 | OMAP_DSS_COLOR_KEY_VID_SRC = 1, | |
124 | }; | |
125 | ||
126 | enum omap_rfbi_te_mode { | |
127 | OMAP_DSS_RFBI_TE_MODE_1 = 1, | |
128 | OMAP_DSS_RFBI_TE_MODE_2 = 2, | |
129 | }; | |
130 | ||
a8d5e41c AT |
131 | enum omap_dss_signal_level { |
132 | OMAPDSS_SIG_ACTIVE_HIGH = 0, | |
133 | OMAPDSS_SIG_ACTIVE_LOW = 1, | |
134 | }; | |
135 | ||
136 | enum omap_dss_signal_edge { | |
137 | OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES, | |
138 | OMAPDSS_DRIVE_SIG_RISING_EDGE, | |
139 | OMAPDSS_DRIVE_SIG_FALLING_EDGE, | |
140 | }; | |
141 | ||
559d6701 TV |
142 | enum omap_dss_venc_type { |
143 | OMAP_DSS_VENC_TYPE_COMPOSITE, | |
144 | OMAP_DSS_VENC_TYPE_SVIDEO, | |
145 | }; | |
146 | ||
a3b3cc2b AT |
147 | enum omap_dss_dsi_pixel_format { |
148 | OMAP_DSS_DSI_FMT_RGB888, | |
149 | OMAP_DSS_DSI_FMT_RGB666, | |
150 | OMAP_DSS_DSI_FMT_RGB666_PACKED, | |
151 | OMAP_DSS_DSI_FMT_RGB565, | |
152 | }; | |
153 | ||
7e951ee9 AT |
154 | enum omap_dss_dsi_mode { |
155 | OMAP_DSS_DSI_CMD_MODE = 0, | |
156 | OMAP_DSS_DSI_VIDEO_MODE, | |
157 | }; | |
158 | ||
559d6701 TV |
159 | enum omap_display_caps { |
160 | OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0, | |
161 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1, | |
162 | }; | |
163 | ||
559d6701 TV |
164 | enum omap_dss_display_state { |
165 | OMAP_DSS_DISPLAY_DISABLED = 0, | |
166 | OMAP_DSS_DISPLAY_ACTIVE, | |
559d6701 TV |
167 | }; |
168 | ||
0b450c31 TV |
169 | struct omap_dss_audio { |
170 | struct snd_aes_iec958 *iec; | |
171 | struct snd_cea_861_aud_if *cea; | |
172 | }; | |
173 | ||
559d6701 | 174 | enum omap_dss_rotation_type { |
65e006ff CM |
175 | OMAP_DSS_ROT_DMA = 1 << 0, |
176 | OMAP_DSS_ROT_VRFB = 1 << 1, | |
177 | OMAP_DSS_ROT_TILER = 1 << 2, | |
559d6701 TV |
178 | }; |
179 | ||
180 | /* clockwise rotation angle */ | |
181 | enum omap_dss_rotation_angle { | |
182 | OMAP_DSS_ROT_0 = 0, | |
183 | OMAP_DSS_ROT_90 = 1, | |
184 | OMAP_DSS_ROT_180 = 2, | |
185 | OMAP_DSS_ROT_270 = 3, | |
186 | }; | |
187 | ||
188 | enum omap_overlay_caps { | |
189 | OMAP_DSS_OVL_CAP_SCALE = 1 << 0, | |
f6dc8150 TV |
190 | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1, |
191 | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2, | |
11354dd5 | 192 | OMAP_DSS_OVL_CAP_ZORDER = 1 << 3, |
d79db853 AT |
193 | OMAP_DSS_OVL_CAP_POS = 1 << 4, |
194 | OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5, | |
559d6701 TV |
195 | }; |
196 | ||
197 | enum omap_overlay_manager_caps { | |
4a9e78ab | 198 | OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */ |
559d6701 TV |
199 | }; |
200 | ||
89a35e51 AT |
201 | enum omap_dss_clk_source { |
202 | OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK | |
203 | * OMAP4: DSS_FCLK */ | |
204 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK | |
205 | * OMAP4: PLL1_CLK1 */ | |
206 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK | |
207 | * OMAP4: PLL1_CLK2 */ | |
5a8b572d AT |
208 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */ |
209 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */ | |
89a35e51 AT |
210 | }; |
211 | ||
9a901683 M |
212 | enum omap_hdmi_flags { |
213 | OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0, | |
214 | }; | |
215 | ||
484dc404 AT |
216 | enum omap_dss_output_id { |
217 | OMAP_DSS_OUTPUT_DPI = 1 << 0, | |
218 | OMAP_DSS_OUTPUT_DBI = 1 << 1, | |
219 | OMAP_DSS_OUTPUT_SDI = 1 << 2, | |
220 | OMAP_DSS_OUTPUT_DSI1 = 1 << 3, | |
221 | OMAP_DSS_OUTPUT_DSI2 = 1 << 4, | |
222 | OMAP_DSS_OUTPUT_VENC = 1 << 5, | |
223 | OMAP_DSS_OUTPUT_HDMI = 1 << 6, | |
224 | }; | |
225 | ||
559d6701 TV |
226 | /* RFBI */ |
227 | ||
228 | struct rfbi_timings { | |
229 | int cs_on_time; | |
230 | int cs_off_time; | |
231 | int we_on_time; | |
232 | int we_off_time; | |
233 | int re_on_time; | |
234 | int re_off_time; | |
235 | int we_cycle_time; | |
236 | int re_cycle_time; | |
237 | int cs_pulse_width; | |
238 | int access_time; | |
239 | ||
240 | int clk_div; | |
241 | ||
242 | u32 tim[5]; /* set by rfbi_convert_timings() */ | |
243 | ||
244 | int converted; | |
245 | }; | |
246 | ||
559d6701 | 247 | /* DSI */ |
8af6ff01 | 248 | |
478d7df8 TV |
249 | enum omap_dss_dsi_trans_mode { |
250 | /* Sync Pulses: both sync start and end packets sent */ | |
251 | OMAP_DSS_DSI_PULSE_MODE, | |
252 | /* Sync Events: only sync start packets sent */ | |
253 | OMAP_DSS_DSI_EVENT_MODE, | |
254 | /* Burst: only sync start packets sent, pixels are time compressed */ | |
255 | OMAP_DSS_DSI_BURST_MODE, | |
256 | }; | |
257 | ||
6b849375 | 258 | struct omap_dss_dsi_videomode_timings { |
f1e0001f TV |
259 | unsigned long hsclk; |
260 | ||
261 | unsigned ndl; | |
262 | unsigned bitspp; | |
263 | ||
264 | /* pixels */ | |
265 | u16 hact; | |
266 | /* lines */ | |
267 | u16 vact; | |
268 | ||
8af6ff01 AT |
269 | /* DSI video mode blanking data */ |
270 | /* Unit: byte clock cycles */ | |
f1e0001f | 271 | u16 hss; |
8af6ff01 | 272 | u16 hsa; |
f1e0001f | 273 | u16 hse; |
8af6ff01 AT |
274 | u16 hfp; |
275 | u16 hbp; | |
276 | /* Unit: line clocks */ | |
277 | u16 vsa; | |
278 | u16 vfp; | |
279 | u16 vbp; | |
280 | ||
281 | /* DSI blanking modes */ | |
282 | int blanking_mode; | |
283 | int hsa_blanking_mode; | |
284 | int hbp_blanking_mode; | |
285 | int hfp_blanking_mode; | |
286 | ||
478d7df8 | 287 | enum omap_dss_dsi_trans_mode trans_mode; |
8af6ff01 AT |
288 | |
289 | bool ddr_clk_always_on; | |
290 | int window_sync; | |
291 | }; | |
292 | ||
777f05cc TV |
293 | struct omap_dss_dsi_config { |
294 | enum omap_dss_dsi_mode mode; | |
295 | enum omap_dss_dsi_pixel_format pixel_format; | |
296 | const struct omap_video_timings *timings; | |
777f05cc | 297 | |
f1e0001f TV |
298 | unsigned long hs_clk_min, hs_clk_max; |
299 | unsigned long lp_clk_min, lp_clk_max; | |
300 | ||
301 | bool ddr_clk_always_on; | |
302 | enum omap_dss_dsi_trans_mode trans_mode; | |
777f05cc TV |
303 | }; |
304 | ||
acd18af9 TV |
305 | enum omapdss_version { |
306 | OMAPDSS_VER_UNKNOWN = 0, | |
307 | OMAPDSS_VER_OMAP24xx, | |
308 | OMAPDSS_VER_OMAP34xx_ES1, /* OMAP3430 ES1.0, 2.0 */ | |
309 | OMAPDSS_VER_OMAP34xx_ES3, /* OMAP3430 ES3.0+ */ | |
310 | OMAPDSS_VER_OMAP3630, | |
311 | OMAPDSS_VER_AM35xx, | |
312 | OMAPDSS_VER_OMAP4430_ES1, /* OMAP4430 ES1.0 */ | |
313 | OMAPDSS_VER_OMAP4430_ES2, /* OMAP4430 ES2.0, 2.1, 2.2 */ | |
314 | OMAPDSS_VER_OMAP4, /* All other OMAP4s */ | |
315 | OMAPDSS_VER_OMAP5, | |
d6279d4a | 316 | OMAPDSS_VER_AM43xx, |
472da57b | 317 | OMAPDSS_VER_DRA7xx, |
acd18af9 TV |
318 | }; |
319 | ||
559d6701 TV |
320 | /* Board specific data */ |
321 | struct omap_dss_board_info { | |
559d6701 TV |
322 | int num_devices; |
323 | struct omap_dss_device **devices; | |
324 | struct omap_dss_device *default_device; | |
0a200126 | 325 | const char *default_display_name; |
5bc416cb TV |
326 | int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask); |
327 | void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask); | |
62c1dcfc | 328 | int (*set_min_bus_tput)(struct device *dev, unsigned long r); |
acd18af9 | 329 | enum omapdss_version version; |
559d6701 TV |
330 | }; |
331 | ||
b7ee79ab SS |
332 | /* Init with the board info */ |
333 | extern int omap_display_init(struct omap_dss_board_info *board_data); | |
ee9dfd82 | 334 | /* HDMI mux init*/ |
9a901683 | 335 | extern int omap_hdmi_init(enum omap_hdmi_flags flags); |
b7ee79ab | 336 | |
559d6701 TV |
337 | struct omap_video_timings { |
338 | /* Unit: pixels */ | |
339 | u16 x_res; | |
340 | /* Unit: pixels */ | |
341 | u16 y_res; | |
d8d78941 TV |
342 | /* Unit: Hz */ |
343 | u32 pixelclock; | |
559d6701 TV |
344 | /* Unit: pixel clocks */ |
345 | u16 hsw; /* Horizontal synchronization pulse width */ | |
346 | /* Unit: pixel clocks */ | |
347 | u16 hfp; /* Horizontal front porch */ | |
348 | /* Unit: pixel clocks */ | |
349 | u16 hbp; /* Horizontal back porch */ | |
350 | /* Unit: line clocks */ | |
351 | u16 vsw; /* Vertical synchronization pulse width */ | |
352 | /* Unit: line clocks */ | |
353 | u16 vfp; /* Vertical front porch */ | |
354 | /* Unit: line clocks */ | |
355 | u16 vbp; /* Vertical back porch */ | |
a8d5e41c AT |
356 | |
357 | /* Vsync logic level */ | |
358 | enum omap_dss_signal_level vsync_level; | |
359 | /* Hsync logic level */ | |
360 | enum omap_dss_signal_level hsync_level; | |
23c8f88e AT |
361 | /* Interlaced or Progressive timings */ |
362 | bool interlace; | |
a8d5e41c AT |
363 | /* Pixel clock edge to drive LCD data */ |
364 | enum omap_dss_signal_edge data_pclk_edge; | |
365 | /* Data enable logic level */ | |
366 | enum omap_dss_signal_level de_level; | |
367 | /* Pixel clock edges to drive HSYNC and VSYNC signals */ | |
368 | enum omap_dss_signal_edge sync_pclk_edge; | |
559d6701 TV |
369 | }; |
370 | ||
371 | #ifdef CONFIG_OMAP2_DSS_VENC | |
372 | /* Hardcoded timings for tv modes. Venc only uses these to | |
373 | * identify the mode, and does not actually use the configs | |
374 | * itself. However, the configs should be something that | |
375 | * a normal monitor can also show */ | |
5a1819e3 TK |
376 | extern const struct omap_video_timings omap_dss_pal_timings; |
377 | extern const struct omap_video_timings omap_dss_ntsc_timings; | |
559d6701 TV |
378 | #endif |
379 | ||
3c07cae2 TV |
380 | struct omap_dss_cpr_coefs { |
381 | s16 rr, rg, rb; | |
382 | s16 gr, gg, gb; | |
383 | s16 br, bg, bb; | |
384 | }; | |
385 | ||
559d6701 | 386 | struct omap_overlay_info { |
24f13a66 AB |
387 | dma_addr_t paddr; |
388 | dma_addr_t p_uv_addr; /* for NV12 format */ | |
559d6701 TV |
389 | u16 screen_width; |
390 | u16 width; | |
391 | u16 height; | |
392 | enum omap_color_mode color_mode; | |
393 | u8 rotation; | |
394 | enum omap_dss_rotation_type rotation_type; | |
395 | bool mirror; | |
396 | ||
397 | u16 pos_x; | |
398 | u16 pos_y; | |
399 | u16 out_width; /* if 0, out_width == width */ | |
400 | u16 out_height; /* if 0, out_height == height */ | |
401 | u8 global_alpha; | |
fd28a390 | 402 | u8 pre_mult_alpha; |
54128701 | 403 | u8 zorder; |
559d6701 TV |
404 | }; |
405 | ||
406 | struct omap_overlay { | |
407 | struct kobject kobj; | |
408 | struct list_head list; | |
409 | ||
410 | /* static fields */ | |
411 | const char *name; | |
4a9e78ab | 412 | enum omap_plane id; |
559d6701 TV |
413 | enum omap_color_mode supported_modes; |
414 | enum omap_overlay_caps caps; | |
415 | ||
416 | /* dynamic fields */ | |
417 | struct omap_overlay_manager *manager; | |
559d6701 | 418 | |
9d11c321 TV |
419 | /* |
420 | * The following functions do not block: | |
421 | * | |
422 | * is_enabled | |
423 | * set_overlay_info | |
424 | * get_overlay_info | |
425 | * | |
426 | * The rest of the functions may block and cannot be called from | |
427 | * interrupt context | |
428 | */ | |
429 | ||
aaa874a9 TV |
430 | int (*enable)(struct omap_overlay *ovl); |
431 | int (*disable)(struct omap_overlay *ovl); | |
432 | bool (*is_enabled)(struct omap_overlay *ovl); | |
433 | ||
559d6701 TV |
434 | int (*set_manager)(struct omap_overlay *ovl, |
435 | struct omap_overlay_manager *mgr); | |
436 | int (*unset_manager)(struct omap_overlay *ovl); | |
437 | ||
438 | int (*set_overlay_info)(struct omap_overlay *ovl, | |
439 | struct omap_overlay_info *info); | |
440 | void (*get_overlay_info)(struct omap_overlay *ovl, | |
441 | struct omap_overlay_info *info); | |
442 | ||
443 | int (*wait_for_go)(struct omap_overlay *ovl); | |
794bc4ee AT |
444 | |
445 | struct omap_dss_device *(*get_device)(struct omap_overlay *ovl); | |
559d6701 TV |
446 | }; |
447 | ||
448 | struct omap_overlay_manager_info { | |
449 | u32 default_color; | |
450 | ||
451 | enum omap_dss_trans_key_type trans_key_type; | |
452 | u32 trans_key; | |
453 | bool trans_enabled; | |
454 | ||
11354dd5 | 455 | bool partial_alpha_enabled; |
3c07cae2 TV |
456 | |
457 | bool cpr_enable; | |
458 | struct omap_dss_cpr_coefs cpr_coefs; | |
559d6701 TV |
459 | }; |
460 | ||
461 | struct omap_overlay_manager { | |
462 | struct kobject kobj; | |
559d6701 TV |
463 | |
464 | /* static fields */ | |
465 | const char *name; | |
4a9e78ab | 466 | enum omap_channel id; |
559d6701 | 467 | enum omap_overlay_manager_caps caps; |
07e327c9 | 468 | struct list_head overlays; |
559d6701 | 469 | enum omap_display_type supported_displays; |
97f01b3a | 470 | enum omap_dss_output_id supported_outputs; |
559d6701 TV |
471 | |
472 | /* dynamic fields */ | |
1f68d9c4 | 473 | struct omap_dss_device *output; |
559d6701 | 474 | |
9d11c321 TV |
475 | /* |
476 | * The following functions do not block: | |
477 | * | |
478 | * set_manager_info | |
479 | * get_manager_info | |
480 | * apply | |
481 | * | |
482 | * The rest of the functions may block and cannot be called from | |
483 | * interrupt context | |
484 | */ | |
485 | ||
97f01b3a | 486 | int (*set_output)(struct omap_overlay_manager *mgr, |
1f68d9c4 | 487 | struct omap_dss_device *output); |
97f01b3a | 488 | int (*unset_output)(struct omap_overlay_manager *mgr); |
559d6701 TV |
489 | |
490 | int (*set_manager_info)(struct omap_overlay_manager *mgr, | |
491 | struct omap_overlay_manager_info *info); | |
492 | void (*get_manager_info)(struct omap_overlay_manager *mgr, | |
493 | struct omap_overlay_manager_info *info); | |
494 | ||
495 | int (*apply)(struct omap_overlay_manager *mgr); | |
496 | int (*wait_for_go)(struct omap_overlay_manager *mgr); | |
3f71cbe7 | 497 | int (*wait_for_vsync)(struct omap_overlay_manager *mgr); |
794bc4ee AT |
498 | |
499 | struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr); | |
559d6701 TV |
500 | }; |
501 | ||
e4a9e94c TV |
502 | /* 22 pins means 1 clk lane and 10 data lanes */ |
503 | #define OMAP_DSS_MAX_DSI_PINS 22 | |
504 | ||
505 | struct omap_dsi_pin_config { | |
506 | int num_pins; | |
507 | /* | |
508 | * pin numbers in the following order: | |
509 | * clk+, clk- | |
510 | * data1+, data1- | |
511 | * data2+, data2- | |
512 | * ... | |
513 | */ | |
514 | int pins[OMAP_DSS_MAX_DSI_PINS]; | |
515 | }; | |
516 | ||
749feffa AT |
517 | struct omap_dss_writeback_info { |
518 | u32 paddr; | |
519 | u32 p_uv_addr; | |
520 | u16 buf_width; | |
521 | u16 width; | |
522 | u16 height; | |
523 | enum omap_color_mode color_mode; | |
524 | u8 rotation; | |
525 | enum omap_dss_rotation_type rotation_type; | |
526 | bool mirror; | |
527 | u8 pre_mult_alpha; | |
528 | }; | |
529 | ||
0b24edb1 TV |
530 | struct omapdss_dpi_ops { |
531 | int (*connect)(struct omap_dss_device *dssdev, | |
532 | struct omap_dss_device *dst); | |
533 | void (*disconnect)(struct omap_dss_device *dssdev, | |
534 | struct omap_dss_device *dst); | |
535 | ||
536 | int (*enable)(struct omap_dss_device *dssdev); | |
537 | void (*disable)(struct omap_dss_device *dssdev); | |
538 | ||
539 | int (*check_timings)(struct omap_dss_device *dssdev, | |
540 | struct omap_video_timings *timings); | |
541 | void (*set_timings)(struct omap_dss_device *dssdev, | |
542 | struct omap_video_timings *timings); | |
543 | void (*get_timings)(struct omap_dss_device *dssdev, | |
544 | struct omap_video_timings *timings); | |
545 | ||
546 | void (*set_data_lines)(struct omap_dss_device *dssdev, int data_lines); | |
547 | }; | |
548 | ||
b1082dfd TV |
549 | struct omapdss_sdi_ops { |
550 | int (*connect)(struct omap_dss_device *dssdev, | |
551 | struct omap_dss_device *dst); | |
552 | void (*disconnect)(struct omap_dss_device *dssdev, | |
553 | struct omap_dss_device *dst); | |
554 | ||
555 | int (*enable)(struct omap_dss_device *dssdev); | |
556 | void (*disable)(struct omap_dss_device *dssdev); | |
557 | ||
558 | int (*check_timings)(struct omap_dss_device *dssdev, | |
559 | struct omap_video_timings *timings); | |
560 | void (*set_timings)(struct omap_dss_device *dssdev, | |
561 | struct omap_video_timings *timings); | |
562 | void (*get_timings)(struct omap_dss_device *dssdev, | |
563 | struct omap_video_timings *timings); | |
564 | ||
565 | void (*set_datapairs)(struct omap_dss_device *dssdev, int datapairs); | |
566 | }; | |
567 | ||
7700c2d4 TV |
568 | struct omapdss_dvi_ops { |
569 | int (*connect)(struct omap_dss_device *dssdev, | |
570 | struct omap_dss_device *dst); | |
571 | void (*disconnect)(struct omap_dss_device *dssdev, | |
572 | struct omap_dss_device *dst); | |
573 | ||
574 | int (*enable)(struct omap_dss_device *dssdev); | |
575 | void (*disable)(struct omap_dss_device *dssdev); | |
576 | ||
577 | int (*check_timings)(struct omap_dss_device *dssdev, | |
578 | struct omap_video_timings *timings); | |
579 | void (*set_timings)(struct omap_dss_device *dssdev, | |
580 | struct omap_video_timings *timings); | |
581 | void (*get_timings)(struct omap_dss_device *dssdev, | |
582 | struct omap_video_timings *timings); | |
583 | }; | |
584 | ||
fb8efa49 TV |
585 | struct omapdss_atv_ops { |
586 | int (*connect)(struct omap_dss_device *dssdev, | |
587 | struct omap_dss_device *dst); | |
588 | void (*disconnect)(struct omap_dss_device *dssdev, | |
589 | struct omap_dss_device *dst); | |
590 | ||
591 | int (*enable)(struct omap_dss_device *dssdev); | |
592 | void (*disable)(struct omap_dss_device *dssdev); | |
593 | ||
594 | int (*check_timings)(struct omap_dss_device *dssdev, | |
595 | struct omap_video_timings *timings); | |
596 | void (*set_timings)(struct omap_dss_device *dssdev, | |
597 | struct omap_video_timings *timings); | |
598 | void (*get_timings)(struct omap_dss_device *dssdev, | |
599 | struct omap_video_timings *timings); | |
600 | ||
601 | void (*set_type)(struct omap_dss_device *dssdev, | |
602 | enum omap_dss_venc_type type); | |
603 | void (*invert_vid_out_polarity)(struct omap_dss_device *dssdev, | |
604 | bool invert_polarity); | |
605 | ||
606 | int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); | |
607 | u32 (*get_wss)(struct omap_dss_device *dssdev); | |
608 | }; | |
609 | ||
0b450c31 TV |
610 | struct omapdss_hdmi_ops { |
611 | int (*connect)(struct omap_dss_device *dssdev, | |
612 | struct omap_dss_device *dst); | |
613 | void (*disconnect)(struct omap_dss_device *dssdev, | |
614 | struct omap_dss_device *dst); | |
615 | ||
616 | int (*enable)(struct omap_dss_device *dssdev); | |
617 | void (*disable)(struct omap_dss_device *dssdev); | |
618 | ||
619 | int (*check_timings)(struct omap_dss_device *dssdev, | |
620 | struct omap_video_timings *timings); | |
621 | void (*set_timings)(struct omap_dss_device *dssdev, | |
622 | struct omap_video_timings *timings); | |
623 | void (*get_timings)(struct omap_dss_device *dssdev, | |
624 | struct omap_video_timings *timings); | |
625 | ||
626 | int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); | |
627 | bool (*detect)(struct omap_dss_device *dssdev); | |
628 | ||
8c071caa TV |
629 | int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode); |
630 | int (*set_infoframe)(struct omap_dss_device *dssdev, | |
631 | const struct hdmi_avi_infoframe *avi); | |
0b450c31 TV |
632 | }; |
633 | ||
deb16df8 TV |
634 | struct omapdss_dsi_ops { |
635 | int (*connect)(struct omap_dss_device *dssdev, | |
636 | struct omap_dss_device *dst); | |
637 | void (*disconnect)(struct omap_dss_device *dssdev, | |
638 | struct omap_dss_device *dst); | |
639 | ||
640 | int (*enable)(struct omap_dss_device *dssdev); | |
641 | void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes, | |
642 | bool enter_ulps); | |
643 | ||
644 | /* bus configuration */ | |
645 | int (*set_config)(struct omap_dss_device *dssdev, | |
646 | const struct omap_dss_dsi_config *cfg); | |
647 | int (*configure_pins)(struct omap_dss_device *dssdev, | |
648 | const struct omap_dsi_pin_config *pin_cfg); | |
649 | ||
650 | void (*enable_hs)(struct omap_dss_device *dssdev, int channel, | |
651 | bool enable); | |
652 | int (*enable_te)(struct omap_dss_device *dssdev, bool enable); | |
653 | ||
654 | int (*update)(struct omap_dss_device *dssdev, int channel, | |
655 | void (*callback)(int, void *), void *data); | |
656 | ||
657 | void (*bus_lock)(struct omap_dss_device *dssdev); | |
658 | void (*bus_unlock)(struct omap_dss_device *dssdev); | |
659 | ||
660 | int (*enable_video_output)(struct omap_dss_device *dssdev, int channel); | |
661 | void (*disable_video_output)(struct omap_dss_device *dssdev, | |
662 | int channel); | |
663 | ||
664 | int (*request_vc)(struct omap_dss_device *dssdev, int *channel); | |
665 | int (*set_vc_id)(struct omap_dss_device *dssdev, int channel, | |
666 | int vc_id); | |
667 | void (*release_vc)(struct omap_dss_device *dssdev, int channel); | |
668 | ||
669 | /* data transfer */ | |
670 | int (*dcs_write)(struct omap_dss_device *dssdev, int channel, | |
671 | u8 *data, int len); | |
672 | int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel, | |
673 | u8 *data, int len); | |
674 | int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, | |
675 | u8 *data, int len); | |
676 | ||
677 | int (*gen_write)(struct omap_dss_device *dssdev, int channel, | |
678 | u8 *data, int len); | |
679 | int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel, | |
680 | u8 *data, int len); | |
681 | int (*gen_read)(struct omap_dss_device *dssdev, int channel, | |
682 | u8 *reqdata, int reqlen, | |
683 | u8 *data, int len); | |
684 | ||
685 | int (*bta_sync)(struct omap_dss_device *dssdev, int channel); | |
686 | ||
687 | int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev, | |
688 | int channel, u16 plen); | |
689 | }; | |
690 | ||
559d6701 | 691 | struct omap_dss_device { |
ecc8b370 | 692 | struct device *dev; |
559d6701 | 693 | |
4f3e44ea TV |
694 | struct module *owner; |
695 | ||
2e7e3dc7 TV |
696 | struct list_head panel_list; |
697 | ||
698 | /* alias in the form of "display%d" */ | |
699 | char alias[16]; | |
700 | ||
559d6701 | 701 | enum omap_display_type type; |
1f68d9c4 | 702 | enum omap_display_type output_type; |
559d6701 TV |
703 | |
704 | union { | |
705 | struct { | |
706 | u8 data_lines; | |
707 | } dpi; | |
708 | ||
709 | struct { | |
710 | u8 channel; | |
711 | u8 data_lines; | |
712 | } rfbi; | |
713 | ||
714 | struct { | |
715 | u8 datapairs; | |
716 | } sdi; | |
717 | ||
718 | struct { | |
a72b64b9 | 719 | int module; |
559d6701 TV |
720 | } dsi; |
721 | ||
722 | struct { | |
723 | enum omap_dss_venc_type type; | |
724 | bool invert_polarity; | |
725 | } venc; | |
726 | } phy; | |
727 | ||
728 | struct { | |
729 | struct omap_video_timings timings; | |
730 | ||
a3b3cc2b | 731 | enum omap_dss_dsi_pixel_format dsi_pix_fmt; |
7e951ee9 | 732 | enum omap_dss_dsi_mode dsi_mode; |
559d6701 TV |
733 | } panel; |
734 | ||
735 | struct { | |
736 | u8 pixel_size; | |
737 | struct rfbi_timings rfbi_timings; | |
559d6701 TV |
738 | } ctrl; |
739 | ||
559d6701 TV |
740 | const char *name; |
741 | ||
742 | /* used to match device to driver */ | |
743 | const char *driver_name; | |
744 | ||
745 | void *data; | |
746 | ||
747 | struct omap_dss_driver *driver; | |
748 | ||
0b24edb1 TV |
749 | union { |
750 | const struct omapdss_dpi_ops *dpi; | |
b1082dfd | 751 | const struct omapdss_sdi_ops *sdi; |
7700c2d4 | 752 | const struct omapdss_dvi_ops *dvi; |
0b450c31 | 753 | const struct omapdss_hdmi_ops *hdmi; |
fb8efa49 | 754 | const struct omapdss_atv_ops *atv; |
deb16df8 | 755 | const struct omapdss_dsi_ops *dsi; |
0b24edb1 TV |
756 | } ops; |
757 | ||
559d6701 TV |
758 | /* helper variable for driver suspend/resume */ |
759 | bool activate_after_resume; | |
760 | ||
761 | enum omap_display_caps caps; | |
762 | ||
a73fdc64 | 763 | struct omap_dss_device *src; |
559d6701 TV |
764 | |
765 | enum omap_dss_display_state state; | |
766 | ||
1f68d9c4 TV |
767 | /* OMAP DSS output specific fields */ |
768 | ||
769 | struct list_head list; | |
770 | ||
771 | /* DISPC channel for this output */ | |
772 | enum omap_channel dispc_channel; | |
773 | ||
774 | /* output instance */ | |
775 | enum omap_dss_output_id id; | |
776 | ||
ef691ff4 AT |
777 | /* the port number in the DT node */ |
778 | int port_num; | |
779 | ||
1f68d9c4 TV |
780 | /* dynamic fields */ |
781 | struct omap_overlay_manager *manager; | |
782 | ||
9560dc10 | 783 | struct omap_dss_device *dst; |
559d6701 TV |
784 | }; |
785 | ||
c49d005b TV |
786 | struct omap_dss_hdmi_data |
787 | { | |
cca35017 TV |
788 | int ct_cp_hpd_gpio; |
789 | int ls_oe_gpio; | |
c49d005b TV |
790 | int hpd_gpio; |
791 | }; | |
792 | ||
559d6701 | 793 | struct omap_dss_driver { |
559d6701 TV |
794 | int (*probe)(struct omap_dss_device *); |
795 | void (*remove)(struct omap_dss_device *); | |
796 | ||
a7e71e7f TV |
797 | int (*connect)(struct omap_dss_device *dssdev); |
798 | void (*disconnect)(struct omap_dss_device *dssdev); | |
799 | ||
559d6701 TV |
800 | int (*enable)(struct omap_dss_device *display); |
801 | void (*disable)(struct omap_dss_device *display); | |
559d6701 TV |
802 | int (*run_test)(struct omap_dss_device *display, int test); |
803 | ||
18946f62 TV |
804 | int (*update)(struct omap_dss_device *dssdev, |
805 | u16 x, u16 y, u16 w, u16 h); | |
806 | int (*sync)(struct omap_dss_device *dssdev); | |
807 | ||
559d6701 | 808 | int (*enable_te)(struct omap_dss_device *dssdev, bool enable); |
225b650d | 809 | int (*get_te)(struct omap_dss_device *dssdev); |
559d6701 TV |
810 | |
811 | u8 (*get_rotate)(struct omap_dss_device *dssdev); | |
812 | int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate); | |
813 | ||
814 | bool (*get_mirror)(struct omap_dss_device *dssdev); | |
815 | int (*set_mirror)(struct omap_dss_device *dssdev, bool enable); | |
816 | ||
817 | int (*memory_read)(struct omap_dss_device *dssdev, | |
818 | void *buf, size_t size, | |
819 | u16 x, u16 y, u16 w, u16 h); | |
96adcece TV |
820 | |
821 | void (*get_resolution)(struct omap_dss_device *dssdev, | |
822 | u16 *xres, u16 *yres); | |
7a0987bf JN |
823 | void (*get_dimensions)(struct omap_dss_device *dssdev, |
824 | u32 *width, u32 *height); | |
a2699504 | 825 | int (*get_recommended_bpp)(struct omap_dss_device *dssdev); |
36511312 | 826 | |
69b2048f TV |
827 | int (*check_timings)(struct omap_dss_device *dssdev, |
828 | struct omap_video_timings *timings); | |
829 | void (*set_timings)(struct omap_dss_device *dssdev, | |
830 | struct omap_video_timings *timings); | |
831 | void (*get_timings)(struct omap_dss_device *dssdev, | |
832 | struct omap_video_timings *timings); | |
833 | ||
36511312 TV |
834 | int (*set_wss)(struct omap_dss_device *dssdev, u32 wss); |
835 | u32 (*get_wss)(struct omap_dss_device *dssdev); | |
3d5e0ef7 TV |
836 | |
837 | int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len); | |
df4769c9 | 838 | bool (*detect)(struct omap_dss_device *dssdev); |
9c0b8420 | 839 | |
8c071caa TV |
840 | int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode); |
841 | int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev, | |
842 | const struct hdmi_avi_infoframe *avi); | |
559d6701 TV |
843 | }; |
844 | ||
b2c7d54f | 845 | enum omapdss_version omapdss_get_version(void); |
591a0ac7 | 846 | bool omapdss_is_initialized(void); |
b2c7d54f | 847 | |
559d6701 TV |
848 | int omap_dss_register_driver(struct omap_dss_driver *); |
849 | void omap_dss_unregister_driver(struct omap_dss_driver *); | |
850 | ||
2e7e3dc7 TV |
851 | int omapdss_register_display(struct omap_dss_device *dssdev); |
852 | void omapdss_unregister_display(struct omap_dss_device *dssdev); | |
853 | ||
d35317a4 | 854 | struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev); |
559d6701 TV |
855 | void omap_dss_put_device(struct omap_dss_device *dssdev); |
856 | #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL) | |
857 | struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from); | |
858 | struct omap_dss_device *omap_dss_find_device(void *data, | |
859 | int (*match)(struct omap_dss_device *dssdev, void *data)); | |
2bbcce5e | 860 | const char *omapdss_get_default_display_name(void); |
559d6701 | 861 | |
6fcd485b TV |
862 | void videomode_to_omap_video_timings(const struct videomode *vm, |
863 | struct omap_video_timings *ovt); | |
864 | void omap_video_timings_to_videomode(const struct omap_video_timings *ovt, | |
865 | struct videomode *vm); | |
866 | ||
eda34273 TV |
867 | int dss_feat_get_num_mgrs(void); |
868 | int dss_feat_get_num_ovls(void); | |
869 | enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); | |
870 | enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel); | |
871 | enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane); | |
872 | ||
873 | ||
874 | ||
559d6701 TV |
875 | int omap_dss_get_num_overlay_managers(void); |
876 | struct omap_overlay_manager *omap_dss_get_overlay_manager(int num); | |
877 | ||
878 | int omap_dss_get_num_overlays(void); | |
879 | struct omap_overlay *omap_dss_get_overlay(int num); | |
880 | ||
5d47dbc8 TV |
881 | int omapdss_register_output(struct omap_dss_device *output); |
882 | void omapdss_unregister_output(struct omap_dss_device *output); | |
1f68d9c4 TV |
883 | struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id); |
884 | struct omap_dss_device *omap_dss_find_output(const char *name); | |
ef691ff4 | 885 | struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port); |
1f68d9c4 | 886 | int omapdss_output_set_device(struct omap_dss_device *out, |
6d71b923 | 887 | struct omap_dss_device *dssdev); |
1f68d9c4 | 888 | int omapdss_output_unset_device(struct omap_dss_device *out); |
484dc404 | 889 | |
1f68d9c4 | 890 | struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev); |
be8e8e1c TV |
891 | struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev); |
892 | ||
96adcece TV |
893 | void omapdss_default_get_resolution(struct omap_dss_device *dssdev, |
894 | u16 *xres, u16 *yres); | |
a2699504 | 895 | int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev); |
4b6430fc GI |
896 | void omapdss_default_get_timings(struct omap_dss_device *dssdev, |
897 | struct omap_video_timings *timings); | |
a2699504 | 898 | |
559d6701 TV |
899 | typedef void (*omap_dispc_isr_t) (void *arg, u32 mask); |
900 | int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask); | |
901 | int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask); | |
902 | ||
348be69d TV |
903 | u32 dispc_read_irqstatus(void); |
904 | void dispc_clear_irqstatus(u32 mask); | |
905 | u32 dispc_read_irqenable(void); | |
906 | void dispc_write_irqenable(u32 mask); | |
907 | ||
908 | int dispc_request_irq(irq_handler_t handler, void *dev_id); | |
909 | void dispc_free_irq(void *dev_id); | |
910 | ||
911 | int dispc_runtime_get(void); | |
912 | void dispc_runtime_put(void); | |
913 | ||
914 | void dispc_mgr_enable(enum omap_channel channel, bool enable); | |
915 | bool dispc_mgr_is_enabled(enum omap_channel channel); | |
916 | u32 dispc_mgr_get_vsync_irq(enum omap_channel channel); | |
917 | u32 dispc_mgr_get_framedone_irq(enum omap_channel channel); | |
918 | u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel); | |
919 | bool dispc_mgr_go_busy(enum omap_channel channel); | |
920 | void dispc_mgr_go(enum omap_channel channel); | |
921 | void dispc_mgr_set_lcd_config(enum omap_channel channel, | |
922 | const struct dss_lcd_mgr_config *config); | |
923 | void dispc_mgr_set_timings(enum omap_channel channel, | |
924 | const struct omap_video_timings *timings); | |
925 | void dispc_mgr_setup(enum omap_channel channel, | |
926 | const struct omap_overlay_manager_info *info); | |
927 | ||
928 | int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel, | |
929 | const struct omap_overlay_info *oi, | |
930 | const struct omap_video_timings *timings, | |
931 | int *x_predecim, int *y_predecim); | |
932 | ||
933 | int dispc_ovl_enable(enum omap_plane plane, bool enable); | |
934 | bool dispc_ovl_enabled(enum omap_plane plane); | |
935 | void dispc_ovl_set_channel_out(enum omap_plane plane, | |
936 | enum omap_channel channel); | |
937 | int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, | |
938 | bool replication, const struct omap_video_timings *mgr_timings, | |
939 | bool mem_to_mem); | |
940 | ||
8dd2491a TV |
941 | int omapdss_compat_init(void); |
942 | void omapdss_compat_uninit(void); | |
943 | ||
a97a9634 | 944 | struct dss_mgr_ops { |
a7e71e7f | 945 | int (*connect)(struct omap_overlay_manager *mgr, |
1f68d9c4 | 946 | struct omap_dss_device *dst); |
a7e71e7f | 947 | void (*disconnect)(struct omap_overlay_manager *mgr, |
1f68d9c4 | 948 | struct omap_dss_device *dst); |
a7e71e7f | 949 | |
a97a9634 TV |
950 | void (*start_update)(struct omap_overlay_manager *mgr); |
951 | int (*enable)(struct omap_overlay_manager *mgr); | |
952 | void (*disable)(struct omap_overlay_manager *mgr); | |
953 | void (*set_timings)(struct omap_overlay_manager *mgr, | |
954 | const struct omap_video_timings *timings); | |
955 | void (*set_lcd_config)(struct omap_overlay_manager *mgr, | |
956 | const struct dss_lcd_mgr_config *config); | |
957 | int (*register_framedone_handler)(struct omap_overlay_manager *mgr, | |
958 | void (*handler)(void *), void *data); | |
959 | void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr, | |
960 | void (*handler)(void *), void *data); | |
961 | }; | |
962 | ||
963 | int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops); | |
964 | void dss_uninstall_mgr_ops(void); | |
965 | ||
a7e71e7f | 966 | int dss_mgr_connect(struct omap_overlay_manager *mgr, |
1f68d9c4 | 967 | struct omap_dss_device *dst); |
a7e71e7f | 968 | void dss_mgr_disconnect(struct omap_overlay_manager *mgr, |
1f68d9c4 | 969 | struct omap_dss_device *dst); |
a97a9634 TV |
970 | void dss_mgr_set_timings(struct omap_overlay_manager *mgr, |
971 | const struct omap_video_timings *timings); | |
972 | void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr, | |
973 | const struct dss_lcd_mgr_config *config); | |
974 | int dss_mgr_enable(struct omap_overlay_manager *mgr); | |
975 | void dss_mgr_disable(struct omap_overlay_manager *mgr); | |
976 | void dss_mgr_start_update(struct omap_overlay_manager *mgr); | |
977 | int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr, | |
978 | void (*handler)(void *), void *data); | |
979 | void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr, | |
980 | void (*handler)(void *), void *data); | |
a7e71e7f TV |
981 | |
982 | static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev) | |
983 | { | |
a73fdc64 | 984 | return dssdev->src; |
a7e71e7f TV |
985 | } |
986 | ||
987 | static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev) | |
988 | { | |
989 | return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE; | |
990 | } | |
991 | ||
4e7470dd TV |
992 | struct device_node * |
993 | omapdss_of_get_next_port(const struct device_node *parent, | |
994 | struct device_node *prev); | |
995 | ||
996 | struct device_node * | |
997 | omapdss_of_get_next_endpoint(const struct device_node *parent, | |
998 | struct device_node *prev); | |
999 | ||
1000 | struct device_node * | |
1001 | omapdss_of_get_first_endpoint(const struct device_node *parent); | |
1002 | ||
1003 | struct omap_dss_device * | |
1004 | omapdss_of_find_source_for_first_ep(struct device_node *node); | |
1005 | ||
559d6701 | 1006 | #endif |