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5a213a55 | 1 | /* include/video/samsung_fimd.h |
8f995cc3 BD |
2 | * |
3 | * Copyright 2008 Openmoko, Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * http://armlinux.simtec.co.uk/ | |
6 | * Ben Dooks <ben@simtec.co.uk> | |
7 | * | |
5a213a55 | 8 | * S3C Platform - new-style fimd and framebuffer register definitions |
8f995cc3 | 9 | * |
5a213a55 | 10 | * This is the register set for the fimd and new style framebuffer interface |
8f995cc3 BD |
11 | * found from the S3C2443 onwards into the S3C2416, S3C2450 and the |
12 | * S3C64XX series such as the S3C6400 and S3C6410. | |
13 | * | |
14 | * The file does not contain the cpu specific items which are based on | |
15 | * whichever architecture is selected, it only contains the core of the | |
16 | * register set. See <mach/regs-fb.h> to get the specifics. | |
17 | * | |
8f995cc3 BD |
18 | * This program is free software; you can redistribute it and/or modify |
19 | * it under the terms of the GNU General Public License version 2 as | |
20 | * published by the Free Software Foundation. | |
21 | */ | |
22 | ||
8f995cc3 BD |
23 | /* VIDCON0 */ |
24 | ||
25 | #define VIDCON0 (0x00) | |
26 | #define VIDCON0_INTERLACE (1 << 29) | |
27 | #define VIDCON0_VIDOUT_MASK (0x3 << 26) | |
28 | #define VIDCON0_VIDOUT_SHIFT (26) | |
29 | #define VIDCON0_VIDOUT_RGB (0x0 << 26) | |
30 | #define VIDCON0_VIDOUT_TV (0x1 << 26) | |
31 | #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) | |
32 | #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) | |
33 | ||
34 | #define VIDCON0_L1_DATA_MASK (0x7 << 23) | |
35 | #define VIDCON0_L1_DATA_SHIFT (23) | |
36 | #define VIDCON0_L1_DATA_16BPP (0x0 << 23) | |
37 | #define VIDCON0_L1_DATA_18BPP16 (0x1 << 23) | |
38 | #define VIDCON0_L1_DATA_18BPP9 (0x2 << 23) | |
39 | #define VIDCON0_L1_DATA_24BPP (0x3 << 23) | |
40 | #define VIDCON0_L1_DATA_18BPP (0x4 << 23) | |
41 | #define VIDCON0_L1_DATA_16BPP8 (0x5 << 23) | |
42 | ||
43 | #define VIDCON0_L0_DATA_MASK (0x7 << 20) | |
44 | #define VIDCON0_L0_DATA_SHIFT (20) | |
45 | #define VIDCON0_L0_DATA_16BPP (0x0 << 20) | |
46 | #define VIDCON0_L0_DATA_18BPP16 (0x1 << 20) | |
47 | #define VIDCON0_L0_DATA_18BPP9 (0x2 << 20) | |
48 | #define VIDCON0_L0_DATA_24BPP (0x3 << 20) | |
49 | #define VIDCON0_L0_DATA_18BPP (0x4 << 20) | |
50 | #define VIDCON0_L0_DATA_16BPP8 (0x5 << 20) | |
51 | ||
52 | #define VIDCON0_PNRMODE_MASK (0x3 << 17) | |
53 | #define VIDCON0_PNRMODE_SHIFT (17) | |
54 | #define VIDCON0_PNRMODE_RGB (0x0 << 17) | |
55 | #define VIDCON0_PNRMODE_BGR (0x1 << 17) | |
56 | #define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17) | |
57 | #define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17) | |
58 | ||
59 | #define VIDCON0_CLKVALUP (1 << 16) | |
60 | #define VIDCON0_CLKVAL_F_MASK (0xff << 6) | |
61 | #define VIDCON0_CLKVAL_F_SHIFT (6) | |
62 | #define VIDCON0_CLKVAL_F_LIMIT (0xff) | |
63 | #define VIDCON0_CLKVAL_F(_x) ((_x) << 6) | |
64 | #define VIDCON0_VLCKFREE (1 << 5) | |
65 | #define VIDCON0_CLKDIR (1 << 4) | |
66 | ||
67 | #define VIDCON0_CLKSEL_MASK (0x3 << 2) | |
68 | #define VIDCON0_CLKSEL_SHIFT (2) | |
69 | #define VIDCON0_CLKSEL_HCLK (0x0 << 2) | |
70 | #define VIDCON0_CLKSEL_LCD (0x1 << 2) | |
71 | #define VIDCON0_CLKSEL_27M (0x3 << 2) | |
72 | ||
73 | #define VIDCON0_ENVID (1 << 1) | |
74 | #define VIDCON0_ENVID_F (1 << 0) | |
75 | ||
76 | #define VIDCON1 (0x04) | |
77 | #define VIDCON1_LINECNT_MASK (0x7ff << 16) | |
78 | #define VIDCON1_LINECNT_SHIFT (16) | |
79 | #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) | |
80 | #define VIDCON1_VSTATUS_MASK (0x3 << 13) | |
81 | #define VIDCON1_VSTATUS_SHIFT (13) | |
82 | #define VIDCON1_VSTATUS_VSYNC (0x0 << 13) | |
83 | #define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13) | |
84 | #define VIDCON1_VSTATUS_ACTIVE (0x2 << 13) | |
85 | #define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13) | |
d8b97db4 JH |
86 | #define VIDCON1_VCLK_MASK (0x3 << 9) |
87 | #define VIDCON1_VCLK_HOLD (0x0 << 9) | |
88 | #define VIDCON1_VCLK_RUN (0x1 << 9) | |
8f995cc3 BD |
89 | |
90 | #define VIDCON1_INV_VCLK (1 << 7) | |
91 | #define VIDCON1_INV_HSYNC (1 << 6) | |
92 | #define VIDCON1_INV_VSYNC (1 << 5) | |
93 | #define VIDCON1_INV_VDEN (1 << 4) | |
94 | ||
95 | /* VIDCON2 */ | |
96 | ||
97 | #define VIDCON2 (0x08) | |
98 | #define VIDCON2_EN601 (1 << 23) | |
99 | #define VIDCON2_TVFMTSEL_SW (1 << 14) | |
100 | ||
101 | #define VIDCON2_TVFMTSEL1_MASK (0x3 << 12) | |
102 | #define VIDCON2_TVFMTSEL1_SHIFT (12) | |
103 | #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12) | |
104 | #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12) | |
105 | #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12) | |
106 | ||
107 | #define VIDCON2_ORGYCbCr (1 << 8) | |
108 | #define VIDCON2_YUVORDCrCb (1 << 7) | |
109 | ||
067b226b PO |
110 | /* PRTCON (S3C6410, S5PC100) |
111 | * Might not be present in the S3C6410 documentation, | |
112 | * but tests prove it's there almost for sure; shouldn't hurt in any case. | |
113 | */ | |
114 | #define PRTCON (0x0c) | |
115 | #define PRTCON_PROTECT (1 << 11) | |
116 | ||
8f995cc3 BD |
117 | /* VIDTCON0 */ |
118 | ||
9d07a0bf | 119 | #define VIDTCON0 (0x10) |
8f995cc3 BD |
120 | #define VIDTCON0_VBPDE_MASK (0xff << 24) |
121 | #define VIDTCON0_VBPDE_SHIFT (24) | |
122 | #define VIDTCON0_VBPDE_LIMIT (0xff) | |
123 | #define VIDTCON0_VBPDE(_x) ((_x) << 24) | |
124 | ||
125 | #define VIDTCON0_VBPD_MASK (0xff << 16) | |
126 | #define VIDTCON0_VBPD_SHIFT (16) | |
127 | #define VIDTCON0_VBPD_LIMIT (0xff) | |
128 | #define VIDTCON0_VBPD(_x) ((_x) << 16) | |
129 | ||
130 | #define VIDTCON0_VFPD_MASK (0xff << 8) | |
131 | #define VIDTCON0_VFPD_SHIFT (8) | |
132 | #define VIDTCON0_VFPD_LIMIT (0xff) | |
133 | #define VIDTCON0_VFPD(_x) ((_x) << 8) | |
134 | ||
135 | #define VIDTCON0_VSPW_MASK (0xff << 0) | |
136 | #define VIDTCON0_VSPW_SHIFT (0) | |
137 | #define VIDTCON0_VSPW_LIMIT (0xff) | |
138 | #define VIDTCON0_VSPW(_x) ((_x) << 0) | |
139 | ||
140 | /* VIDTCON1 */ | |
141 | ||
9d07a0bf | 142 | #define VIDTCON1 (0x14) |
8f995cc3 BD |
143 | #define VIDTCON1_VFPDE_MASK (0xff << 24) |
144 | #define VIDTCON1_VFPDE_SHIFT (24) | |
145 | #define VIDTCON1_VFPDE_LIMIT (0xff) | |
146 | #define VIDTCON1_VFPDE(_x) ((_x) << 24) | |
147 | ||
148 | #define VIDTCON1_HBPD_MASK (0xff << 16) | |
149 | #define VIDTCON1_HBPD_SHIFT (16) | |
150 | #define VIDTCON1_HBPD_LIMIT (0xff) | |
151 | #define VIDTCON1_HBPD(_x) ((_x) << 16) | |
152 | ||
153 | #define VIDTCON1_HFPD_MASK (0xff << 8) | |
154 | #define VIDTCON1_HFPD_SHIFT (8) | |
155 | #define VIDTCON1_HFPD_LIMIT (0xff) | |
156 | #define VIDTCON1_HFPD(_x) ((_x) << 8) | |
157 | ||
158 | #define VIDTCON1_HSPW_MASK (0xff << 0) | |
159 | #define VIDTCON1_HSPW_SHIFT (0) | |
160 | #define VIDTCON1_HSPW_LIMIT (0xff) | |
161 | #define VIDTCON1_HSPW(_x) ((_x) << 0) | |
162 | ||
9d07a0bf | 163 | #define VIDTCON2 (0x18) |
8f995cc3 | 164 | #define VIDTCON2 (0x18) |
5c44778e | 165 | #define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23) |
8f995cc3 BD |
166 | #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) |
167 | #define VIDTCON2_LINEVAL_SHIFT (11) | |
168 | #define VIDTCON2_LINEVAL_LIMIT (0x7ff) | |
5c44778e | 169 | #define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11) |
8f995cc3 | 170 | |
5c44778e | 171 | #define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22) |
8f995cc3 BD |
172 | #define VIDTCON2_HOZVAL_MASK (0x7ff << 0) |
173 | #define VIDTCON2_HOZVAL_SHIFT (0) | |
174 | #define VIDTCON2_HOZVAL_LIMIT (0x7ff) | |
5c44778e | 175 | #define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0) |
8f995cc3 BD |
176 | |
177 | /* WINCONx */ | |
178 | ||
36ff8d54 JH |
179 | #define WINCON(_win) (0x20 + ((_win) * 4)) |
180 | #define WINCONx_CSCWIDTH_MASK (0x3 << 26) | |
181 | #define WINCONx_CSCWIDTH_SHIFT (26) | |
182 | #define WINCONx_CSCWIDTH_WIDE (0x0 << 26) | |
183 | #define WINCONx_CSCWIDTH_NARROW (0x3 << 26) | |
184 | #define WINCONx_ENLOCAL (1 << 22) | |
185 | #define WINCONx_BUFSTATUS (1 << 21) | |
186 | #define WINCONx_BUFSEL (1 << 20) | |
187 | #define WINCONx_BUFAUTOEN (1 << 19) | |
8f995cc3 BD |
188 | #define WINCONx_BITSWP (1 << 18) |
189 | #define WINCONx_BYTSWP (1 << 17) | |
190 | #define WINCONx_HAWSWP (1 << 16) | |
dc8498c0 | 191 | #define WINCONx_WSWP (1 << 15) |
36ff8d54 | 192 | #define WINCONx_YCbCr (1 << 13) |
8f995cc3 BD |
193 | #define WINCONx_BURSTLEN_MASK (0x3 << 9) |
194 | #define WINCONx_BURSTLEN_SHIFT (9) | |
195 | #define WINCONx_BURSTLEN_16WORD (0x0 << 9) | |
196 | #define WINCONx_BURSTLEN_8WORD (0x1 << 9) | |
197 | #define WINCONx_BURSTLEN_4WORD (0x2 << 9) | |
8f995cc3 | 198 | #define WINCONx_ENWIN (1 << 0) |
36ff8d54 | 199 | |
8f995cc3 BD |
200 | #define WINCON0_BPPMODE_MASK (0xf << 2) |
201 | #define WINCON0_BPPMODE_SHIFT (2) | |
202 | #define WINCON0_BPPMODE_1BPP (0x0 << 2) | |
203 | #define WINCON0_BPPMODE_2BPP (0x1 << 2) | |
204 | #define WINCON0_BPPMODE_4BPP (0x2 << 2) | |
205 | #define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2) | |
206 | #define WINCON0_BPPMODE_16BPP_565 (0x5 << 2) | |
207 | #define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2) | |
208 | #define WINCON0_BPPMODE_18BPP_666 (0x8 << 2) | |
209 | #define WINCON0_BPPMODE_24BPP_888 (0xb << 2) | |
210 | ||
36ff8d54 | 211 | #define WINCON1_LOCALSEL_CAMIF (1 << 23) |
8f995cc3 | 212 | #define WINCON1_BLD_PIX (1 << 6) |
8f995cc3 BD |
213 | #define WINCON1_BPPMODE_MASK (0xf << 2) |
214 | #define WINCON1_BPPMODE_SHIFT (2) | |
215 | #define WINCON1_BPPMODE_1BPP (0x0 << 2) | |
216 | #define WINCON1_BPPMODE_2BPP (0x1 << 2) | |
217 | #define WINCON1_BPPMODE_4BPP (0x2 << 2) | |
218 | #define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2) | |
219 | #define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2) | |
220 | #define WINCON1_BPPMODE_16BPP_565 (0x5 << 2) | |
221 | #define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2) | |
222 | #define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2) | |
223 | #define WINCON1_BPPMODE_18BPP_666 (0x8 << 2) | |
224 | #define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2) | |
225 | #define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2) | |
226 | #define WINCON1_BPPMODE_24BPP_888 (0xb << 2) | |
227 | #define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2) | |
228 | #define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2) | |
229 | #define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2) | |
36ff8d54 | 230 | #define WINCON1_ALPHA_SEL (1 << 1) |
8f995cc3 | 231 | |
f5ec546f PO |
232 | /* S5PV210 */ |
233 | #define SHADOWCON (0x34) | |
234 | #define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win))) | |
04ab9ef9 PO |
235 | /* DMA channels (all windows) */ |
236 | #define SHADOWCON_CHx_ENABLE(_win) (1 << (_win)) | |
237 | /* Local input channels (windows 0-2) */ | |
238 | #define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win))) | |
8f995cc3 | 239 | |
99a2c61e JH |
240 | /* VIDOSDx */ |
241 | ||
242 | #define VIDOSD_BASE (0x40) | |
5c44778e | 243 | #define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23) |
8f995cc3 BD |
244 | #define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) |
245 | #define VIDOSDxA_TOPLEFT_X_SHIFT (11) | |
246 | #define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff) | |
5c44778e | 247 | #define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11) |
8f995cc3 | 248 | |
5c44778e | 249 | #define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22) |
8f995cc3 BD |
250 | #define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0) |
251 | #define VIDOSDxA_TOPLEFT_Y_SHIFT (0) | |
252 | #define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff) | |
5c44778e | 253 | #define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0) |
8f995cc3 | 254 | |
5c44778e | 255 | #define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23) |
8f995cc3 BD |
256 | #define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11) |
257 | #define VIDOSDxB_BOTRIGHT_X_SHIFT (11) | |
258 | #define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff) | |
5c44778e | 259 | #define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11) |
8f995cc3 | 260 | |
5c44778e | 261 | #define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22) |
8f995cc3 BD |
262 | #define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0) |
263 | #define VIDOSDxB_BOTRIGHT_Y_SHIFT (0) | |
264 | #define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff) | |
5c44778e | 265 | #define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0) |
8f995cc3 BD |
266 | |
267 | /* For VIDOSD[1..4]C */ | |
268 | #define VIDISD14C_ALPHA0_R(_x) ((_x) << 20) | |
269 | #define VIDISD14C_ALPHA0_G_MASK (0xf << 16) | |
270 | #define VIDISD14C_ALPHA0_G_SHIFT (16) | |
271 | #define VIDISD14C_ALPHA0_G_LIMIT (0xf) | |
272 | #define VIDISD14C_ALPHA0_G(_x) ((_x) << 16) | |
273 | #define VIDISD14C_ALPHA0_B_MASK (0xf << 12) | |
274 | #define VIDISD14C_ALPHA0_B_SHIFT (12) | |
275 | #define VIDISD14C_ALPHA0_B_LIMIT (0xf) | |
276 | #define VIDISD14C_ALPHA0_B(_x) ((_x) << 12) | |
277 | #define VIDISD14C_ALPHA1_R_MASK (0xf << 8) | |
278 | #define VIDISD14C_ALPHA1_R_SHIFT (8) | |
279 | #define VIDISD14C_ALPHA1_R_LIMIT (0xf) | |
280 | #define VIDISD14C_ALPHA1_R(_x) ((_x) << 8) | |
281 | #define VIDISD14C_ALPHA1_G_MASK (0xf << 4) | |
282 | #define VIDISD14C_ALPHA1_G_SHIFT (4) | |
283 | #define VIDISD14C_ALPHA1_G_LIMIT (0xf) | |
284 | #define VIDISD14C_ALPHA1_G(_x) ((_x) << 4) | |
285 | #define VIDISD14C_ALPHA1_B_MASK (0xf << 0) | |
286 | #define VIDISD14C_ALPHA1_B_SHIFT (0) | |
287 | #define VIDISD14C_ALPHA1_B_LIMIT (0xf) | |
288 | #define VIDISD14C_ALPHA1_B(_x) ((_x) << 0) | |
289 | ||
290 | /* Video buffer addresses */ | |
291 | #define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8)) | |
292 | #define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8)) | |
293 | #define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8)) | |
294 | #define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) | |
295 | #define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) | |
296 | ||
5c44778e | 297 | #define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27) |
8f995cc3 BD |
298 | #define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13) |
299 | #define VIDW_BUF_SIZE_OFFSET_SHIFT (13) | |
300 | #define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff) | |
5c44778e | 301 | #define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13) |
8f995cc3 | 302 | |
5c44778e | 303 | #define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26) |
8f995cc3 BD |
304 | #define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0) |
305 | #define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0) | |
306 | #define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff) | |
5c44778e | 307 | #define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0) |
8f995cc3 BD |
308 | |
309 | /* Interrupt controls and status */ | |
310 | ||
60eb8d83 | 311 | #define VIDINTCON0 (0x130) |
8f995cc3 BD |
312 | #define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20) |
313 | #define VIDINTCON0_FIFOINTERVAL_SHIFT (20) | |
314 | #define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f) | |
315 | #define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20) | |
316 | ||
317 | #define VIDINTCON0_INT_SYSMAINCON (1 << 19) | |
318 | #define VIDINTCON0_INT_SYSSUBCON (1 << 18) | |
319 | #define VIDINTCON0_INT_I80IFDONE (1 << 17) | |
320 | ||
321 | #define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15) | |
322 | #define VIDINTCON0_FRAMESEL0_SHIFT (15) | |
323 | #define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15) | |
324 | #define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15) | |
325 | #define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15) | |
326 | #define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15) | |
327 | ||
9fa424a4 | 328 | #define VIDINTCON0_FRAMESEL1 (1 << 13) |
efdc846d | 329 | #define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13) |
9fa424a4 PO |
330 | #define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13) |
331 | #define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13) | |
332 | #define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13) | |
333 | #define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13) | |
8f995cc3 BD |
334 | |
335 | #define VIDINTCON0_INT_FRAME (1 << 12) | |
336 | #define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5) | |
337 | #define VIDINTCON0_FIFIOSEL_SHIFT (5) | |
338 | #define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5) | |
339 | #define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5) | |
60eb8d83 JH |
340 | #define VIDINTCON0_FIFIOSEL_WINDOW2 (0x10 << 5) |
341 | #define VIDINTCON0_FIFIOSEL_WINDOW3 (0x20 << 5) | |
342 | #define VIDINTCON0_FIFIOSEL_WINDOW4 (0x40 << 5) | |
8f995cc3 BD |
343 | |
344 | #define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2) | |
345 | #define VIDINTCON0_FIFOLEVEL_SHIFT (2) | |
346 | #define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2) | |
347 | #define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2) | |
348 | #define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2) | |
349 | #define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2) | |
350 | #define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2) | |
351 | ||
352 | #define VIDINTCON0_INT_FIFO_MASK (0x3 << 0) | |
353 | #define VIDINTCON0_INT_FIFO_SHIFT (0) | |
354 | #define VIDINTCON0_INT_ENABLE (1 << 0) | |
355 | ||
356 | #define VIDINTCON1 (0x134) | |
357 | #define VIDINTCON1_INT_I180 (1 << 2) | |
358 | #define VIDINTCON1_INT_FRAME (1 << 1) | |
359 | #define VIDINTCON1_INT_FIFO (1 << 0) | |
360 | ||
361 | /* Window colour-key control registers */ | |
c4bb6ffa BD |
362 | #define WKEYCON (0x140) /* 6410,V210 */ |
363 | ||
364 | #define WKEYCON0 (0x00) | |
365 | #define WKEYCON1 (0x04) | |
8f995cc3 BD |
366 | |
367 | #define WxKEYCON0_KEYBL_EN (1 << 26) | |
368 | #define WxKEYCON0_KEYEN_F (1 << 25) | |
369 | #define WxKEYCON0_DIRCON (1 << 24) | |
370 | #define WxKEYCON0_COMPKEY_MASK (0xffffff << 0) | |
371 | #define WxKEYCON0_COMPKEY_SHIFT (0) | |
372 | #define WxKEYCON0_COMPKEY_LIMIT (0xffffff) | |
373 | #define WxKEYCON0_COMPKEY(_x) ((_x) << 0) | |
374 | #define WxKEYCON1_COLVAL_MASK (0xffffff << 0) | |
375 | #define WxKEYCON1_COLVAL_SHIFT (0) | |
376 | #define WxKEYCON1_COLVAL_LIMIT (0xffffff) | |
377 | #define WxKEYCON1_COLVAL(_x) ((_x) << 0) | |
378 | ||
379 | ||
380 | /* Window blanking (MAP) */ | |
381 | ||
382 | #define WINxMAP_MAP (1 << 24) | |
383 | #define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) | |
384 | #define WINxMAP_MAP_COLOUR_SHIFT (0) | |
385 | #define WINxMAP_MAP_COLOUR_LIMIT (0xffffff) | |
386 | #define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) | |
387 | ||
388 | #define WPALCON_PAL_UPDATE (1 << 9) | |
389 | #define WPALCON_W1PAL_MASK (0x7 << 3) | |
390 | #define WPALCON_W1PAL_SHIFT (3) | |
391 | #define WPALCON_W1PAL_25BPP_A888 (0x0 << 3) | |
392 | #define WPALCON_W1PAL_24BPP (0x1 << 3) | |
393 | #define WPALCON_W1PAL_19BPP_A666 (0x2 << 3) | |
394 | #define WPALCON_W1PAL_18BPP_A665 (0x3 << 3) | |
395 | #define WPALCON_W1PAL_18BPP (0x4 << 3) | |
396 | #define WPALCON_W1PAL_16BPP_A555 (0x5 << 3) | |
397 | #define WPALCON_W1PAL_16BPP_565 (0x6 << 3) | |
398 | ||
399 | #define WPALCON_W0PAL_MASK (0x7 << 0) | |
400 | #define WPALCON_W0PAL_SHIFT (0) | |
401 | #define WPALCON_W0PAL_25BPP_A888 (0x0 << 0) | |
402 | #define WPALCON_W0PAL_24BPP (0x1 << 0) | |
403 | #define WPALCON_W0PAL_19BPP_A666 (0x2 << 0) | |
404 | #define WPALCON_W0PAL_18BPP_A665 (0x3 << 0) | |
405 | #define WPALCON_W0PAL_18BPP (0x4 << 0) | |
406 | #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0) | |
407 | #define WPALCON_W0PAL_16BPP_565 (0x6 << 0) | |
408 | ||
f7f31e50 JH |
409 | /* Blending equation control */ |
410 | #define BLENDCON (0x260) | |
411 | #define BLENDCON_NEW_MASK (1 << 0) | |
412 | #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0) | |
413 | #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) | |
414 | ||
5a213a55 LKA |
415 | #define S3C_FB_MAX_WIN (5) /* number of hardware windows available. */ |
416 | #define VIDCON1_FSTATUS_EVEN (1 << 15) | |
417 | ||
5a213a55 LKA |
418 | #define DITHMODE (0x170) |
419 | #define WINxMAP(_win) (0x180 + ((_win) * 4)) | |
420 | ||
421 | ||
422 | #define DITHMODE_R_POS_MASK (0x3 << 5) | |
423 | #define DITHMODE_R_POS_SHIFT (5) | |
424 | #define DITHMODE_R_POS_8BIT (0x0 << 5) | |
425 | #define DITHMODE_R_POS_6BIT (0x1 << 5) | |
426 | #define DITHMODE_R_POS_5BIT (0x2 << 5) | |
427 | ||
428 | #define DITHMODE_G_POS_MASK (0x3 << 3) | |
429 | #define DITHMODE_G_POS_SHIFT (3) | |
430 | #define DITHMODE_G_POS_8BIT (0x0 << 3) | |
431 | #define DITHMODE_G_POS_6BIT (0x1 << 3) | |
432 | #define DITHMODE_G_POS_5BIT (0x2 << 3) | |
433 | ||
434 | #define DITHMODE_B_POS_MASK (0x3 << 1) | |
435 | #define DITHMODE_B_POS_SHIFT (1) | |
436 | #define DITHMODE_B_POS_8BIT (0x0 << 1) | |
437 | #define DITHMODE_B_POS_6BIT (0x1 << 1) | |
438 | #define DITHMODE_B_POS_5BIT (0x2 << 1) | |
439 | ||
440 | #define DITHMODE_DITH_EN (1 << 0) | |
441 | ||
442 | #define WPALCON (0x1A0) | |
443 | ||
444 | /* Palette control */ | |
445 | /* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L), | |
446 | * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */ | |
447 | #define WPALCON_W4PAL_16BPP_A555 (1 << 8) | |
448 | #define WPALCON_W3PAL_16BPP_A555 (1 << 7) | |
449 | #define WPALCON_W2PAL_16BPP_A555 (1 << 6) | |
450 | ||
451 | ||
452 | /* Notes on per-window bpp settings | |
453 | * | |
454 | * Value Win0 Win1 Win2 Win3 Win 4 | |
455 | * 0000 1(P) 1(P) 1(P) 1(P) 1(P) | |
456 | * 0001 2(P) 2(P) 2(P) 2(P) 2(P) | |
457 | * 0010 4(P) 4(P) 4(P) 4(P) -none- | |
458 | * 0011 8(P) 8(P) -none- -none- -none- | |
459 | * 0100 -none- 8(A232) 8(A232) -none- -none- | |
460 | * 0101 16(565) 16(565) 16(565) 16(565) 16(565) | |
461 | * 0110 -none- 16(A555) 16(A555) 16(A555) 16(A555) | |
462 | * 0111 16(I555) 16(I565) 16(I555) 16(I555) 16(I555) | |
463 | * 1000 18(666) 18(666) 18(666) 18(666) 18(666) | |
464 | * 1001 -none- 18(A665) 18(A665) 18(A665) 16(A665) | |
465 | * 1010 -none- 19(A666) 19(A666) 19(A666) 19(A666) | |
466 | * 1011 24(888) 24(888) 24(888) 24(888) 24(888) | |
467 | * 1100 -none- 24(A887) 24(A887) 24(A887) 24(A887) | |
468 | * 1101 -none- 25(A888) 25(A888) 25(A888) 25(A888) | |
469 | * 1110 -none- -none- -none- -none- -none- | |
470 | * 1111 -none- -none- -none- -none- -none- | |
471 | */ | |
a44cf75d LKA |
472 | |
473 | /* FIMD Version 8 register offset definitions */ | |
474 | #define FIMD_V8_VIDTCON0 (0x20010) | |
475 | #define FIMD_V8_VIDTCON1 (0x20014) | |
476 | #define FIMD_V8_VIDTCON2 (0x20018) | |
477 | #define FIMD_V8_VIDTCON3 (0x2001C) | |
478 | #define FIMD_V8_VIDCON1 (0x20004) |