Merge remote-tracking branch 'cgroup/for-next'
[deliverable/linux.git] / kernel / irq / chip.c
CommitLineData
dd87eb3a
TG
1/*
2 * linux/kernel/irq/chip.c
3 *
4 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
5 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 *
7 * This file contains the core interrupt handling code, for irq-chip
8 * based architectures.
9 *
10 * Detailed information is available in Documentation/DocBook/genericirq
11 */
12
13#include <linux/irq.h>
7fe3730d 14#include <linux/msi.h>
dd87eb3a
TG
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
f8264e34 18#include <linux/irqdomain.h>
dd87eb3a 19
f069686e
SR
20#include <trace/events/irq.h>
21
dd87eb3a
TG
22#include "internals.h"
23
e509bd7d
MW
24static irqreturn_t bad_chained_irq(int irq, void *dev_id)
25{
26 WARN_ONCE(1, "Chained irq %d should not call an action\n", irq);
27 return IRQ_NONE;
28}
29
30/*
31 * Chained handlers should never call action on their IRQ. This default
32 * action will emit warning if such thing happens.
33 */
34struct irqaction chained_action = {
35 .handler = bad_chained_irq,
36};
37
dd87eb3a 38/**
a0cd9ca2 39 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
40 * @irq: irq number
41 * @chip: pointer to irq chip description structure
42 */
a0cd9ca2 43int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 44{
dd87eb3a 45 unsigned long flags;
31d9d9b6 46 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 47
02725e74 48 if (!desc)
dd87eb3a 49 return -EINVAL;
dd87eb3a
TG
50
51 if (!chip)
52 chip = &no_irq_chip;
53
6b8ff312 54 desc->irq_data.chip = chip;
02725e74 55 irq_put_desc_unlock(desc, flags);
d72274e5
DD
56 /*
57 * For !CONFIG_SPARSE_IRQ make the irq show up in
f63b6a05 58 * allocated_irqs.
d72274e5 59 */
f63b6a05 60 irq_mark_irq(irq);
dd87eb3a
TG
61 return 0;
62}
a0cd9ca2 63EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
64
65/**
a0cd9ca2 66 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 67 * @irq: irq number
0c5d1eb7 68 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 69 */
a0cd9ca2 70int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 71{
dd87eb3a 72 unsigned long flags;
31d9d9b6 73 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
02725e74 74 int ret = 0;
dd87eb3a 75
02725e74
TG
76 if (!desc)
77 return -EINVAL;
dd87eb3a 78
a1ff541a 79 ret = __irq_set_trigger(desc, type);
02725e74 80 irq_put_desc_busunlock(desc, flags);
dd87eb3a
TG
81 return ret;
82}
a0cd9ca2 83EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
84
85/**
a0cd9ca2 86 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
87 * @irq: Interrupt number
88 * @data: Pointer to interrupt specific data
89 *
90 * Set the hardware irq controller data for an irq
91 */
a0cd9ca2 92int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 93{
dd87eb3a 94 unsigned long flags;
31d9d9b6 95 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 96
02725e74 97 if (!desc)
dd87eb3a 98 return -EINVAL;
af7080e0 99 desc->irq_common_data.handler_data = data;
02725e74 100 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
101 return 0;
102}
a0cd9ca2 103EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 104
5b912c10 105/**
51906e77
AG
106 * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset
107 * @irq_base: Interrupt number base
108 * @irq_offset: Interrupt number offset
109 * @entry: Pointer to MSI descriptor data
5b912c10 110 *
51906e77 111 * Set the MSI descriptor entry for an irq at offset
5b912c10 112 */
51906e77
AG
113int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
114 struct msi_desc *entry)
5b912c10 115{
5b912c10 116 unsigned long flags;
51906e77 117 struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
5b912c10 118
02725e74 119 if (!desc)
5b912c10 120 return -EINVAL;
b237721c 121 desc->irq_common_data.msi_desc = entry;
51906e77
AG
122 if (entry && !irq_offset)
123 entry->irq = irq_base;
02725e74 124 irq_put_desc_unlock(desc, flags);
5b912c10
EB
125 return 0;
126}
127
51906e77
AG
128/**
129 * irq_set_msi_desc - set MSI descriptor data for an irq
130 * @irq: Interrupt number
131 * @entry: Pointer to MSI descriptor data
132 *
133 * Set the MSI descriptor entry for an irq
134 */
135int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
136{
137 return irq_set_msi_desc_off(irq, 0, entry);
138}
139
dd87eb3a 140/**
a0cd9ca2 141 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
142 * @irq: Interrupt number
143 * @data: Pointer to chip specific data
144 *
145 * Set the hardware irq chip data for an irq
146 */
a0cd9ca2 147int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 148{
dd87eb3a 149 unsigned long flags;
31d9d9b6 150 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 151
02725e74 152 if (!desc)
dd87eb3a 153 return -EINVAL;
6b8ff312 154 desc->irq_data.chip_data = data;
02725e74 155 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
156 return 0;
157}
a0cd9ca2 158EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 159
f303a6dd
TG
160struct irq_data *irq_get_irq_data(unsigned int irq)
161{
162 struct irq_desc *desc = irq_to_desc(irq);
163
164 return desc ? &desc->irq_data : NULL;
165}
166EXPORT_SYMBOL_GPL(irq_get_irq_data);
167
c1594b77
TG
168static void irq_state_clr_disabled(struct irq_desc *desc)
169{
801a0e9a 170 irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
171}
172
173static void irq_state_set_disabled(struct irq_desc *desc)
174{
801a0e9a 175 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
176}
177
6e40262e
TG
178static void irq_state_clr_masked(struct irq_desc *desc)
179{
32f4125e 180 irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
181}
182
183static void irq_state_set_masked(struct irq_desc *desc)
184{
32f4125e 185 irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
186}
187
b4bc724e 188int irq_startup(struct irq_desc *desc, bool resend)
46999238 189{
b4bc724e
TG
190 int ret = 0;
191
c1594b77 192 irq_state_clr_disabled(desc);
46999238
TG
193 desc->depth = 0;
194
f8264e34 195 irq_domain_activate_irq(&desc->irq_data);
3aae994f 196 if (desc->irq_data.chip->irq_startup) {
b4bc724e 197 ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
6e40262e 198 irq_state_clr_masked(desc);
b4bc724e
TG
199 } else {
200 irq_enable(desc);
3aae994f 201 }
b4bc724e 202 if (resend)
0798abeb 203 check_irq_resend(desc);
b4bc724e 204 return ret;
46999238
TG
205}
206
207void irq_shutdown(struct irq_desc *desc)
208{
c1594b77 209 irq_state_set_disabled(desc);
46999238 210 desc->depth = 1;
50f7c032
TG
211 if (desc->irq_data.chip->irq_shutdown)
212 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
ed585a65 213 else if (desc->irq_data.chip->irq_disable)
50f7c032
TG
214 desc->irq_data.chip->irq_disable(&desc->irq_data);
215 else
216 desc->irq_data.chip->irq_mask(&desc->irq_data);
f8264e34 217 irq_domain_deactivate_irq(&desc->irq_data);
6e40262e 218 irq_state_set_masked(desc);
46999238
TG
219}
220
87923470
TG
221void irq_enable(struct irq_desc *desc)
222{
c1594b77 223 irq_state_clr_disabled(desc);
50f7c032
TG
224 if (desc->irq_data.chip->irq_enable)
225 desc->irq_data.chip->irq_enable(&desc->irq_data);
226 else
227 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 228 irq_state_clr_masked(desc);
dd87eb3a
TG
229}
230
d671a605 231/**
f788e7bf 232 * irq_disable - Mark interrupt disabled
d671a605
AF
233 * @desc: irq descriptor which should be disabled
234 *
235 * If the chip does not implement the irq_disable callback, we
236 * use a lazy disable approach. That means we mark the interrupt
237 * disabled, but leave the hardware unmasked. That's an
238 * optimization because we avoid the hardware access for the
239 * common case where no interrupt happens after we marked it
240 * disabled. If an interrupt happens, then the interrupt flow
241 * handler masks the line at the hardware level and marks it
242 * pending.
e9849777
TG
243 *
244 * If the interrupt chip does not implement the irq_disable callback,
245 * a driver can disable the lazy approach for a particular irq line by
246 * calling 'irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY)'. This can
247 * be used for devices which cannot disable the interrupt at the
248 * device level under certain circumstances and have to use
249 * disable_irq[_nosync] instead.
d671a605 250 */
50f7c032 251void irq_disable(struct irq_desc *desc)
89d694b9 252{
c1594b77 253 irq_state_set_disabled(desc);
50f7c032
TG
254 if (desc->irq_data.chip->irq_disable) {
255 desc->irq_data.chip->irq_disable(&desc->irq_data);
a61d8258 256 irq_state_set_masked(desc);
e9849777
TG
257 } else if (irq_settings_disable_unlazy(desc)) {
258 mask_irq(desc);
50f7c032 259 }
89d694b9
TG
260}
261
31d9d9b6
MZ
262void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
263{
264 if (desc->irq_data.chip->irq_enable)
265 desc->irq_data.chip->irq_enable(&desc->irq_data);
266 else
267 desc->irq_data.chip->irq_unmask(&desc->irq_data);
268 cpumask_set_cpu(cpu, desc->percpu_enabled);
269}
270
271void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
272{
273 if (desc->irq_data.chip->irq_disable)
274 desc->irq_data.chip->irq_disable(&desc->irq_data);
275 else
276 desc->irq_data.chip->irq_mask(&desc->irq_data);
277 cpumask_clear_cpu(cpu, desc->percpu_enabled);
278}
279
9205e31d 280static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 281{
9205e31d
TG
282 if (desc->irq_data.chip->irq_mask_ack)
283 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
dd87eb3a 284 else {
e2c0f8ff 285 desc->irq_data.chip->irq_mask(&desc->irq_data);
22a49163
TG
286 if (desc->irq_data.chip->irq_ack)
287 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 288 }
6e40262e 289 irq_state_set_masked(desc);
0b1adaa0
TG
290}
291
d4d5e089 292void mask_irq(struct irq_desc *desc)
0b1adaa0 293{
e2c0f8ff
TG
294 if (desc->irq_data.chip->irq_mask) {
295 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 296 irq_state_set_masked(desc);
0b1adaa0
TG
297 }
298}
299
d4d5e089 300void unmask_irq(struct irq_desc *desc)
0b1adaa0 301{
0eda58b7
TG
302 if (desc->irq_data.chip->irq_unmask) {
303 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 304 irq_state_clr_masked(desc);
0b1adaa0 305 }
dd87eb3a
TG
306}
307
328a4978
TG
308void unmask_threaded_irq(struct irq_desc *desc)
309{
310 struct irq_chip *chip = desc->irq_data.chip;
311
312 if (chip->flags & IRQCHIP_EOI_THREADED)
313 chip->irq_eoi(&desc->irq_data);
314
315 if (chip->irq_unmask) {
316 chip->irq_unmask(&desc->irq_data);
317 irq_state_clr_masked(desc);
318 }
319}
320
399b5da2
TG
321/*
322 * handle_nested_irq - Handle a nested irq from a irq thread
323 * @irq: the interrupt number
324 *
325 * Handle interrupts which are nested into a threaded interrupt
326 * handler. The handler function is called inside the calling
327 * threads context.
328 */
329void handle_nested_irq(unsigned int irq)
330{
331 struct irq_desc *desc = irq_to_desc(irq);
332 struct irqaction *action;
333 irqreturn_t action_ret;
334
335 might_sleep();
336
239007b8 337 raw_spin_lock_irq(&desc->lock);
399b5da2 338
293a7a0a 339 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
399b5da2
TG
340
341 action = desc->action;
23812b9d
NJ
342 if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
343 desc->istate |= IRQS_PENDING;
399b5da2 344 goto out_unlock;
23812b9d 345 }
399b5da2 346
a946e8c7 347 kstat_incr_irqs_this_cpu(desc);
32f4125e 348 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
239007b8 349 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
350
351 action_ret = action->thread_fn(action->irq, action->dev_id);
352 if (!noirqdebug)
0dcdbc97 353 note_interrupt(desc, action_ret);
399b5da2 354
239007b8 355 raw_spin_lock_irq(&desc->lock);
32f4125e 356 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
399b5da2
TG
357
358out_unlock:
239007b8 359 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
360}
361EXPORT_SYMBOL_GPL(handle_nested_irq);
362
fe200ae4
TG
363static bool irq_check_poll(struct irq_desc *desc)
364{
6954b75b 365 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
366 return false;
367 return irq_wait_for_poll(desc);
368}
369
c7bd3ec0
TG
370static bool irq_may_run(struct irq_desc *desc)
371{
9ce7a258
TG
372 unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED;
373
374 /*
375 * If the interrupt is not in progress and is not an armed
376 * wakeup interrupt, proceed.
377 */
378 if (!irqd_has_set(&desc->irq_data, mask))
c7bd3ec0 379 return true;
9ce7a258
TG
380
381 /*
382 * If the interrupt is an armed wakeup source, mark it pending
383 * and suspended, disable it and notify the pm core about the
384 * event.
385 */
386 if (irq_pm_check_wakeup(desc))
387 return false;
388
389 /*
390 * Handle a potential concurrent poll on a different core.
391 */
c7bd3ec0
TG
392 return irq_check_poll(desc);
393}
394
dd87eb3a
TG
395/**
396 * handle_simple_irq - Simple and software-decoded IRQs.
dd87eb3a 397 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
398 *
399 * Simple interrupts are either sent from a demultiplexing interrupt
400 * handler or come from hardware, where no interrupt hardware control
401 * is necessary.
402 *
403 * Note: The caller is expected to handle the ack, clear, mask and
404 * unmask issues if necessary.
405 */
bd0b9ac4 406void handle_simple_irq(struct irq_desc *desc)
dd87eb3a 407{
239007b8 408 raw_spin_lock(&desc->lock);
dd87eb3a 409
c7bd3ec0
TG
410 if (!irq_may_run(desc))
411 goto out_unlock;
fe200ae4 412
163ef309 413 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a 414
23812b9d
NJ
415 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
416 desc->istate |= IRQS_PENDING;
dd87eb3a 417 goto out_unlock;
23812b9d 418 }
dd87eb3a 419
a946e8c7 420 kstat_incr_irqs_this_cpu(desc);
107781e7 421 handle_irq_event(desc);
dd87eb3a 422
dd87eb3a 423out_unlock:
239007b8 424 raw_spin_unlock(&desc->lock);
dd87eb3a 425}
edf76f83 426EXPORT_SYMBOL_GPL(handle_simple_irq);
dd87eb3a 427
edd14cfe
KB
428/**
429 * handle_untracked_irq - Simple and software-decoded IRQs.
430 * @desc: the interrupt description structure for this irq
431 *
432 * Untracked interrupts are sent from a demultiplexing interrupt
433 * handler when the demultiplexer does not know which device it its
434 * multiplexed irq domain generated the interrupt. IRQ's handled
435 * through here are not subjected to stats tracking, randomness, or
436 * spurious interrupt detection.
437 *
438 * Note: Like handle_simple_irq, the caller is expected to handle
439 * the ack, clear, mask and unmask issues if necessary.
440 */
441void handle_untracked_irq(struct irq_desc *desc)
442{
443 unsigned int flags = 0;
444
445 raw_spin_lock(&desc->lock);
446
447 if (!irq_may_run(desc))
448 goto out_unlock;
449
450 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
451
452 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
453 desc->istate |= IRQS_PENDING;
454 goto out_unlock;
455 }
456
457 desc->istate &= ~IRQS_PENDING;
458 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
459 raw_spin_unlock(&desc->lock);
460
461 __handle_irq_event_percpu(desc, &flags);
462
463 raw_spin_lock(&desc->lock);
464 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
465
466out_unlock:
467 raw_spin_unlock(&desc->lock);
468}
469EXPORT_SYMBOL_GPL(handle_untracked_irq);
470
ac563761
TG
471/*
472 * Called unconditionally from handle_level_irq() and only for oneshot
473 * interrupts from handle_fasteoi_irq()
474 */
475static void cond_unmask_irq(struct irq_desc *desc)
476{
477 /*
478 * We need to unmask in the following cases:
479 * - Standard level irq (IRQF_ONESHOT is not set)
480 * - Oneshot irq which did not wake the thread (caused by a
481 * spurious interrupt or a primary handler handling it
482 * completely).
483 */
484 if (!irqd_irq_disabled(&desc->irq_data) &&
485 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
486 unmask_irq(desc);
487}
488
dd87eb3a
TG
489/**
490 * handle_level_irq - Level type irq handler
dd87eb3a 491 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
492 *
493 * Level type interrupts are active as long as the hardware line has
494 * the active level. This may require to mask the interrupt and unmask
495 * it after the associated handler has acknowledged the device, so the
496 * interrupt line is back to inactive.
497 */
bd0b9ac4 498void handle_level_irq(struct irq_desc *desc)
dd87eb3a 499{
239007b8 500 raw_spin_lock(&desc->lock);
9205e31d 501 mask_ack_irq(desc);
dd87eb3a 502
c7bd3ec0
TG
503 if (!irq_may_run(desc))
504 goto out_unlock;
fe200ae4 505
163ef309 506 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
507
508 /*
509 * If its disabled or no action available
510 * keep it masked and get out of here
511 */
d4dc0f90
TG
512 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
513 desc->istate |= IRQS_PENDING;
86998aa6 514 goto out_unlock;
d4dc0f90 515 }
dd87eb3a 516
a946e8c7 517 kstat_incr_irqs_this_cpu(desc);
1529866c 518 handle_irq_event(desc);
b25c340c 519
ac563761
TG
520 cond_unmask_irq(desc);
521
86998aa6 522out_unlock:
239007b8 523 raw_spin_unlock(&desc->lock);
dd87eb3a 524}
14819ea1 525EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a 526
78129576
TG
527#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
528static inline void preflow_handler(struct irq_desc *desc)
529{
530 if (desc->preflow_handler)
531 desc->preflow_handler(&desc->irq_data);
532}
533#else
534static inline void preflow_handler(struct irq_desc *desc) { }
535#endif
536
328a4978
TG
537static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
538{
539 if (!(desc->istate & IRQS_ONESHOT)) {
540 chip->irq_eoi(&desc->irq_data);
541 return;
542 }
543 /*
544 * We need to unmask in the following cases:
545 * - Oneshot irq which did not wake the thread (caused by a
546 * spurious interrupt or a primary handler handling it
547 * completely).
548 */
549 if (!irqd_irq_disabled(&desc->irq_data) &&
550 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
551 chip->irq_eoi(&desc->irq_data);
552 unmask_irq(desc);
553 } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
554 chip->irq_eoi(&desc->irq_data);
555 }
556}
557
dd87eb3a 558/**
47c2a3aa 559 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a 560 * @desc: the interrupt description structure for this irq
dd87eb3a 561 *
47c2a3aa 562 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
563 * call when the interrupt has been serviced. This enables support
564 * for modern forms of interrupt handlers, which handle the flow
565 * details in hardware, transparently.
566 */
bd0b9ac4 567void handle_fasteoi_irq(struct irq_desc *desc)
dd87eb3a 568{
328a4978
TG
569 struct irq_chip *chip = desc->irq_data.chip;
570
239007b8 571 raw_spin_lock(&desc->lock);
dd87eb3a 572
c7bd3ec0
TG
573 if (!irq_may_run(desc))
574 goto out;
dd87eb3a 575
163ef309 576 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
577
578 /*
579 * If its disabled or no action available
76d21601 580 * then mask it and get out of here:
dd87eb3a 581 */
32f4125e 582 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
2a0d6fb3 583 desc->istate |= IRQS_PENDING;
e2c0f8ff 584 mask_irq(desc);
dd87eb3a 585 goto out;
98bb244b 586 }
c69e3758 587
a946e8c7 588 kstat_incr_irqs_this_cpu(desc);
c69e3758
TG
589 if (desc->istate & IRQS_ONESHOT)
590 mask_irq(desc);
591
78129576 592 preflow_handler(desc);
a7ae4de5 593 handle_irq_event(desc);
77694b40 594
328a4978 595 cond_unmask_eoi_irq(desc, chip);
ac563761 596
239007b8 597 raw_spin_unlock(&desc->lock);
77694b40
TG
598 return;
599out:
328a4978
TG
600 if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
601 chip->irq_eoi(&desc->irq_data);
602 raw_spin_unlock(&desc->lock);
dd87eb3a 603}
7cad45ee 604EXPORT_SYMBOL_GPL(handle_fasteoi_irq);
dd87eb3a
TG
605
606/**
607 * handle_edge_irq - edge type IRQ handler
dd87eb3a 608 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
609 *
610 * Interrupt occures on the falling and/or rising edge of a hardware
25985edc 611 * signal. The occurrence is latched into the irq controller hardware
dd87eb3a
TG
612 * and must be acked in order to be reenabled. After the ack another
613 * interrupt can happen on the same source even before the first one
dfff0615 614 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
615 * might be necessary to disable (mask) the interrupt depending on the
616 * controller hardware. This requires to reenable the interrupt inside
617 * of the loop which handles the interrupts which have arrived while
618 * the handler was running. If all pending interrupts are handled, the
619 * loop is left.
620 */
bd0b9ac4 621void handle_edge_irq(struct irq_desc *desc)
dd87eb3a 622{
239007b8 623 raw_spin_lock(&desc->lock);
dd87eb3a 624
163ef309 625 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
c3d7acd0 626
c7bd3ec0
TG
627 if (!irq_may_run(desc)) {
628 desc->istate |= IRQS_PENDING;
629 mask_ack_irq(desc);
630 goto out_unlock;
dd87eb3a 631 }
c3d7acd0 632
dd87eb3a 633 /*
c3d7acd0
TG
634 * If its disabled or no action available then mask it and get
635 * out of here.
dd87eb3a 636 */
c3d7acd0
TG
637 if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
638 desc->istate |= IRQS_PENDING;
639 mask_ack_irq(desc);
640 goto out_unlock;
dd87eb3a 641 }
c3d7acd0 642
b51bf95c 643 kstat_incr_irqs_this_cpu(desc);
dd87eb3a
TG
644
645 /* Start handling the irq */
22a49163 646 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 647
dd87eb3a 648 do {
a60a5dc2 649 if (unlikely(!desc->action)) {
e2c0f8ff 650 mask_irq(desc);
dd87eb3a
TG
651 goto out_unlock;
652 }
653
654 /*
655 * When another irq arrived while we were handling
656 * one, we could have masked the irq.
657 * Renable it, if it was not disabled in meantime.
658 */
2a0d6fb3 659 if (unlikely(desc->istate & IRQS_PENDING)) {
32f4125e
TG
660 if (!irqd_irq_disabled(&desc->irq_data) &&
661 irqd_irq_masked(&desc->irq_data))
c1594b77 662 unmask_irq(desc);
dd87eb3a
TG
663 }
664
a60a5dc2 665 handle_irq_event(desc);
dd87eb3a 666
2a0d6fb3 667 } while ((desc->istate & IRQS_PENDING) &&
32f4125e 668 !irqd_irq_disabled(&desc->irq_data));
dd87eb3a 669
dd87eb3a 670out_unlock:
239007b8 671 raw_spin_unlock(&desc->lock);
dd87eb3a 672}
3911ff30 673EXPORT_SYMBOL(handle_edge_irq);
dd87eb3a 674
0521c8fb
TG
675#ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
676/**
677 * handle_edge_eoi_irq - edge eoi type IRQ handler
0521c8fb
TG
678 * @desc: the interrupt description structure for this irq
679 *
680 * Similar as the above handle_edge_irq, but using eoi and w/o the
681 * mask/unmask logic.
682 */
bd0b9ac4 683void handle_edge_eoi_irq(struct irq_desc *desc)
0521c8fb
TG
684{
685 struct irq_chip *chip = irq_desc_get_chip(desc);
686
687 raw_spin_lock(&desc->lock);
688
689 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
c3d7acd0 690
c7bd3ec0
TG
691 if (!irq_may_run(desc)) {
692 desc->istate |= IRQS_PENDING;
693 goto out_eoi;
0521c8fb 694 }
c3d7acd0 695
0521c8fb 696 /*
c3d7acd0
TG
697 * If its disabled or no action available then mask it and get
698 * out of here.
0521c8fb 699 */
c3d7acd0
TG
700 if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
701 desc->istate |= IRQS_PENDING;
702 goto out_eoi;
0521c8fb 703 }
c3d7acd0 704
b51bf95c 705 kstat_incr_irqs_this_cpu(desc);
0521c8fb
TG
706
707 do {
708 if (unlikely(!desc->action))
709 goto out_eoi;
710
711 handle_irq_event(desc);
712
713 } while ((desc->istate & IRQS_PENDING) &&
714 !irqd_irq_disabled(&desc->irq_data));
715
ac0e0447 716out_eoi:
0521c8fb
TG
717 chip->irq_eoi(&desc->irq_data);
718 raw_spin_unlock(&desc->lock);
719}
720#endif
721
dd87eb3a 722/**
24b26d42 723 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a 724 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
725 *
726 * Per CPU interrupts on SMP machines without locking requirements
727 */
bd0b9ac4 728void handle_percpu_irq(struct irq_desc *desc)
dd87eb3a 729{
35e857cb 730 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 731
b51bf95c 732 kstat_incr_irqs_this_cpu(desc);
dd87eb3a 733
849f061c
TG
734 if (chip->irq_ack)
735 chip->irq_ack(&desc->irq_data);
dd87eb3a 736
71f64340 737 handle_irq_event_percpu(desc);
dd87eb3a 738
849f061c
TG
739 if (chip->irq_eoi)
740 chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
741}
742
31d9d9b6
MZ
743/**
744 * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
31d9d9b6
MZ
745 * @desc: the interrupt description structure for this irq
746 *
747 * Per CPU interrupts on SMP machines without locking requirements. Same as
748 * handle_percpu_irq() above but with the following extras:
749 *
750 * action->percpu_dev_id is a pointer to percpu variables which
751 * contain the real device id for the cpu on which this handler is
752 * called
753 */
bd0b9ac4 754void handle_percpu_devid_irq(struct irq_desc *desc)
31d9d9b6
MZ
755{
756 struct irq_chip *chip = irq_desc_get_chip(desc);
757 struct irqaction *action = desc->action;
bd0b9ac4 758 unsigned int irq = irq_desc_get_irq(desc);
31d9d9b6
MZ
759 irqreturn_t res;
760
b51bf95c 761 kstat_incr_irqs_this_cpu(desc);
31d9d9b6
MZ
762
763 if (chip->irq_ack)
764 chip->irq_ack(&desc->irq_data);
765
fc590c22
TG
766 if (likely(action)) {
767 trace_irq_handler_entry(irq, action);
768 res = action->handler(irq, raw_cpu_ptr(action->percpu_dev_id));
769 trace_irq_handler_exit(irq, action, res);
770 } else {
771 unsigned int cpu = smp_processor_id();
772 bool enabled = cpumask_test_cpu(cpu, desc->percpu_enabled);
773
774 if (enabled)
775 irq_percpu_disable(desc, cpu);
776
777 pr_err_once("Spurious%s percpu IRQ%u on CPU%u\n",
778 enabled ? " and unmasked" : "", irq, cpu);
779 }
31d9d9b6
MZ
780
781 if (chip->irq_eoi)
782 chip->irq_eoi(&desc->irq_data);
783}
784
dd87eb3a 785void
3b0f95be
RK
786__irq_do_set_handler(struct irq_desc *desc, irq_flow_handler_t handle,
787 int is_chained, const char *name)
dd87eb3a 788{
091738a2 789 if (!handle) {
dd87eb3a 790 handle = handle_bad_irq;
091738a2 791 } else {
f86eff22
MZ
792 struct irq_data *irq_data = &desc->irq_data;
793#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
794 /*
795 * With hierarchical domains we might run into a
796 * situation where the outermost chip is not yet set
797 * up, but the inner chips are there. Instead of
798 * bailing we install the handler, but obviously we
799 * cannot enable/startup the interrupt at this point.
800 */
801 while (irq_data) {
802 if (irq_data->chip != &no_irq_chip)
803 break;
804 /*
805 * Bail out if the outer chip is not set up
806 * and the interrrupt supposed to be started
807 * right away.
808 */
809 if (WARN_ON(is_chained))
3b0f95be 810 return;
f86eff22
MZ
811 /* Try the parent */
812 irq_data = irq_data->parent_data;
813 }
814#endif
815 if (WARN_ON(!irq_data || irq_data->chip == &no_irq_chip))
3b0f95be 816 return;
f8b5473f 817 }
dd87eb3a 818
dd87eb3a
TG
819 /* Uninstall? */
820 if (handle == handle_bad_irq) {
6b8ff312 821 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 822 mask_ack_irq(desc);
801a0e9a 823 irq_state_set_disabled(desc);
e509bd7d
MW
824 if (is_chained)
825 desc->action = NULL;
dd87eb3a
TG
826 desc->depth = 1;
827 }
828 desc->handle_irq = handle;
a460e745 829 desc->name = name;
dd87eb3a
TG
830
831 if (handle != handle_bad_irq && is_chained) {
1e12c4a9
MZ
832 /*
833 * We're about to start this interrupt immediately,
834 * hence the need to set the trigger configuration.
835 * But the .set_type callback may have overridden the
836 * flow handler, ignoring that we're dealing with a
837 * chained interrupt. Reset it immediately because we
838 * do know better.
839 */
840 __irq_set_trigger(desc, irqd_get_trigger_type(&desc->irq_data));
841 desc->handle_irq = handle;
842
1ccb4e61
TG
843 irq_settings_set_noprobe(desc);
844 irq_settings_set_norequest(desc);
7f1b1244 845 irq_settings_set_nothread(desc);
e509bd7d 846 desc->action = &chained_action;
b4bc724e 847 irq_startup(desc, true);
dd87eb3a 848 }
3b0f95be
RK
849}
850
851void
852__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
853 const char *name)
854{
855 unsigned long flags;
856 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
857
858 if (!desc)
859 return;
860
861 __irq_do_set_handler(desc, handle, is_chained, name);
02725e74 862 irq_put_desc_busunlock(desc, flags);
dd87eb3a 863}
3836ca08 864EXPORT_SYMBOL_GPL(__irq_set_handler);
dd87eb3a 865
3b0f95be
RK
866void
867irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
868 void *data)
869{
870 unsigned long flags;
871 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
872
873 if (!desc)
874 return;
875
876 __irq_do_set_handler(desc, handle, 1, NULL);
af7080e0 877 desc->irq_common_data.handler_data = data;
3b0f95be
RK
878
879 irq_put_desc_busunlock(desc, flags);
880}
881EXPORT_SYMBOL_GPL(irq_set_chained_handler_and_data);
882
dd87eb3a 883void
3836ca08 884irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
a460e745 885 irq_flow_handler_t handle, const char *name)
dd87eb3a 886{
35e857cb 887 irq_set_chip(irq, chip);
3836ca08 888 __irq_set_handler(irq, handle, 0, name);
dd87eb3a 889}
b3ae66f2 890EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
46f4f8f6 891
44247184 892void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 893{
46f4f8f6 894 unsigned long flags;
31d9d9b6 895 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
46f4f8f6 896
44247184 897 if (!desc)
46f4f8f6 898 return;
a005677b
TG
899 irq_settings_clr_and_set(desc, clr, set);
900
876dbd4c 901 irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
e1ef8241 902 IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
a005677b
TG
903 if (irq_settings_has_no_balance_set(desc))
904 irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
905 if (irq_settings_is_per_cpu(desc))
906 irqd_set(&desc->irq_data, IRQD_PER_CPU);
e1ef8241
TG
907 if (irq_settings_can_move_pcntxt(desc))
908 irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
0ef5ca1e
TG
909 if (irq_settings_is_level(desc))
910 irqd_set(&desc->irq_data, IRQD_LEVEL);
a005677b 911
876dbd4c
TG
912 irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc));
913
02725e74 914 irq_put_desc_unlock(desc, flags);
46f4f8f6 915}
edf76f83 916EXPORT_SYMBOL_GPL(irq_modify_status);
0fdb4b25
DD
917
918/**
919 * irq_cpu_online - Invoke all irq_cpu_online functions.
920 *
921 * Iterate through all irqs and invoke the chip.irq_cpu_online()
922 * for each.
923 */
924void irq_cpu_online(void)
925{
926 struct irq_desc *desc;
927 struct irq_chip *chip;
928 unsigned long flags;
929 unsigned int irq;
930
931 for_each_active_irq(irq) {
932 desc = irq_to_desc(irq);
933 if (!desc)
934 continue;
935
936 raw_spin_lock_irqsave(&desc->lock, flags);
937
938 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
939 if (chip && chip->irq_cpu_online &&
940 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 941 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
942 chip->irq_cpu_online(&desc->irq_data);
943
944 raw_spin_unlock_irqrestore(&desc->lock, flags);
945 }
946}
947
948/**
949 * irq_cpu_offline - Invoke all irq_cpu_offline functions.
950 *
951 * Iterate through all irqs and invoke the chip.irq_cpu_offline()
952 * for each.
953 */
954void irq_cpu_offline(void)
955{
956 struct irq_desc *desc;
957 struct irq_chip *chip;
958 unsigned long flags;
959 unsigned int irq;
960
961 for_each_active_irq(irq) {
962 desc = irq_to_desc(irq);
963 if (!desc)
964 continue;
965
966 raw_spin_lock_irqsave(&desc->lock, flags);
967
968 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
969 if (chip && chip->irq_cpu_offline &&
970 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 971 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
972 chip->irq_cpu_offline(&desc->irq_data);
973
974 raw_spin_unlock_irqrestore(&desc->lock, flags);
975 }
976}
85f08c17
JL
977
978#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
3cfeffc2
SA
979/**
980 * irq_chip_enable_parent - Enable the parent interrupt (defaults to unmask if
981 * NULL)
982 * @data: Pointer to interrupt specific data
983 */
984void irq_chip_enable_parent(struct irq_data *data)
985{
986 data = data->parent_data;
987 if (data->chip->irq_enable)
988 data->chip->irq_enable(data);
989 else
990 data->chip->irq_unmask(data);
991}
992
993/**
994 * irq_chip_disable_parent - Disable the parent interrupt (defaults to mask if
995 * NULL)
996 * @data: Pointer to interrupt specific data
997 */
998void irq_chip_disable_parent(struct irq_data *data)
999{
1000 data = data->parent_data;
1001 if (data->chip->irq_disable)
1002 data->chip->irq_disable(data);
1003 else
1004 data->chip->irq_mask(data);
1005}
1006
85f08c17
JL
1007/**
1008 * irq_chip_ack_parent - Acknowledge the parent interrupt
1009 * @data: Pointer to interrupt specific data
1010 */
1011void irq_chip_ack_parent(struct irq_data *data)
1012{
1013 data = data->parent_data;
1014 data->chip->irq_ack(data);
1015}
a4289dc2 1016EXPORT_SYMBOL_GPL(irq_chip_ack_parent);
85f08c17 1017
56e8abab
YC
1018/**
1019 * irq_chip_mask_parent - Mask the parent interrupt
1020 * @data: Pointer to interrupt specific data
1021 */
1022void irq_chip_mask_parent(struct irq_data *data)
1023{
1024 data = data->parent_data;
1025 data->chip->irq_mask(data);
1026}
52b2a05f 1027EXPORT_SYMBOL_GPL(irq_chip_mask_parent);
56e8abab
YC
1028
1029/**
1030 * irq_chip_unmask_parent - Unmask the parent interrupt
1031 * @data: Pointer to interrupt specific data
1032 */
1033void irq_chip_unmask_parent(struct irq_data *data)
1034{
1035 data = data->parent_data;
1036 data->chip->irq_unmask(data);
1037}
52b2a05f 1038EXPORT_SYMBOL_GPL(irq_chip_unmask_parent);
56e8abab
YC
1039
1040/**
1041 * irq_chip_eoi_parent - Invoke EOI on the parent interrupt
1042 * @data: Pointer to interrupt specific data
1043 */
1044void irq_chip_eoi_parent(struct irq_data *data)
1045{
1046 data = data->parent_data;
1047 data->chip->irq_eoi(data);
1048}
52b2a05f 1049EXPORT_SYMBOL_GPL(irq_chip_eoi_parent);
56e8abab
YC
1050
1051/**
1052 * irq_chip_set_affinity_parent - Set affinity on the parent interrupt
1053 * @data: Pointer to interrupt specific data
1054 * @dest: The affinity mask to set
1055 * @force: Flag to enforce setting (disable online checks)
1056 *
1057 * Conditinal, as the underlying parent chip might not implement it.
1058 */
1059int irq_chip_set_affinity_parent(struct irq_data *data,
1060 const struct cpumask *dest, bool force)
1061{
1062 data = data->parent_data;
1063 if (data->chip->irq_set_affinity)
1064 return data->chip->irq_set_affinity(data, dest, force);
b7560de1
GS
1065
1066 return -ENOSYS;
1067}
1068
1069/**
1070 * irq_chip_set_type_parent - Set IRQ type on the parent interrupt
1071 * @data: Pointer to interrupt specific data
1072 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
1073 *
1074 * Conditional, as the underlying parent chip might not implement it.
1075 */
1076int irq_chip_set_type_parent(struct irq_data *data, unsigned int type)
1077{
1078 data = data->parent_data;
1079
1080 if (data->chip->irq_set_type)
1081 return data->chip->irq_set_type(data, type);
56e8abab
YC
1082
1083 return -ENOSYS;
1084}
52b2a05f 1085EXPORT_SYMBOL_GPL(irq_chip_set_type_parent);
56e8abab 1086
85f08c17
JL
1087/**
1088 * irq_chip_retrigger_hierarchy - Retrigger an interrupt in hardware
1089 * @data: Pointer to interrupt specific data
1090 *
1091 * Iterate through the domain hierarchy of the interrupt and check
1092 * whether a hw retrigger function exists. If yes, invoke it.
1093 */
1094int irq_chip_retrigger_hierarchy(struct irq_data *data)
1095{
1096 for (data = data->parent_data; data; data = data->parent_data)
1097 if (data->chip && data->chip->irq_retrigger)
1098 return data->chip->irq_retrigger(data);
1099
6d4affea 1100 return 0;
85f08c17 1101}
08b55e2a 1102
0a4377de
JL
1103/**
1104 * irq_chip_set_vcpu_affinity_parent - Set vcpu affinity on the parent interrupt
1105 * @data: Pointer to interrupt specific data
8505a81b 1106 * @vcpu_info: The vcpu affinity information
0a4377de
JL
1107 */
1108int irq_chip_set_vcpu_affinity_parent(struct irq_data *data, void *vcpu_info)
1109{
1110 data = data->parent_data;
1111 if (data->chip->irq_set_vcpu_affinity)
1112 return data->chip->irq_set_vcpu_affinity(data, vcpu_info);
1113
1114 return -ENOSYS;
1115}
1116
08b55e2a
MZ
1117/**
1118 * irq_chip_set_wake_parent - Set/reset wake-up on the parent interrupt
1119 * @data: Pointer to interrupt specific data
1120 * @on: Whether to set or reset the wake-up capability of this irq
1121 *
1122 * Conditional, as the underlying parent chip might not implement it.
1123 */
1124int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on)
1125{
1126 data = data->parent_data;
1127 if (data->chip->irq_set_wake)
1128 return data->chip->irq_set_wake(data, on);
1129
1130 return -ENOSYS;
1131}
85f08c17 1132#endif
515085ef
JL
1133
1134/**
1135 * irq_chip_compose_msi_msg - Componse msi message for a irq chip
1136 * @data: Pointer to interrupt specific data
1137 * @msg: Pointer to the MSI message
1138 *
1139 * For hierarchical domains we find the first chip in the hierarchy
1140 * which implements the irq_compose_msi_msg callback. For non
1141 * hierarchical we use the top level chip.
1142 */
1143int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
1144{
1145 struct irq_data *pos = NULL;
1146
1147#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
1148 for (; data; data = data->parent_data)
1149#endif
1150 if (data->chip && data->chip->irq_compose_msi_msg)
1151 pos = data;
1152 if (!pos)
1153 return -ENOSYS;
1154
1155 pos->chip->irq_compose_msi_msg(pos, msg);
1156
1157 return 0;
1158}
be45beb2
JH
1159
1160/**
1161 * irq_chip_pm_get - Enable power for an IRQ chip
1162 * @data: Pointer to interrupt specific data
1163 *
1164 * Enable the power to the IRQ chip referenced by the interrupt data
1165 * structure.
1166 */
1167int irq_chip_pm_get(struct irq_data *data)
1168{
1169 int retval;
1170
1171 if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device) {
1172 retval = pm_runtime_get_sync(data->chip->parent_device);
1173 if (retval < 0) {
1174 pm_runtime_put_noidle(data->chip->parent_device);
1175 return retval;
1176 }
1177 }
1178
1179 return 0;
1180}
1181
1182/**
1183 * irq_chip_pm_put - Disable power for an IRQ chip
1184 * @data: Pointer to interrupt specific data
1185 *
1186 * Disable the power to the IRQ chip referenced by the interrupt data
1187 * structure, belongs. Note that power will only be disabled, once this
1188 * function has been called for all IRQs that have called irq_chip_pm_get().
1189 */
1190int irq_chip_pm_put(struct irq_data *data)
1191{
1192 int retval = 0;
1193
1194 if (IS_ENABLED(CONFIG_PM) && data->chip->parent_device)
1195 retval = pm_runtime_put(data->chip->parent_device);
1196
1197 return (retval < 0) ? retval : 0;
1198}
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