Commit | Line | Data |
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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
7fe3730d | 14 | #include <linux/msi.h> |
dd87eb3a TG |
15 | #include <linux/module.h> |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | ||
19 | #include "internals.h" | |
20 | ||
3a16d713 EB |
21 | /** |
22 | * dynamic_irq_init - initialize a dynamically allocated irq | |
23 | * @irq: irq number to initialize | |
24 | */ | |
25 | void dynamic_irq_init(unsigned int irq) | |
26 | { | |
27 | struct irq_desc *desc; | |
28 | unsigned long flags; | |
29 | ||
cb5bc832 YL |
30 | /* first time to use this irq_desc */ |
31 | desc = irq_to_desc_alloc(irq); | |
7d94f7ca | 32 | if (!desc) { |
261c40c1 | 33 | WARN(1, KERN_ERR "Trying to initialize invalid IRQ%d\n", irq); |
3a16d713 EB |
34 | return; |
35 | } | |
36 | ||
37 | /* Ensure we don't have left over values from a previous use of this irq */ | |
3a16d713 EB |
38 | spin_lock_irqsave(&desc->lock, flags); |
39 | desc->status = IRQ_DISABLED; | |
40 | desc->chip = &no_irq_chip; | |
41 | desc->handle_irq = handle_bad_irq; | |
42 | desc->depth = 1; | |
5b912c10 | 43 | desc->msi_desc = NULL; |
3a16d713 EB |
44 | desc->handler_data = NULL; |
45 | desc->chip_data = NULL; | |
46 | desc->action = NULL; | |
47 | desc->irq_count = 0; | |
48 | desc->irqs_unhandled = 0; | |
49 | #ifdef CONFIG_SMP | |
d366f8cb | 50 | cpus_setall(desc->affinity); |
3a16d713 EB |
51 | #endif |
52 | spin_unlock_irqrestore(&desc->lock, flags); | |
53 | } | |
54 | ||
55 | /** | |
56 | * dynamic_irq_cleanup - cleanup a dynamically allocated irq | |
57 | * @irq: irq number to initialize | |
58 | */ | |
59 | void dynamic_irq_cleanup(unsigned int irq) | |
60 | { | |
61 | struct irq_desc *desc; | |
62 | unsigned long flags; | |
63 | ||
cb5bc832 | 64 | desc = irq_to_desc(irq); |
7d94f7ca | 65 | if (!desc) { |
261c40c1 | 66 | WARN(1, KERN_ERR "Trying to cleanup invalid IRQ%d\n", irq); |
3a16d713 EB |
67 | return; |
68 | } | |
69 | ||
3a16d713 | 70 | spin_lock_irqsave(&desc->lock, flags); |
1f80025e EB |
71 | if (desc->action) { |
72 | spin_unlock_irqrestore(&desc->lock, flags); | |
261c40c1 | 73 | WARN(1, KERN_ERR "Destroying IRQ%d without calling free_irq\n", |
1f80025e | 74 | irq); |
1f80025e EB |
75 | return; |
76 | } | |
5b912c10 EB |
77 | desc->msi_desc = NULL; |
78 | desc->handler_data = NULL; | |
79 | desc->chip_data = NULL; | |
3a16d713 EB |
80 | desc->handle_irq = handle_bad_irq; |
81 | desc->chip = &no_irq_chip; | |
82 | spin_unlock_irqrestore(&desc->lock, flags); | |
83 | } | |
84 | ||
85 | ||
dd87eb3a TG |
86 | /** |
87 | * set_irq_chip - set the irq chip for an irq | |
88 | * @irq: irq number | |
89 | * @chip: pointer to irq chip description structure | |
90 | */ | |
91 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) | |
92 | { | |
93 | struct irq_desc *desc; | |
94 | unsigned long flags; | |
95 | ||
cb5bc832 | 96 | desc = irq_to_desc(irq); |
7d94f7ca | 97 | if (!desc) { |
261c40c1 | 98 | WARN(1, KERN_ERR "Trying to install chip for IRQ%d\n", irq); |
dd87eb3a TG |
99 | return -EINVAL; |
100 | } | |
101 | ||
102 | if (!chip) | |
103 | chip = &no_irq_chip; | |
104 | ||
08678b08 | 105 | desc = irq_to_desc(irq); |
dd87eb3a TG |
106 | spin_lock_irqsave(&desc->lock, flags); |
107 | irq_chip_set_defaults(chip); | |
108 | desc->chip = chip; | |
dd87eb3a TG |
109 | spin_unlock_irqrestore(&desc->lock, flags); |
110 | ||
111 | return 0; | |
112 | } | |
113 | EXPORT_SYMBOL(set_irq_chip); | |
114 | ||
115 | /** | |
0c5d1eb7 | 116 | * set_irq_type - set the irq trigger type for an irq |
dd87eb3a | 117 | * @irq: irq number |
0c5d1eb7 | 118 | * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h |
dd87eb3a TG |
119 | */ |
120 | int set_irq_type(unsigned int irq, unsigned int type) | |
121 | { | |
122 | struct irq_desc *desc; | |
123 | unsigned long flags; | |
124 | int ret = -ENXIO; | |
125 | ||
cb5bc832 | 126 | desc = irq_to_desc(irq); |
7d94f7ca | 127 | if (!desc) { |
dd87eb3a TG |
128 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); |
129 | return -ENODEV; | |
130 | } | |
131 | ||
0c5d1eb7 DB |
132 | if (type == IRQ_TYPE_NONE) |
133 | return 0; | |
134 | ||
135 | spin_lock_irqsave(&desc->lock, flags); | |
136 | ret = __irq_set_trigger(desc, irq, flags); | |
137 | spin_unlock_irqrestore(&desc->lock, flags); | |
dd87eb3a TG |
138 | return ret; |
139 | } | |
140 | EXPORT_SYMBOL(set_irq_type); | |
141 | ||
142 | /** | |
143 | * set_irq_data - set irq type data for an irq | |
144 | * @irq: Interrupt number | |
145 | * @data: Pointer to interrupt specific data | |
146 | * | |
147 | * Set the hardware irq controller data for an irq | |
148 | */ | |
149 | int set_irq_data(unsigned int irq, void *data) | |
150 | { | |
151 | struct irq_desc *desc; | |
152 | unsigned long flags; | |
153 | ||
cb5bc832 | 154 | desc = irq_to_desc(irq); |
7d94f7ca | 155 | if (!desc) { |
dd87eb3a TG |
156 | printk(KERN_ERR |
157 | "Trying to install controller data for IRQ%d\n", irq); | |
158 | return -EINVAL; | |
159 | } | |
160 | ||
dd87eb3a TG |
161 | spin_lock_irqsave(&desc->lock, flags); |
162 | desc->handler_data = data; | |
163 | spin_unlock_irqrestore(&desc->lock, flags); | |
164 | return 0; | |
165 | } | |
166 | EXPORT_SYMBOL(set_irq_data); | |
167 | ||
5b912c10 EB |
168 | /** |
169 | * set_irq_data - set irq type data for an irq | |
170 | * @irq: Interrupt number | |
472900b8 | 171 | * @entry: Pointer to MSI descriptor data |
5b912c10 EB |
172 | * |
173 | * Set the hardware irq controller data for an irq | |
174 | */ | |
175 | int set_irq_msi(unsigned int irq, struct msi_desc *entry) | |
176 | { | |
177 | struct irq_desc *desc; | |
178 | unsigned long flags; | |
179 | ||
cb5bc832 | 180 | desc = irq_to_desc(irq); |
7d94f7ca | 181 | if (!desc) { |
5b912c10 EB |
182 | printk(KERN_ERR |
183 | "Trying to install msi data for IRQ%d\n", irq); | |
184 | return -EINVAL; | |
185 | } | |
7d94f7ca | 186 | |
5b912c10 EB |
187 | spin_lock_irqsave(&desc->lock, flags); |
188 | desc->msi_desc = entry; | |
7fe3730d ME |
189 | if (entry) |
190 | entry->irq = irq; | |
5b912c10 EB |
191 | spin_unlock_irqrestore(&desc->lock, flags); |
192 | return 0; | |
193 | } | |
194 | ||
dd87eb3a TG |
195 | /** |
196 | * set_irq_chip_data - set irq chip data for an irq | |
197 | * @irq: Interrupt number | |
198 | * @data: Pointer to chip specific data | |
199 | * | |
200 | * Set the hardware irq chip data for an irq | |
201 | */ | |
202 | int set_irq_chip_data(unsigned int irq, void *data) | |
203 | { | |
08678b08 | 204 | struct irq_desc *desc; |
dd87eb3a TG |
205 | unsigned long flags; |
206 | ||
cb5bc832 | 207 | desc = irq_to_desc(irq); |
7d94f7ca YL |
208 | if (!desc) { |
209 | printk(KERN_ERR | |
210 | "Trying to install chip data for IRQ%d\n", irq); | |
211 | return -EINVAL; | |
212 | } | |
213 | ||
214 | if (!desc->chip) { | |
dd87eb3a TG |
215 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); |
216 | return -EINVAL; | |
217 | } | |
218 | ||
219 | spin_lock_irqsave(&desc->lock, flags); | |
220 | desc->chip_data = data; | |
221 | spin_unlock_irqrestore(&desc->lock, flags); | |
222 | ||
223 | return 0; | |
224 | } | |
225 | EXPORT_SYMBOL(set_irq_chip_data); | |
226 | ||
227 | /* | |
228 | * default enable function | |
229 | */ | |
230 | static void default_enable(unsigned int irq) | |
231 | { | |
08678b08 | 232 | struct irq_desc *desc; |
dd87eb3a | 233 | |
08678b08 | 234 | desc = irq_to_desc(irq); |
dd87eb3a TG |
235 | desc->chip->unmask(irq); |
236 | desc->status &= ~IRQ_MASKED; | |
237 | } | |
238 | ||
239 | /* | |
240 | * default disable function | |
241 | */ | |
242 | static void default_disable(unsigned int irq) | |
243 | { | |
dd87eb3a TG |
244 | } |
245 | ||
246 | /* | |
247 | * default startup function | |
248 | */ | |
249 | static unsigned int default_startup(unsigned int irq) | |
250 | { | |
08678b08 YL |
251 | struct irq_desc *desc; |
252 | ||
253 | desc = irq_to_desc(irq); | |
254 | desc->chip->enable(irq); | |
dd87eb3a TG |
255 | |
256 | return 0; | |
257 | } | |
258 | ||
89d694b9 TG |
259 | /* |
260 | * default shutdown function | |
261 | */ | |
262 | static void default_shutdown(unsigned int irq) | |
263 | { | |
08678b08 | 264 | struct irq_desc *desc; |
89d694b9 | 265 | |
08678b08 | 266 | desc = irq_to_desc(irq); |
89d694b9 TG |
267 | desc->chip->mask(irq); |
268 | desc->status |= IRQ_MASKED; | |
269 | } | |
270 | ||
dd87eb3a TG |
271 | /* |
272 | * Fixup enable/disable function pointers | |
273 | */ | |
274 | void irq_chip_set_defaults(struct irq_chip *chip) | |
275 | { | |
276 | if (!chip->enable) | |
277 | chip->enable = default_enable; | |
278 | if (!chip->disable) | |
279 | chip->disable = default_disable; | |
280 | if (!chip->startup) | |
281 | chip->startup = default_startup; | |
89d694b9 TG |
282 | /* |
283 | * We use chip->disable, when the user provided its own. When | |
284 | * we have default_disable set for chip->disable, then we need | |
285 | * to use default_shutdown, otherwise the irq line is not | |
286 | * disabled on free_irq(): | |
287 | */ | |
dd87eb3a | 288 | if (!chip->shutdown) |
89d694b9 TG |
289 | chip->shutdown = chip->disable != default_disable ? |
290 | chip->disable : default_shutdown; | |
dd87eb3a TG |
291 | if (!chip->name) |
292 | chip->name = chip->typename; | |
b86432b4 ZY |
293 | if (!chip->end) |
294 | chip->end = dummy_irq_chip.end; | |
dd87eb3a TG |
295 | } |
296 | ||
297 | static inline void mask_ack_irq(struct irq_desc *desc, int irq) | |
298 | { | |
299 | if (desc->chip->mask_ack) | |
300 | desc->chip->mask_ack(irq); | |
301 | else { | |
302 | desc->chip->mask(irq); | |
303 | desc->chip->ack(irq); | |
304 | } | |
305 | } | |
306 | ||
307 | /** | |
308 | * handle_simple_irq - Simple and software-decoded IRQs. | |
309 | * @irq: the interrupt number | |
310 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
311 | * |
312 | * Simple interrupts are either sent from a demultiplexing interrupt | |
313 | * handler or come from hardware, where no interrupt hardware control | |
314 | * is necessary. | |
315 | * | |
316 | * Note: The caller is expected to handle the ack, clear, mask and | |
317 | * unmask issues if necessary. | |
318 | */ | |
7ad5b3a5 | 319 | void |
7d12e780 | 320 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
321 | { |
322 | struct irqaction *action; | |
323 | irqreturn_t action_ret; | |
dd87eb3a TG |
324 | |
325 | spin_lock(&desc->lock); | |
326 | ||
327 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
328 | goto out_unlock; | |
971e5b35 | 329 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
7f95ec9e | 330 | kstat_irqs_this_cpu(desc)++; |
dd87eb3a TG |
331 | |
332 | action = desc->action; | |
971e5b35 | 333 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
dd87eb3a TG |
334 | goto out_unlock; |
335 | ||
336 | desc->status |= IRQ_INPROGRESS; | |
337 | spin_unlock(&desc->lock); | |
338 | ||
7d12e780 | 339 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 340 | if (!noirqdebug) |
7d12e780 | 341 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
342 | |
343 | spin_lock(&desc->lock); | |
344 | desc->status &= ~IRQ_INPROGRESS; | |
345 | out_unlock: | |
346 | spin_unlock(&desc->lock); | |
347 | } | |
348 | ||
349 | /** | |
350 | * handle_level_irq - Level type irq handler | |
351 | * @irq: the interrupt number | |
352 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
353 | * |
354 | * Level type interrupts are active as long as the hardware line has | |
355 | * the active level. This may require to mask the interrupt and unmask | |
356 | * it after the associated handler has acknowledged the device, so the | |
357 | * interrupt line is back to inactive. | |
358 | */ | |
7ad5b3a5 | 359 | void |
7d12e780 | 360 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 361 | { |
dd87eb3a TG |
362 | struct irqaction *action; |
363 | irqreturn_t action_ret; | |
364 | ||
365 | spin_lock(&desc->lock); | |
366 | mask_ack_irq(desc, irq); | |
367 | ||
368 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
86998aa6 | 369 | goto out_unlock; |
dd87eb3a | 370 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
7f95ec9e | 371 | kstat_irqs_this_cpu(desc)++; |
dd87eb3a TG |
372 | |
373 | /* | |
374 | * If its disabled or no action available | |
375 | * keep it masked and get out of here | |
376 | */ | |
377 | action = desc->action; | |
49663421 | 378 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) |
86998aa6 | 379 | goto out_unlock; |
dd87eb3a TG |
380 | |
381 | desc->status |= IRQ_INPROGRESS; | |
382 | spin_unlock(&desc->lock); | |
383 | ||
7d12e780 | 384 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 385 | if (!noirqdebug) |
7d12e780 | 386 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
387 | |
388 | spin_lock(&desc->lock); | |
389 | desc->status &= ~IRQ_INPROGRESS; | |
dd87eb3a TG |
390 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) |
391 | desc->chip->unmask(irq); | |
86998aa6 | 392 | out_unlock: |
dd87eb3a TG |
393 | spin_unlock(&desc->lock); |
394 | } | |
395 | ||
396 | /** | |
47c2a3aa | 397 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
398 | * @irq: the interrupt number |
399 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 400 | * |
47c2a3aa | 401 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
402 | * call when the interrupt has been serviced. This enables support |
403 | * for modern forms of interrupt handlers, which handle the flow | |
404 | * details in hardware, transparently. | |
405 | */ | |
7ad5b3a5 | 406 | void |
7d12e780 | 407 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 408 | { |
dd87eb3a TG |
409 | struct irqaction *action; |
410 | irqreturn_t action_ret; | |
411 | ||
412 | spin_lock(&desc->lock); | |
413 | ||
414 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
415 | goto out; | |
416 | ||
417 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
7f95ec9e | 418 | kstat_irqs_this_cpu(desc)++; |
dd87eb3a TG |
419 | |
420 | /* | |
421 | * If its disabled or no action available | |
76d21601 | 422 | * then mask it and get out of here: |
dd87eb3a TG |
423 | */ |
424 | action = desc->action; | |
98bb244b BH |
425 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
426 | desc->status |= IRQ_PENDING; | |
76d21601 IM |
427 | if (desc->chip->mask) |
428 | desc->chip->mask(irq); | |
dd87eb3a | 429 | goto out; |
98bb244b | 430 | } |
dd87eb3a TG |
431 | |
432 | desc->status |= IRQ_INPROGRESS; | |
98bb244b | 433 | desc->status &= ~IRQ_PENDING; |
dd87eb3a TG |
434 | spin_unlock(&desc->lock); |
435 | ||
7d12e780 | 436 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 437 | if (!noirqdebug) |
7d12e780 | 438 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
439 | |
440 | spin_lock(&desc->lock); | |
441 | desc->status &= ~IRQ_INPROGRESS; | |
442 | out: | |
47c2a3aa | 443 | desc->chip->eoi(irq); |
dd87eb3a TG |
444 | |
445 | spin_unlock(&desc->lock); | |
446 | } | |
447 | ||
448 | /** | |
449 | * handle_edge_irq - edge type IRQ handler | |
450 | * @irq: the interrupt number | |
451 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
452 | * |
453 | * Interrupt occures on the falling and/or rising edge of a hardware | |
454 | * signal. The occurence is latched into the irq controller hardware | |
455 | * and must be acked in order to be reenabled. After the ack another | |
456 | * interrupt can happen on the same source even before the first one | |
457 | * is handled by the assosiacted event handler. If this happens it | |
458 | * might be necessary to disable (mask) the interrupt depending on the | |
459 | * controller hardware. This requires to reenable the interrupt inside | |
460 | * of the loop which handles the interrupts which have arrived while | |
461 | * the handler was running. If all pending interrupts are handled, the | |
462 | * loop is left. | |
463 | */ | |
7ad5b3a5 | 464 | void |
7d12e780 | 465 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a | 466 | { |
dd87eb3a TG |
467 | spin_lock(&desc->lock); |
468 | ||
469 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
470 | ||
471 | /* | |
472 | * If we're currently running this IRQ, or its disabled, | |
473 | * we shouldn't process the IRQ. Mark it pending, handle | |
474 | * the necessary masking and go out | |
475 | */ | |
476 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | |
477 | !desc->action)) { | |
478 | desc->status |= (IRQ_PENDING | IRQ_MASKED); | |
479 | mask_ack_irq(desc, irq); | |
480 | goto out_unlock; | |
481 | } | |
482 | ||
7f95ec9e | 483 | kstat_irqs_this_cpu(desc)++; |
dd87eb3a TG |
484 | |
485 | /* Start handling the irq */ | |
486 | desc->chip->ack(irq); | |
487 | ||
488 | /* Mark the IRQ currently in progress.*/ | |
489 | desc->status |= IRQ_INPROGRESS; | |
490 | ||
491 | do { | |
492 | struct irqaction *action = desc->action; | |
493 | irqreturn_t action_ret; | |
494 | ||
495 | if (unlikely(!action)) { | |
496 | desc->chip->mask(irq); | |
497 | goto out_unlock; | |
498 | } | |
499 | ||
500 | /* | |
501 | * When another irq arrived while we were handling | |
502 | * one, we could have masked the irq. | |
503 | * Renable it, if it was not disabled in meantime. | |
504 | */ | |
505 | if (unlikely((desc->status & | |
506 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | |
507 | (IRQ_PENDING | IRQ_MASKED))) { | |
508 | desc->chip->unmask(irq); | |
509 | desc->status &= ~IRQ_MASKED; | |
510 | } | |
511 | ||
512 | desc->status &= ~IRQ_PENDING; | |
513 | spin_unlock(&desc->lock); | |
7d12e780 | 514 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 515 | if (!noirqdebug) |
7d12e780 | 516 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
517 | spin_lock(&desc->lock); |
518 | ||
519 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | |
520 | ||
521 | desc->status &= ~IRQ_INPROGRESS; | |
522 | out_unlock: | |
523 | spin_unlock(&desc->lock); | |
524 | } | |
525 | ||
dd87eb3a TG |
526 | /** |
527 | * handle_percpu_IRQ - Per CPU local irq handler | |
528 | * @irq: the interrupt number | |
529 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
530 | * |
531 | * Per CPU interrupts on SMP machines without locking requirements | |
532 | */ | |
7ad5b3a5 | 533 | void |
7d12e780 | 534 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
535 | { |
536 | irqreturn_t action_ret; | |
537 | ||
7f95ec9e | 538 | kstat_irqs_this_cpu(desc)++; |
dd87eb3a TG |
539 | |
540 | if (desc->chip->ack) | |
541 | desc->chip->ack(irq); | |
542 | ||
7d12e780 | 543 | action_ret = handle_IRQ_event(irq, desc->action); |
dd87eb3a | 544 | if (!noirqdebug) |
7d12e780 | 545 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
546 | |
547 | if (desc->chip->eoi) | |
548 | desc->chip->eoi(irq); | |
549 | } | |
550 | ||
dd87eb3a | 551 | void |
a460e745 IM |
552 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
553 | const char *name) | |
dd87eb3a TG |
554 | { |
555 | struct irq_desc *desc; | |
556 | unsigned long flags; | |
557 | ||
cb5bc832 | 558 | desc = irq_to_desc(irq); |
7d94f7ca | 559 | if (!desc) { |
dd87eb3a TG |
560 | printk(KERN_ERR |
561 | "Trying to install type control for IRQ%d\n", irq); | |
562 | return; | |
563 | } | |
564 | ||
dd87eb3a TG |
565 | if (!handle) |
566 | handle = handle_bad_irq; | |
9d7ac8be | 567 | else if (desc->chip == &no_irq_chip) { |
f8b5473f | 568 | printk(KERN_WARNING "Trying to install %sinterrupt handler " |
b039db8e | 569 | "for IRQ%d\n", is_chained ? "chained " : "", irq); |
f8b5473f TG |
570 | /* |
571 | * Some ARM implementations install a handler for really dumb | |
572 | * interrupt hardware without setting an irq_chip. This worked | |
573 | * with the ARM no_irq_chip but the check in setup_irq would | |
574 | * prevent us to setup the interrupt at all. Switch it to | |
575 | * dummy_irq_chip for easy transition. | |
576 | */ | |
577 | desc->chip = &dummy_irq_chip; | |
578 | } | |
dd87eb3a TG |
579 | |
580 | spin_lock_irqsave(&desc->lock, flags); | |
581 | ||
582 | /* Uninstall? */ | |
583 | if (handle == handle_bad_irq) { | |
5575ddf7 JB |
584 | if (desc->chip != &no_irq_chip) |
585 | mask_ack_irq(desc, irq); | |
dd87eb3a TG |
586 | desc->status |= IRQ_DISABLED; |
587 | desc->depth = 1; | |
588 | } | |
589 | desc->handle_irq = handle; | |
a460e745 | 590 | desc->name = name; |
dd87eb3a TG |
591 | |
592 | if (handle != handle_bad_irq && is_chained) { | |
593 | desc->status &= ~IRQ_DISABLED; | |
594 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; | |
595 | desc->depth = 0; | |
7e6e178a | 596 | desc->chip->startup(irq); |
dd87eb3a TG |
597 | } |
598 | spin_unlock_irqrestore(&desc->lock, flags); | |
599 | } | |
600 | ||
601 | void | |
602 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
57a58a94 | 603 | irq_flow_handler_t handle) |
dd87eb3a TG |
604 | { |
605 | set_irq_chip(irq, chip); | |
a460e745 | 606 | __set_irq_handler(irq, handle, 0, NULL); |
dd87eb3a TG |
607 | } |
608 | ||
a460e745 IM |
609 | void |
610 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | |
611 | irq_flow_handler_t handle, const char *name) | |
dd87eb3a | 612 | { |
a460e745 IM |
613 | set_irq_chip(irq, chip); |
614 | __set_irq_handler(irq, handle, 0, name); | |
dd87eb3a | 615 | } |
46f4f8f6 RB |
616 | |
617 | void __init set_irq_noprobe(unsigned int irq) | |
618 | { | |
619 | struct irq_desc *desc; | |
620 | unsigned long flags; | |
621 | ||
cb5bc832 | 622 | desc = irq_to_desc(irq); |
7d94f7ca | 623 | if (!desc) { |
46f4f8f6 RB |
624 | printk(KERN_ERR "Trying to mark IRQ%d non-probeable\n", irq); |
625 | ||
626 | return; | |
627 | } | |
628 | ||
46f4f8f6 RB |
629 | spin_lock_irqsave(&desc->lock, flags); |
630 | desc->status |= IRQ_NOPROBE; | |
631 | spin_unlock_irqrestore(&desc->lock, flags); | |
632 | } | |
633 | ||
634 | void __init set_irq_probe(unsigned int irq) | |
635 | { | |
636 | struct irq_desc *desc; | |
637 | unsigned long flags; | |
638 | ||
cb5bc832 | 639 | desc = irq_to_desc(irq); |
7d94f7ca | 640 | if (!desc) { |
46f4f8f6 RB |
641 | printk(KERN_ERR "Trying to mark IRQ%d probeable\n", irq); |
642 | ||
643 | return; | |
644 | } | |
645 | ||
46f4f8f6 RB |
646 | spin_lock_irqsave(&desc->lock, flags); |
647 | desc->status &= ~IRQ_NOPROBE; | |
648 | spin_unlock_irqrestore(&desc->lock, flags); | |
649 | } |