kvm: remove IA64 ioctls
[deliverable/linux.git] / kernel / irq / chip.c
CommitLineData
dd87eb3a
TG
1/*
2 * linux/kernel/irq/chip.c
3 *
4 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
5 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 *
7 * This file contains the core interrupt handling code, for irq-chip
8 * based architectures.
9 *
10 * Detailed information is available in Documentation/DocBook/genericirq
11 */
12
13#include <linux/irq.h>
7fe3730d 14#include <linux/msi.h>
dd87eb3a
TG
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
18
f069686e
SR
19#include <trace/events/irq.h>
20
dd87eb3a
TG
21#include "internals.h"
22
23/**
a0cd9ca2 24 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
25 * @irq: irq number
26 * @chip: pointer to irq chip description structure
27 */
a0cd9ca2 28int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 29{
dd87eb3a 30 unsigned long flags;
31d9d9b6 31 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 32
02725e74 33 if (!desc)
dd87eb3a 34 return -EINVAL;
dd87eb3a
TG
35
36 if (!chip)
37 chip = &no_irq_chip;
38
6b8ff312 39 desc->irq_data.chip = chip;
02725e74 40 irq_put_desc_unlock(desc, flags);
d72274e5
DD
41 /*
42 * For !CONFIG_SPARSE_IRQ make the irq show up in
f63b6a05 43 * allocated_irqs.
d72274e5 44 */
f63b6a05 45 irq_mark_irq(irq);
dd87eb3a
TG
46 return 0;
47}
a0cd9ca2 48EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
49
50/**
a0cd9ca2 51 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 52 * @irq: irq number
0c5d1eb7 53 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 54 */
a0cd9ca2 55int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 56{
dd87eb3a 57 unsigned long flags;
31d9d9b6 58 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
02725e74 59 int ret = 0;
dd87eb3a 60
02725e74
TG
61 if (!desc)
62 return -EINVAL;
dd87eb3a 63
f2b662da 64 type &= IRQ_TYPE_SENSE_MASK;
a09b659c 65 ret = __irq_set_trigger(desc, irq, type);
02725e74 66 irq_put_desc_busunlock(desc, flags);
dd87eb3a
TG
67 return ret;
68}
a0cd9ca2 69EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
70
71/**
a0cd9ca2 72 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
73 * @irq: Interrupt number
74 * @data: Pointer to interrupt specific data
75 *
76 * Set the hardware irq controller data for an irq
77 */
a0cd9ca2 78int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 79{
dd87eb3a 80 unsigned long flags;
31d9d9b6 81 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 82
02725e74 83 if (!desc)
dd87eb3a 84 return -EINVAL;
6b8ff312 85 desc->irq_data.handler_data = data;
02725e74 86 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
87 return 0;
88}
a0cd9ca2 89EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 90
5b912c10 91/**
51906e77
AG
92 * irq_set_msi_desc_off - set MSI descriptor data for an irq at offset
93 * @irq_base: Interrupt number base
94 * @irq_offset: Interrupt number offset
95 * @entry: Pointer to MSI descriptor data
5b912c10 96 *
51906e77 97 * Set the MSI descriptor entry for an irq at offset
5b912c10 98 */
51906e77
AG
99int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
100 struct msi_desc *entry)
5b912c10 101{
5b912c10 102 unsigned long flags;
51906e77 103 struct irq_desc *desc = irq_get_desc_lock(irq_base + irq_offset, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
5b912c10 104
02725e74 105 if (!desc)
5b912c10 106 return -EINVAL;
6b8ff312 107 desc->irq_data.msi_desc = entry;
51906e77
AG
108 if (entry && !irq_offset)
109 entry->irq = irq_base;
02725e74 110 irq_put_desc_unlock(desc, flags);
5b912c10
EB
111 return 0;
112}
113
51906e77
AG
114/**
115 * irq_set_msi_desc - set MSI descriptor data for an irq
116 * @irq: Interrupt number
117 * @entry: Pointer to MSI descriptor data
118 *
119 * Set the MSI descriptor entry for an irq
120 */
121int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
122{
123 return irq_set_msi_desc_off(irq, 0, entry);
124}
125
dd87eb3a 126/**
a0cd9ca2 127 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
128 * @irq: Interrupt number
129 * @data: Pointer to chip specific data
130 *
131 * Set the hardware irq chip data for an irq
132 */
a0cd9ca2 133int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 134{
dd87eb3a 135 unsigned long flags;
31d9d9b6 136 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 137
02725e74 138 if (!desc)
dd87eb3a 139 return -EINVAL;
6b8ff312 140 desc->irq_data.chip_data = data;
02725e74 141 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
142 return 0;
143}
a0cd9ca2 144EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 145
f303a6dd
TG
146struct irq_data *irq_get_irq_data(unsigned int irq)
147{
148 struct irq_desc *desc = irq_to_desc(irq);
149
150 return desc ? &desc->irq_data : NULL;
151}
152EXPORT_SYMBOL_GPL(irq_get_irq_data);
153
c1594b77
TG
154static void irq_state_clr_disabled(struct irq_desc *desc)
155{
801a0e9a 156 irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
157}
158
159static void irq_state_set_disabled(struct irq_desc *desc)
160{
801a0e9a 161 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
162}
163
6e40262e
TG
164static void irq_state_clr_masked(struct irq_desc *desc)
165{
32f4125e 166 irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
167}
168
169static void irq_state_set_masked(struct irq_desc *desc)
170{
32f4125e 171 irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
172}
173
b4bc724e 174int irq_startup(struct irq_desc *desc, bool resend)
46999238 175{
b4bc724e
TG
176 int ret = 0;
177
c1594b77 178 irq_state_clr_disabled(desc);
46999238
TG
179 desc->depth = 0;
180
3aae994f 181 if (desc->irq_data.chip->irq_startup) {
b4bc724e 182 ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
6e40262e 183 irq_state_clr_masked(desc);
b4bc724e
TG
184 } else {
185 irq_enable(desc);
3aae994f 186 }
b4bc724e
TG
187 if (resend)
188 check_irq_resend(desc, desc->irq_data.irq);
189 return ret;
46999238
TG
190}
191
192void irq_shutdown(struct irq_desc *desc)
193{
c1594b77 194 irq_state_set_disabled(desc);
46999238 195 desc->depth = 1;
50f7c032
TG
196 if (desc->irq_data.chip->irq_shutdown)
197 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
ed585a65 198 else if (desc->irq_data.chip->irq_disable)
50f7c032
TG
199 desc->irq_data.chip->irq_disable(&desc->irq_data);
200 else
201 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 202 irq_state_set_masked(desc);
46999238
TG
203}
204
87923470
TG
205void irq_enable(struct irq_desc *desc)
206{
c1594b77 207 irq_state_clr_disabled(desc);
50f7c032
TG
208 if (desc->irq_data.chip->irq_enable)
209 desc->irq_data.chip->irq_enable(&desc->irq_data);
210 else
211 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 212 irq_state_clr_masked(desc);
dd87eb3a
TG
213}
214
d671a605 215/**
f788e7bf 216 * irq_disable - Mark interrupt disabled
d671a605
AF
217 * @desc: irq descriptor which should be disabled
218 *
219 * If the chip does not implement the irq_disable callback, we
220 * use a lazy disable approach. That means we mark the interrupt
221 * disabled, but leave the hardware unmasked. That's an
222 * optimization because we avoid the hardware access for the
223 * common case where no interrupt happens after we marked it
224 * disabled. If an interrupt happens, then the interrupt flow
225 * handler masks the line at the hardware level and marks it
226 * pending.
227 */
50f7c032 228void irq_disable(struct irq_desc *desc)
89d694b9 229{
c1594b77 230 irq_state_set_disabled(desc);
50f7c032
TG
231 if (desc->irq_data.chip->irq_disable) {
232 desc->irq_data.chip->irq_disable(&desc->irq_data);
a61d8258 233 irq_state_set_masked(desc);
50f7c032 234 }
89d694b9
TG
235}
236
31d9d9b6
MZ
237void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
238{
239 if (desc->irq_data.chip->irq_enable)
240 desc->irq_data.chip->irq_enable(&desc->irq_data);
241 else
242 desc->irq_data.chip->irq_unmask(&desc->irq_data);
243 cpumask_set_cpu(cpu, desc->percpu_enabled);
244}
245
246void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
247{
248 if (desc->irq_data.chip->irq_disable)
249 desc->irq_data.chip->irq_disable(&desc->irq_data);
250 else
251 desc->irq_data.chip->irq_mask(&desc->irq_data);
252 cpumask_clear_cpu(cpu, desc->percpu_enabled);
253}
254
9205e31d 255static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 256{
9205e31d
TG
257 if (desc->irq_data.chip->irq_mask_ack)
258 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
dd87eb3a 259 else {
e2c0f8ff 260 desc->irq_data.chip->irq_mask(&desc->irq_data);
22a49163
TG
261 if (desc->irq_data.chip->irq_ack)
262 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 263 }
6e40262e 264 irq_state_set_masked(desc);
0b1adaa0
TG
265}
266
d4d5e089 267void mask_irq(struct irq_desc *desc)
0b1adaa0 268{
e2c0f8ff
TG
269 if (desc->irq_data.chip->irq_mask) {
270 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 271 irq_state_set_masked(desc);
0b1adaa0
TG
272 }
273}
274
d4d5e089 275void unmask_irq(struct irq_desc *desc)
0b1adaa0 276{
0eda58b7
TG
277 if (desc->irq_data.chip->irq_unmask) {
278 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 279 irq_state_clr_masked(desc);
0b1adaa0 280 }
dd87eb3a
TG
281}
282
328a4978
TG
283void unmask_threaded_irq(struct irq_desc *desc)
284{
285 struct irq_chip *chip = desc->irq_data.chip;
286
287 if (chip->flags & IRQCHIP_EOI_THREADED)
288 chip->irq_eoi(&desc->irq_data);
289
290 if (chip->irq_unmask) {
291 chip->irq_unmask(&desc->irq_data);
292 irq_state_clr_masked(desc);
293 }
294}
295
399b5da2
TG
296/*
297 * handle_nested_irq - Handle a nested irq from a irq thread
298 * @irq: the interrupt number
299 *
300 * Handle interrupts which are nested into a threaded interrupt
301 * handler. The handler function is called inside the calling
302 * threads context.
303 */
304void handle_nested_irq(unsigned int irq)
305{
306 struct irq_desc *desc = irq_to_desc(irq);
307 struct irqaction *action;
308 irqreturn_t action_ret;
309
310 might_sleep();
311
239007b8 312 raw_spin_lock_irq(&desc->lock);
399b5da2 313
293a7a0a 314 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
399b5da2
TG
315 kstat_incr_irqs_this_cpu(irq, desc);
316
317 action = desc->action;
23812b9d
NJ
318 if (unlikely(!action || irqd_irq_disabled(&desc->irq_data))) {
319 desc->istate |= IRQS_PENDING;
399b5da2 320 goto out_unlock;
23812b9d 321 }
399b5da2 322
32f4125e 323 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
239007b8 324 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
325
326 action_ret = action->thread_fn(action->irq, action->dev_id);
327 if (!noirqdebug)
328 note_interrupt(irq, desc, action_ret);
329
239007b8 330 raw_spin_lock_irq(&desc->lock);
32f4125e 331 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
399b5da2
TG
332
333out_unlock:
239007b8 334 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
335}
336EXPORT_SYMBOL_GPL(handle_nested_irq);
337
fe200ae4
TG
338static bool irq_check_poll(struct irq_desc *desc)
339{
6954b75b 340 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
341 return false;
342 return irq_wait_for_poll(desc);
343}
344
c7bd3ec0
TG
345static bool irq_may_run(struct irq_desc *desc)
346{
9ce7a258
TG
347 unsigned int mask = IRQD_IRQ_INPROGRESS | IRQD_WAKEUP_ARMED;
348
349 /*
350 * If the interrupt is not in progress and is not an armed
351 * wakeup interrupt, proceed.
352 */
353 if (!irqd_has_set(&desc->irq_data, mask))
c7bd3ec0 354 return true;
9ce7a258
TG
355
356 /*
357 * If the interrupt is an armed wakeup source, mark it pending
358 * and suspended, disable it and notify the pm core about the
359 * event.
360 */
361 if (irq_pm_check_wakeup(desc))
362 return false;
363
364 /*
365 * Handle a potential concurrent poll on a different core.
366 */
c7bd3ec0
TG
367 return irq_check_poll(desc);
368}
369
dd87eb3a
TG
370/**
371 * handle_simple_irq - Simple and software-decoded IRQs.
372 * @irq: the interrupt number
373 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
374 *
375 * Simple interrupts are either sent from a demultiplexing interrupt
376 * handler or come from hardware, where no interrupt hardware control
377 * is necessary.
378 *
379 * Note: The caller is expected to handle the ack, clear, mask and
380 * unmask issues if necessary.
381 */
7ad5b3a5 382void
7d12e780 383handle_simple_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 384{
239007b8 385 raw_spin_lock(&desc->lock);
dd87eb3a 386
c7bd3ec0
TG
387 if (!irq_may_run(desc))
388 goto out_unlock;
fe200ae4 389
163ef309 390 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 391 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 392
23812b9d
NJ
393 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
394 desc->istate |= IRQS_PENDING;
dd87eb3a 395 goto out_unlock;
23812b9d 396 }
dd87eb3a 397
107781e7 398 handle_irq_event(desc);
dd87eb3a 399
dd87eb3a 400out_unlock:
239007b8 401 raw_spin_unlock(&desc->lock);
dd87eb3a 402}
edf76f83 403EXPORT_SYMBOL_GPL(handle_simple_irq);
dd87eb3a 404
ac563761
TG
405/*
406 * Called unconditionally from handle_level_irq() and only for oneshot
407 * interrupts from handle_fasteoi_irq()
408 */
409static void cond_unmask_irq(struct irq_desc *desc)
410{
411 /*
412 * We need to unmask in the following cases:
413 * - Standard level irq (IRQF_ONESHOT is not set)
414 * - Oneshot irq which did not wake the thread (caused by a
415 * spurious interrupt or a primary handler handling it
416 * completely).
417 */
418 if (!irqd_irq_disabled(&desc->irq_data) &&
419 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
420 unmask_irq(desc);
421}
422
dd87eb3a
TG
423/**
424 * handle_level_irq - Level type irq handler
425 * @irq: the interrupt number
426 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
427 *
428 * Level type interrupts are active as long as the hardware line has
429 * the active level. This may require to mask the interrupt and unmask
430 * it after the associated handler has acknowledged the device, so the
431 * interrupt line is back to inactive.
432 */
7ad5b3a5 433void
7d12e780 434handle_level_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 435{
239007b8 436 raw_spin_lock(&desc->lock);
9205e31d 437 mask_ack_irq(desc);
dd87eb3a 438
c7bd3ec0
TG
439 if (!irq_may_run(desc))
440 goto out_unlock;
fe200ae4 441
163ef309 442 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 443 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
444
445 /*
446 * If its disabled or no action available
447 * keep it masked and get out of here
448 */
d4dc0f90
TG
449 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
450 desc->istate |= IRQS_PENDING;
86998aa6 451 goto out_unlock;
d4dc0f90 452 }
dd87eb3a 453
1529866c 454 handle_irq_event(desc);
b25c340c 455
ac563761
TG
456 cond_unmask_irq(desc);
457
86998aa6 458out_unlock:
239007b8 459 raw_spin_unlock(&desc->lock);
dd87eb3a 460}
14819ea1 461EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a 462
78129576
TG
463#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
464static inline void preflow_handler(struct irq_desc *desc)
465{
466 if (desc->preflow_handler)
467 desc->preflow_handler(&desc->irq_data);
468}
469#else
470static inline void preflow_handler(struct irq_desc *desc) { }
471#endif
472
328a4978
TG
473static void cond_unmask_eoi_irq(struct irq_desc *desc, struct irq_chip *chip)
474{
475 if (!(desc->istate & IRQS_ONESHOT)) {
476 chip->irq_eoi(&desc->irq_data);
477 return;
478 }
479 /*
480 * We need to unmask in the following cases:
481 * - Oneshot irq which did not wake the thread (caused by a
482 * spurious interrupt or a primary handler handling it
483 * completely).
484 */
485 if (!irqd_irq_disabled(&desc->irq_data) &&
486 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot) {
487 chip->irq_eoi(&desc->irq_data);
488 unmask_irq(desc);
489 } else if (!(chip->flags & IRQCHIP_EOI_THREADED)) {
490 chip->irq_eoi(&desc->irq_data);
491 }
492}
493
dd87eb3a 494/**
47c2a3aa 495 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a
TG
496 * @irq: the interrupt number
497 * @desc: the interrupt description structure for this irq
dd87eb3a 498 *
47c2a3aa 499 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
500 * call when the interrupt has been serviced. This enables support
501 * for modern forms of interrupt handlers, which handle the flow
502 * details in hardware, transparently.
503 */
7ad5b3a5 504void
7d12e780 505handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 506{
328a4978
TG
507 struct irq_chip *chip = desc->irq_data.chip;
508
239007b8 509 raw_spin_lock(&desc->lock);
dd87eb3a 510
c7bd3ec0
TG
511 if (!irq_may_run(desc))
512 goto out;
dd87eb3a 513
163ef309 514 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 515 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
516
517 /*
518 * If its disabled or no action available
76d21601 519 * then mask it and get out of here:
dd87eb3a 520 */
32f4125e 521 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
2a0d6fb3 522 desc->istate |= IRQS_PENDING;
e2c0f8ff 523 mask_irq(desc);
dd87eb3a 524 goto out;
98bb244b 525 }
c69e3758
TG
526
527 if (desc->istate & IRQS_ONESHOT)
528 mask_irq(desc);
529
78129576 530 preflow_handler(desc);
a7ae4de5 531 handle_irq_event(desc);
77694b40 532
328a4978 533 cond_unmask_eoi_irq(desc, chip);
ac563761 534
239007b8 535 raw_spin_unlock(&desc->lock);
77694b40
TG
536 return;
537out:
328a4978
TG
538 if (!(chip->flags & IRQCHIP_EOI_IF_HANDLED))
539 chip->irq_eoi(&desc->irq_data);
540 raw_spin_unlock(&desc->lock);
dd87eb3a 541}
7cad45ee 542EXPORT_SYMBOL_GPL(handle_fasteoi_irq);
dd87eb3a
TG
543
544/**
545 * handle_edge_irq - edge type IRQ handler
546 * @irq: the interrupt number
547 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
548 *
549 * Interrupt occures on the falling and/or rising edge of a hardware
25985edc 550 * signal. The occurrence is latched into the irq controller hardware
dd87eb3a
TG
551 * and must be acked in order to be reenabled. After the ack another
552 * interrupt can happen on the same source even before the first one
dfff0615 553 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
554 * might be necessary to disable (mask) the interrupt depending on the
555 * controller hardware. This requires to reenable the interrupt inside
556 * of the loop which handles the interrupts which have arrived while
557 * the handler was running. If all pending interrupts are handled, the
558 * loop is left.
559 */
7ad5b3a5 560void
7d12e780 561handle_edge_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 562{
239007b8 563 raw_spin_lock(&desc->lock);
dd87eb3a 564
163ef309 565 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
c3d7acd0 566
c7bd3ec0
TG
567 if (!irq_may_run(desc)) {
568 desc->istate |= IRQS_PENDING;
569 mask_ack_irq(desc);
570 goto out_unlock;
dd87eb3a 571 }
c3d7acd0 572
dd87eb3a 573 /*
c3d7acd0
TG
574 * If its disabled or no action available then mask it and get
575 * out of here.
dd87eb3a 576 */
c3d7acd0
TG
577 if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
578 desc->istate |= IRQS_PENDING;
579 mask_ack_irq(desc);
580 goto out_unlock;
dd87eb3a 581 }
c3d7acd0 582
d6c88a50 583 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
584
585 /* Start handling the irq */
22a49163 586 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 587
dd87eb3a 588 do {
a60a5dc2 589 if (unlikely(!desc->action)) {
e2c0f8ff 590 mask_irq(desc);
dd87eb3a
TG
591 goto out_unlock;
592 }
593
594 /*
595 * When another irq arrived while we were handling
596 * one, we could have masked the irq.
597 * Renable it, if it was not disabled in meantime.
598 */
2a0d6fb3 599 if (unlikely(desc->istate & IRQS_PENDING)) {
32f4125e
TG
600 if (!irqd_irq_disabled(&desc->irq_data) &&
601 irqd_irq_masked(&desc->irq_data))
c1594b77 602 unmask_irq(desc);
dd87eb3a
TG
603 }
604
a60a5dc2 605 handle_irq_event(desc);
dd87eb3a 606
2a0d6fb3 607 } while ((desc->istate & IRQS_PENDING) &&
32f4125e 608 !irqd_irq_disabled(&desc->irq_data));
dd87eb3a 609
dd87eb3a 610out_unlock:
239007b8 611 raw_spin_unlock(&desc->lock);
dd87eb3a 612}
3911ff30 613EXPORT_SYMBOL(handle_edge_irq);
dd87eb3a 614
0521c8fb
TG
615#ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
616/**
617 * handle_edge_eoi_irq - edge eoi type IRQ handler
618 * @irq: the interrupt number
619 * @desc: the interrupt description structure for this irq
620 *
621 * Similar as the above handle_edge_irq, but using eoi and w/o the
622 * mask/unmask logic.
623 */
624void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc)
625{
626 struct irq_chip *chip = irq_desc_get_chip(desc);
627
628 raw_spin_lock(&desc->lock);
629
630 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
c3d7acd0 631
c7bd3ec0
TG
632 if (!irq_may_run(desc)) {
633 desc->istate |= IRQS_PENDING;
634 goto out_eoi;
0521c8fb 635 }
c3d7acd0 636
0521c8fb 637 /*
c3d7acd0
TG
638 * If its disabled or no action available then mask it and get
639 * out of here.
0521c8fb 640 */
c3d7acd0
TG
641 if (irqd_irq_disabled(&desc->irq_data) || !desc->action) {
642 desc->istate |= IRQS_PENDING;
643 goto out_eoi;
0521c8fb 644 }
c3d7acd0 645
0521c8fb
TG
646 kstat_incr_irqs_this_cpu(irq, desc);
647
648 do {
649 if (unlikely(!desc->action))
650 goto out_eoi;
651
652 handle_irq_event(desc);
653
654 } while ((desc->istate & IRQS_PENDING) &&
655 !irqd_irq_disabled(&desc->irq_data));
656
ac0e0447 657out_eoi:
0521c8fb
TG
658 chip->irq_eoi(&desc->irq_data);
659 raw_spin_unlock(&desc->lock);
660}
661#endif
662
dd87eb3a 663/**
24b26d42 664 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a
TG
665 * @irq: the interrupt number
666 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
667 *
668 * Per CPU interrupts on SMP machines without locking requirements
669 */
7ad5b3a5 670void
7d12e780 671handle_percpu_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 672{
35e857cb 673 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 674
d6c88a50 675 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 676
849f061c
TG
677 if (chip->irq_ack)
678 chip->irq_ack(&desc->irq_data);
dd87eb3a 679
849f061c 680 handle_irq_event_percpu(desc, desc->action);
dd87eb3a 681
849f061c
TG
682 if (chip->irq_eoi)
683 chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
684}
685
31d9d9b6
MZ
686/**
687 * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
688 * @irq: the interrupt number
689 * @desc: the interrupt description structure for this irq
690 *
691 * Per CPU interrupts on SMP machines without locking requirements. Same as
692 * handle_percpu_irq() above but with the following extras:
693 *
694 * action->percpu_dev_id is a pointer to percpu variables which
695 * contain the real device id for the cpu on which this handler is
696 * called
697 */
698void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc)
699{
700 struct irq_chip *chip = irq_desc_get_chip(desc);
701 struct irqaction *action = desc->action;
532d0d06 702 void *dev_id = raw_cpu_ptr(action->percpu_dev_id);
31d9d9b6
MZ
703 irqreturn_t res;
704
705 kstat_incr_irqs_this_cpu(irq, desc);
706
707 if (chip->irq_ack)
708 chip->irq_ack(&desc->irq_data);
709
710 trace_irq_handler_entry(irq, action);
711 res = action->handler(irq, dev_id);
712 trace_irq_handler_exit(irq, action, res);
713
714 if (chip->irq_eoi)
715 chip->irq_eoi(&desc->irq_data);
716}
717
dd87eb3a 718void
3836ca08 719__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
a460e745 720 const char *name)
dd87eb3a 721{
dd87eb3a 722 unsigned long flags;
31d9d9b6 723 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
dd87eb3a 724
02725e74 725 if (!desc)
dd87eb3a 726 return;
dd87eb3a 727
091738a2 728 if (!handle) {
dd87eb3a 729 handle = handle_bad_irq;
091738a2
TG
730 } else {
731 if (WARN_ON(desc->irq_data.chip == &no_irq_chip))
02725e74 732 goto out;
f8b5473f 733 }
dd87eb3a 734
dd87eb3a
TG
735 /* Uninstall? */
736 if (handle == handle_bad_irq) {
6b8ff312 737 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 738 mask_ack_irq(desc);
801a0e9a 739 irq_state_set_disabled(desc);
dd87eb3a
TG
740 desc->depth = 1;
741 }
742 desc->handle_irq = handle;
a460e745 743 desc->name = name;
dd87eb3a
TG
744
745 if (handle != handle_bad_irq && is_chained) {
1ccb4e61
TG
746 irq_settings_set_noprobe(desc);
747 irq_settings_set_norequest(desc);
7f1b1244 748 irq_settings_set_nothread(desc);
b4bc724e 749 irq_startup(desc, true);
dd87eb3a 750 }
02725e74
TG
751out:
752 irq_put_desc_busunlock(desc, flags);
dd87eb3a 753}
3836ca08 754EXPORT_SYMBOL_GPL(__irq_set_handler);
dd87eb3a
TG
755
756void
3836ca08 757irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
a460e745 758 irq_flow_handler_t handle, const char *name)
dd87eb3a 759{
35e857cb 760 irq_set_chip(irq, chip);
3836ca08 761 __irq_set_handler(irq, handle, 0, name);
dd87eb3a 762}
b3ae66f2 763EXPORT_SYMBOL_GPL(irq_set_chip_and_handler_name);
46f4f8f6 764
44247184 765void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 766{
46f4f8f6 767 unsigned long flags;
31d9d9b6 768 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
46f4f8f6 769
44247184 770 if (!desc)
46f4f8f6 771 return;
a005677b
TG
772 irq_settings_clr_and_set(desc, clr, set);
773
876dbd4c 774 irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
e1ef8241 775 IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
a005677b
TG
776 if (irq_settings_has_no_balance_set(desc))
777 irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
778 if (irq_settings_is_per_cpu(desc))
779 irqd_set(&desc->irq_data, IRQD_PER_CPU);
e1ef8241
TG
780 if (irq_settings_can_move_pcntxt(desc))
781 irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
0ef5ca1e
TG
782 if (irq_settings_is_level(desc))
783 irqd_set(&desc->irq_data, IRQD_LEVEL);
a005677b 784
876dbd4c
TG
785 irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc));
786
02725e74 787 irq_put_desc_unlock(desc, flags);
46f4f8f6 788}
edf76f83 789EXPORT_SYMBOL_GPL(irq_modify_status);
0fdb4b25
DD
790
791/**
792 * irq_cpu_online - Invoke all irq_cpu_online functions.
793 *
794 * Iterate through all irqs and invoke the chip.irq_cpu_online()
795 * for each.
796 */
797void irq_cpu_online(void)
798{
799 struct irq_desc *desc;
800 struct irq_chip *chip;
801 unsigned long flags;
802 unsigned int irq;
803
804 for_each_active_irq(irq) {
805 desc = irq_to_desc(irq);
806 if (!desc)
807 continue;
808
809 raw_spin_lock_irqsave(&desc->lock, flags);
810
811 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
812 if (chip && chip->irq_cpu_online &&
813 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 814 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
815 chip->irq_cpu_online(&desc->irq_data);
816
817 raw_spin_unlock_irqrestore(&desc->lock, flags);
818 }
819}
820
821/**
822 * irq_cpu_offline - Invoke all irq_cpu_offline functions.
823 *
824 * Iterate through all irqs and invoke the chip.irq_cpu_offline()
825 * for each.
826 */
827void irq_cpu_offline(void)
828{
829 struct irq_desc *desc;
830 struct irq_chip *chip;
831 unsigned long flags;
832 unsigned int irq;
833
834 for_each_active_irq(irq) {
835 desc = irq_to_desc(irq);
836 if (!desc)
837 continue;
838
839 raw_spin_lock_irqsave(&desc->lock, flags);
840
841 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
842 if (chip && chip->irq_cpu_offline &&
843 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 844 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
845 chip->irq_cpu_offline(&desc->irq_data);
846
847 raw_spin_unlock_irqrestore(&desc->lock, flags);
848 }
849}
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