genirq: Add IRQCHIP_SKIP_SET_WAKE flag
[deliverable/linux.git] / kernel / irq / chip.c
CommitLineData
dd87eb3a
TG
1/*
2 * linux/kernel/irq/chip.c
3 *
4 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
5 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 *
7 * This file contains the core interrupt handling code, for irq-chip
8 * based architectures.
9 *
10 * Detailed information is available in Documentation/DocBook/genericirq
11 */
12
13#include <linux/irq.h>
7fe3730d 14#include <linux/msi.h>
dd87eb3a
TG
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
18
19#include "internals.h"
20
21/**
a0cd9ca2 22 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
23 * @irq: irq number
24 * @chip: pointer to irq chip description structure
25 */
a0cd9ca2 26int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 27{
dd87eb3a 28 unsigned long flags;
02725e74 29 struct irq_desc *desc = irq_get_desc_lock(irq, &flags);
dd87eb3a 30
02725e74 31 if (!desc)
dd87eb3a 32 return -EINVAL;
dd87eb3a
TG
33
34 if (!chip)
35 chip = &no_irq_chip;
36
6b8ff312 37 desc->irq_data.chip = chip;
02725e74 38 irq_put_desc_unlock(desc, flags);
d72274e5
DD
39 /*
40 * For !CONFIG_SPARSE_IRQ make the irq show up in
41 * allocated_irqs. For the CONFIG_SPARSE_IRQ case, it is
42 * already marked, and this call is harmless.
43 */
44 irq_reserve_irq(irq);
dd87eb3a
TG
45 return 0;
46}
a0cd9ca2 47EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
48
49/**
a0cd9ca2 50 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 51 * @irq: irq number
0c5d1eb7 52 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 53 */
a0cd9ca2 54int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 55{
dd87eb3a 56 unsigned long flags;
02725e74
TG
57 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags);
58 int ret = 0;
dd87eb3a 59
02725e74
TG
60 if (!desc)
61 return -EINVAL;
dd87eb3a 62
f2b662da 63 type &= IRQ_TYPE_SENSE_MASK;
02725e74
TG
64 if (type != IRQ_TYPE_NONE)
65 ret = __irq_set_trigger(desc, irq, type);
66 irq_put_desc_busunlock(desc, flags);
dd87eb3a
TG
67 return ret;
68}
a0cd9ca2 69EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
70
71/**
a0cd9ca2 72 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
73 * @irq: Interrupt number
74 * @data: Pointer to interrupt specific data
75 *
76 * Set the hardware irq controller data for an irq
77 */
a0cd9ca2 78int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 79{
dd87eb3a 80 unsigned long flags;
02725e74 81 struct irq_desc *desc = irq_get_desc_lock(irq, &flags);
dd87eb3a 82
02725e74 83 if (!desc)
dd87eb3a 84 return -EINVAL;
6b8ff312 85 desc->irq_data.handler_data = data;
02725e74 86 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
87 return 0;
88}
a0cd9ca2 89EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 90
5b912c10 91/**
a0cd9ca2 92 * irq_set_msi_desc - set MSI descriptor data for an irq
5b912c10 93 * @irq: Interrupt number
472900b8 94 * @entry: Pointer to MSI descriptor data
5b912c10 95 *
24b26d42 96 * Set the MSI descriptor entry for an irq
5b912c10 97 */
a0cd9ca2 98int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
5b912c10 99{
5b912c10 100 unsigned long flags;
02725e74 101 struct irq_desc *desc = irq_get_desc_lock(irq, &flags);
5b912c10 102
02725e74 103 if (!desc)
5b912c10 104 return -EINVAL;
6b8ff312 105 desc->irq_data.msi_desc = entry;
7fe3730d
ME
106 if (entry)
107 entry->irq = irq;
02725e74 108 irq_put_desc_unlock(desc, flags);
5b912c10
EB
109 return 0;
110}
111
dd87eb3a 112/**
a0cd9ca2 113 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
114 * @irq: Interrupt number
115 * @data: Pointer to chip specific data
116 *
117 * Set the hardware irq chip data for an irq
118 */
a0cd9ca2 119int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 120{
dd87eb3a 121 unsigned long flags;
02725e74 122 struct irq_desc *desc = irq_get_desc_lock(irq, &flags);
dd87eb3a 123
02725e74 124 if (!desc)
dd87eb3a 125 return -EINVAL;
6b8ff312 126 desc->irq_data.chip_data = data;
02725e74 127 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
128 return 0;
129}
a0cd9ca2 130EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 131
f303a6dd
TG
132struct irq_data *irq_get_irq_data(unsigned int irq)
133{
134 struct irq_desc *desc = irq_to_desc(irq);
135
136 return desc ? &desc->irq_data : NULL;
137}
138EXPORT_SYMBOL_GPL(irq_get_irq_data);
139
c1594b77
TG
140static void irq_state_clr_disabled(struct irq_desc *desc)
141{
801a0e9a 142 irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
143}
144
145static void irq_state_set_disabled(struct irq_desc *desc)
146{
801a0e9a 147 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
148}
149
6e40262e
TG
150static void irq_state_clr_masked(struct irq_desc *desc)
151{
32f4125e 152 irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
153}
154
155static void irq_state_set_masked(struct irq_desc *desc)
156{
32f4125e 157 irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
158}
159
46999238
TG
160int irq_startup(struct irq_desc *desc)
161{
c1594b77 162 irq_state_clr_disabled(desc);
46999238
TG
163 desc->depth = 0;
164
3aae994f
TG
165 if (desc->irq_data.chip->irq_startup) {
166 int ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
6e40262e 167 irq_state_clr_masked(desc);
3aae994f
TG
168 return ret;
169 }
46999238 170
87923470 171 irq_enable(desc);
46999238
TG
172 return 0;
173}
174
175void irq_shutdown(struct irq_desc *desc)
176{
c1594b77 177 irq_state_set_disabled(desc);
46999238 178 desc->depth = 1;
50f7c032
TG
179 if (desc->irq_data.chip->irq_shutdown)
180 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
ed585a65 181 else if (desc->irq_data.chip->irq_disable)
50f7c032
TG
182 desc->irq_data.chip->irq_disable(&desc->irq_data);
183 else
184 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 185 irq_state_set_masked(desc);
46999238
TG
186}
187
87923470
TG
188void irq_enable(struct irq_desc *desc)
189{
c1594b77 190 irq_state_clr_disabled(desc);
50f7c032
TG
191 if (desc->irq_data.chip->irq_enable)
192 desc->irq_data.chip->irq_enable(&desc->irq_data);
193 else
194 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 195 irq_state_clr_masked(desc);
dd87eb3a
TG
196}
197
50f7c032 198void irq_disable(struct irq_desc *desc)
89d694b9 199{
c1594b77 200 irq_state_set_disabled(desc);
50f7c032
TG
201 if (desc->irq_data.chip->irq_disable) {
202 desc->irq_data.chip->irq_disable(&desc->irq_data);
a61d8258 203 irq_state_set_masked(desc);
50f7c032 204 }
89d694b9
TG
205}
206
9205e31d 207static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 208{
9205e31d
TG
209 if (desc->irq_data.chip->irq_mask_ack)
210 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
dd87eb3a 211 else {
e2c0f8ff 212 desc->irq_data.chip->irq_mask(&desc->irq_data);
22a49163
TG
213 if (desc->irq_data.chip->irq_ack)
214 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 215 }
6e40262e 216 irq_state_set_masked(desc);
0b1adaa0
TG
217}
218
d4d5e089 219void mask_irq(struct irq_desc *desc)
0b1adaa0 220{
e2c0f8ff
TG
221 if (desc->irq_data.chip->irq_mask) {
222 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 223 irq_state_set_masked(desc);
0b1adaa0
TG
224 }
225}
226
d4d5e089 227void unmask_irq(struct irq_desc *desc)
0b1adaa0 228{
0eda58b7
TG
229 if (desc->irq_data.chip->irq_unmask) {
230 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 231 irq_state_clr_masked(desc);
0b1adaa0 232 }
dd87eb3a
TG
233}
234
399b5da2
TG
235/*
236 * handle_nested_irq - Handle a nested irq from a irq thread
237 * @irq: the interrupt number
238 *
239 * Handle interrupts which are nested into a threaded interrupt
240 * handler. The handler function is called inside the calling
241 * threads context.
242 */
243void handle_nested_irq(unsigned int irq)
244{
245 struct irq_desc *desc = irq_to_desc(irq);
246 struct irqaction *action;
247 irqreturn_t action_ret;
248
249 might_sleep();
250
239007b8 251 raw_spin_lock_irq(&desc->lock);
399b5da2
TG
252
253 kstat_incr_irqs_this_cpu(irq, desc);
254
255 action = desc->action;
32f4125e 256 if (unlikely(!action || irqd_irq_disabled(&desc->irq_data)))
399b5da2
TG
257 goto out_unlock;
258
32f4125e 259 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
239007b8 260 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
261
262 action_ret = action->thread_fn(action->irq, action->dev_id);
263 if (!noirqdebug)
264 note_interrupt(irq, desc, action_ret);
265
239007b8 266 raw_spin_lock_irq(&desc->lock);
32f4125e 267 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
399b5da2
TG
268
269out_unlock:
239007b8 270 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
271}
272EXPORT_SYMBOL_GPL(handle_nested_irq);
273
fe200ae4
TG
274static bool irq_check_poll(struct irq_desc *desc)
275{
6954b75b 276 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
277 return false;
278 return irq_wait_for_poll(desc);
279}
280
dd87eb3a
TG
281/**
282 * handle_simple_irq - Simple and software-decoded IRQs.
283 * @irq: the interrupt number
284 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
285 *
286 * Simple interrupts are either sent from a demultiplexing interrupt
287 * handler or come from hardware, where no interrupt hardware control
288 * is necessary.
289 *
290 * Note: The caller is expected to handle the ack, clear, mask and
291 * unmask issues if necessary.
292 */
7ad5b3a5 293void
7d12e780 294handle_simple_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 295{
239007b8 296 raw_spin_lock(&desc->lock);
dd87eb3a 297
32f4125e 298 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
299 if (!irq_check_poll(desc))
300 goto out_unlock;
301
163ef309 302 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 303 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 304
32f4125e 305 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data)))
dd87eb3a
TG
306 goto out_unlock;
307
107781e7 308 handle_irq_event(desc);
dd87eb3a 309
dd87eb3a 310out_unlock:
239007b8 311 raw_spin_unlock(&desc->lock);
dd87eb3a 312}
edf76f83 313EXPORT_SYMBOL_GPL(handle_simple_irq);
dd87eb3a
TG
314
315/**
316 * handle_level_irq - Level type irq handler
317 * @irq: the interrupt number
318 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
319 *
320 * Level type interrupts are active as long as the hardware line has
321 * the active level. This may require to mask the interrupt and unmask
322 * it after the associated handler has acknowledged the device, so the
323 * interrupt line is back to inactive.
324 */
7ad5b3a5 325void
7d12e780 326handle_level_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 327{
239007b8 328 raw_spin_lock(&desc->lock);
9205e31d 329 mask_ack_irq(desc);
dd87eb3a 330
32f4125e 331 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
332 if (!irq_check_poll(desc))
333 goto out_unlock;
334
163ef309 335 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 336 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
337
338 /*
339 * If its disabled or no action available
340 * keep it masked and get out of here
341 */
32f4125e 342 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data)))
86998aa6 343 goto out_unlock;
dd87eb3a 344
1529866c 345 handle_irq_event(desc);
b25c340c 346
32f4125e 347 if (!irqd_irq_disabled(&desc->irq_data) && !(desc->istate & IRQS_ONESHOT))
0eda58b7 348 unmask_irq(desc);
86998aa6 349out_unlock:
239007b8 350 raw_spin_unlock(&desc->lock);
dd87eb3a 351}
14819ea1 352EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a 353
78129576
TG
354#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
355static inline void preflow_handler(struct irq_desc *desc)
356{
357 if (desc->preflow_handler)
358 desc->preflow_handler(&desc->irq_data);
359}
360#else
361static inline void preflow_handler(struct irq_desc *desc) { }
362#endif
363
dd87eb3a 364/**
47c2a3aa 365 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a
TG
366 * @irq: the interrupt number
367 * @desc: the interrupt description structure for this irq
dd87eb3a 368 *
47c2a3aa 369 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
370 * call when the interrupt has been serviced. This enables support
371 * for modern forms of interrupt handlers, which handle the flow
372 * details in hardware, transparently.
373 */
7ad5b3a5 374void
7d12e780 375handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 376{
239007b8 377 raw_spin_lock(&desc->lock);
dd87eb3a 378
32f4125e 379 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
380 if (!irq_check_poll(desc))
381 goto out;
dd87eb3a 382
163ef309 383 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 384 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
385
386 /*
387 * If its disabled or no action available
76d21601 388 * then mask it and get out of here:
dd87eb3a 389 */
32f4125e 390 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
2a0d6fb3 391 desc->istate |= IRQS_PENDING;
e2c0f8ff 392 mask_irq(desc);
dd87eb3a 393 goto out;
98bb244b 394 }
c69e3758
TG
395
396 if (desc->istate & IRQS_ONESHOT)
397 mask_irq(desc);
398
78129576 399 preflow_handler(desc);
a7ae4de5 400 handle_irq_event(desc);
77694b40
TG
401
402out_eoi:
0c5c1557 403 desc->irq_data.chip->irq_eoi(&desc->irq_data);
77694b40 404out_unlock:
239007b8 405 raw_spin_unlock(&desc->lock);
77694b40
TG
406 return;
407out:
408 if (!(desc->irq_data.chip->flags & IRQCHIP_EOI_IF_HANDLED))
409 goto out_eoi;
410 goto out_unlock;
dd87eb3a
TG
411}
412
413/**
414 * handle_edge_irq - edge type IRQ handler
415 * @irq: the interrupt number
416 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
417 *
418 * Interrupt occures on the falling and/or rising edge of a hardware
25985edc 419 * signal. The occurrence is latched into the irq controller hardware
dd87eb3a
TG
420 * and must be acked in order to be reenabled. After the ack another
421 * interrupt can happen on the same source even before the first one
dfff0615 422 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
423 * might be necessary to disable (mask) the interrupt depending on the
424 * controller hardware. This requires to reenable the interrupt inside
425 * of the loop which handles the interrupts which have arrived while
426 * the handler was running. If all pending interrupts are handled, the
427 * loop is left.
428 */
7ad5b3a5 429void
7d12e780 430handle_edge_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 431{
239007b8 432 raw_spin_lock(&desc->lock);
dd87eb3a 433
163ef309 434 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
435 /*
436 * If we're currently running this IRQ, or its disabled,
437 * we shouldn't process the IRQ. Mark it pending, handle
438 * the necessary masking and go out
439 */
32f4125e
TG
440 if (unlikely(irqd_irq_disabled(&desc->irq_data) ||
441 irqd_irq_inprogress(&desc->irq_data) || !desc->action)) {
fe200ae4 442 if (!irq_check_poll(desc)) {
2a0d6fb3 443 desc->istate |= IRQS_PENDING;
fe200ae4
TG
444 mask_ack_irq(desc);
445 goto out_unlock;
446 }
dd87eb3a 447 }
d6c88a50 448 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
449
450 /* Start handling the irq */
22a49163 451 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 452
dd87eb3a 453 do {
a60a5dc2 454 if (unlikely(!desc->action)) {
e2c0f8ff 455 mask_irq(desc);
dd87eb3a
TG
456 goto out_unlock;
457 }
458
459 /*
460 * When another irq arrived while we were handling
461 * one, we could have masked the irq.
462 * Renable it, if it was not disabled in meantime.
463 */
2a0d6fb3 464 if (unlikely(desc->istate & IRQS_PENDING)) {
32f4125e
TG
465 if (!irqd_irq_disabled(&desc->irq_data) &&
466 irqd_irq_masked(&desc->irq_data))
c1594b77 467 unmask_irq(desc);
dd87eb3a
TG
468 }
469
a60a5dc2 470 handle_irq_event(desc);
dd87eb3a 471
2a0d6fb3 472 } while ((desc->istate & IRQS_PENDING) &&
32f4125e 473 !irqd_irq_disabled(&desc->irq_data));
dd87eb3a 474
dd87eb3a 475out_unlock:
239007b8 476 raw_spin_unlock(&desc->lock);
dd87eb3a
TG
477}
478
0521c8fb
TG
479#ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
480/**
481 * handle_edge_eoi_irq - edge eoi type IRQ handler
482 * @irq: the interrupt number
483 * @desc: the interrupt description structure for this irq
484 *
485 * Similar as the above handle_edge_irq, but using eoi and w/o the
486 * mask/unmask logic.
487 */
488void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc)
489{
490 struct irq_chip *chip = irq_desc_get_chip(desc);
491
492 raw_spin_lock(&desc->lock);
493
494 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
495 /*
496 * If we're currently running this IRQ, or its disabled,
497 * we shouldn't process the IRQ. Mark it pending, handle
498 * the necessary masking and go out
499 */
500 if (unlikely(irqd_irq_disabled(&desc->irq_data) ||
501 irqd_irq_inprogress(&desc->irq_data) || !desc->action)) {
502 if (!irq_check_poll(desc)) {
503 desc->istate |= IRQS_PENDING;
504 goto out_eoi;
505 }
506 }
507 kstat_incr_irqs_this_cpu(irq, desc);
508
509 do {
510 if (unlikely(!desc->action))
511 goto out_eoi;
512
513 handle_irq_event(desc);
514
515 } while ((desc->istate & IRQS_PENDING) &&
516 !irqd_irq_disabled(&desc->irq_data));
517
ac0e0447 518out_eoi:
0521c8fb
TG
519 chip->irq_eoi(&desc->irq_data);
520 raw_spin_unlock(&desc->lock);
521}
522#endif
523
dd87eb3a 524/**
24b26d42 525 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a
TG
526 * @irq: the interrupt number
527 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
528 *
529 * Per CPU interrupts on SMP machines without locking requirements
530 */
7ad5b3a5 531void
7d12e780 532handle_percpu_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 533{
35e857cb 534 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 535
d6c88a50 536 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 537
849f061c
TG
538 if (chip->irq_ack)
539 chip->irq_ack(&desc->irq_data);
dd87eb3a 540
849f061c 541 handle_irq_event_percpu(desc, desc->action);
dd87eb3a 542
849f061c
TG
543 if (chip->irq_eoi)
544 chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
545}
546
dd87eb3a 547void
3836ca08 548__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
a460e745 549 const char *name)
dd87eb3a 550{
dd87eb3a 551 unsigned long flags;
02725e74 552 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags);
dd87eb3a 553
02725e74 554 if (!desc)
dd87eb3a 555 return;
dd87eb3a 556
091738a2 557 if (!handle) {
dd87eb3a 558 handle = handle_bad_irq;
091738a2
TG
559 } else {
560 if (WARN_ON(desc->irq_data.chip == &no_irq_chip))
02725e74 561 goto out;
f8b5473f 562 }
dd87eb3a 563
dd87eb3a
TG
564 /* Uninstall? */
565 if (handle == handle_bad_irq) {
6b8ff312 566 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 567 mask_ack_irq(desc);
801a0e9a 568 irq_state_set_disabled(desc);
dd87eb3a
TG
569 desc->depth = 1;
570 }
571 desc->handle_irq = handle;
a460e745 572 desc->name = name;
dd87eb3a
TG
573
574 if (handle != handle_bad_irq && is_chained) {
1ccb4e61
TG
575 irq_settings_set_noprobe(desc);
576 irq_settings_set_norequest(desc);
7f1b1244 577 irq_settings_set_nothread(desc);
46999238 578 irq_startup(desc);
dd87eb3a 579 }
02725e74
TG
580out:
581 irq_put_desc_busunlock(desc, flags);
dd87eb3a 582}
3836ca08 583EXPORT_SYMBOL_GPL(__irq_set_handler);
dd87eb3a
TG
584
585void
3836ca08 586irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
a460e745 587 irq_flow_handler_t handle, const char *name)
dd87eb3a 588{
35e857cb 589 irq_set_chip(irq, chip);
3836ca08 590 __irq_set_handler(irq, handle, 0, name);
dd87eb3a 591}
46f4f8f6 592
44247184 593void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 594{
46f4f8f6 595 unsigned long flags;
02725e74 596 struct irq_desc *desc = irq_get_desc_lock(irq, &flags);
46f4f8f6 597
44247184 598 if (!desc)
46f4f8f6 599 return;
a005677b
TG
600 irq_settings_clr_and_set(desc, clr, set);
601
876dbd4c 602 irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
e1ef8241 603 IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
a005677b
TG
604 if (irq_settings_has_no_balance_set(desc))
605 irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
606 if (irq_settings_is_per_cpu(desc))
607 irqd_set(&desc->irq_data, IRQD_PER_CPU);
e1ef8241
TG
608 if (irq_settings_can_move_pcntxt(desc))
609 irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
0ef5ca1e
TG
610 if (irq_settings_is_level(desc))
611 irqd_set(&desc->irq_data, IRQD_LEVEL);
a005677b 612
876dbd4c
TG
613 irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc));
614
02725e74 615 irq_put_desc_unlock(desc, flags);
46f4f8f6 616}
edf76f83 617EXPORT_SYMBOL_GPL(irq_modify_status);
0fdb4b25
DD
618
619/**
620 * irq_cpu_online - Invoke all irq_cpu_online functions.
621 *
622 * Iterate through all irqs and invoke the chip.irq_cpu_online()
623 * for each.
624 */
625void irq_cpu_online(void)
626{
627 struct irq_desc *desc;
628 struct irq_chip *chip;
629 unsigned long flags;
630 unsigned int irq;
631
632 for_each_active_irq(irq) {
633 desc = irq_to_desc(irq);
634 if (!desc)
635 continue;
636
637 raw_spin_lock_irqsave(&desc->lock, flags);
638
639 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
640 if (chip && chip->irq_cpu_online &&
641 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 642 !irqd_irq_disabled(&desc->irq_data)))
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DD
643 chip->irq_cpu_online(&desc->irq_data);
644
645 raw_spin_unlock_irqrestore(&desc->lock, flags);
646 }
647}
648
649/**
650 * irq_cpu_offline - Invoke all irq_cpu_offline functions.
651 *
652 * Iterate through all irqs and invoke the chip.irq_cpu_offline()
653 * for each.
654 */
655void irq_cpu_offline(void)
656{
657 struct irq_desc *desc;
658 struct irq_chip *chip;
659 unsigned long flags;
660 unsigned int irq;
661
662 for_each_active_irq(irq) {
663 desc = irq_to_desc(irq);
664 if (!desc)
665 continue;
666
667 raw_spin_lock_irqsave(&desc->lock, flags);
668
669 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
670 if (chip && chip->irq_cpu_offline &&
671 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 672 !irqd_irq_disabled(&desc->irq_data)))
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DD
673 chip->irq_cpu_offline(&desc->irq_data);
674
675 raw_spin_unlock_irqrestore(&desc->lock, flags);
676 }
677}
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