genirq: Fix long-term regression in genirq irq_set_irq_type() handling
[deliverable/linux.git] / kernel / irq / chip.c
CommitLineData
dd87eb3a
TG
1/*
2 * linux/kernel/irq/chip.c
3 *
4 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
5 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 *
7 * This file contains the core interrupt handling code, for irq-chip
8 * based architectures.
9 *
10 * Detailed information is available in Documentation/DocBook/genericirq
11 */
12
13#include <linux/irq.h>
7fe3730d 14#include <linux/msi.h>
dd87eb3a
TG
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
18
19#include "internals.h"
20
21/**
a0cd9ca2 22 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
23 * @irq: irq number
24 * @chip: pointer to irq chip description structure
25 */
a0cd9ca2 26int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 27{
dd87eb3a 28 unsigned long flags;
31d9d9b6 29 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 30
02725e74 31 if (!desc)
dd87eb3a 32 return -EINVAL;
dd87eb3a
TG
33
34 if (!chip)
35 chip = &no_irq_chip;
36
6b8ff312 37 desc->irq_data.chip = chip;
02725e74 38 irq_put_desc_unlock(desc, flags);
d72274e5
DD
39 /*
40 * For !CONFIG_SPARSE_IRQ make the irq show up in
41 * allocated_irqs. For the CONFIG_SPARSE_IRQ case, it is
42 * already marked, and this call is harmless.
43 */
44 irq_reserve_irq(irq);
dd87eb3a
TG
45 return 0;
46}
a0cd9ca2 47EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
48
49/**
a0cd9ca2 50 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 51 * @irq: irq number
0c5d1eb7 52 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 53 */
a0cd9ca2 54int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 55{
dd87eb3a 56 unsigned long flags;
31d9d9b6 57 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
02725e74 58 int ret = 0;
dd87eb3a 59
02725e74
TG
60 if (!desc)
61 return -EINVAL;
dd87eb3a 62
f2b662da 63 type &= IRQ_TYPE_SENSE_MASK;
a09b659c 64 ret = __irq_set_trigger(desc, irq, type);
02725e74 65 irq_put_desc_busunlock(desc, flags);
dd87eb3a
TG
66 return ret;
67}
a0cd9ca2 68EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
69
70/**
a0cd9ca2 71 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
72 * @irq: Interrupt number
73 * @data: Pointer to interrupt specific data
74 *
75 * Set the hardware irq controller data for an irq
76 */
a0cd9ca2 77int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 78{
dd87eb3a 79 unsigned long flags;
31d9d9b6 80 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 81
02725e74 82 if (!desc)
dd87eb3a 83 return -EINVAL;
6b8ff312 84 desc->irq_data.handler_data = data;
02725e74 85 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
86 return 0;
87}
a0cd9ca2 88EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 89
5b912c10 90/**
a0cd9ca2 91 * irq_set_msi_desc - set MSI descriptor data for an irq
5b912c10 92 * @irq: Interrupt number
472900b8 93 * @entry: Pointer to MSI descriptor data
5b912c10 94 *
24b26d42 95 * Set the MSI descriptor entry for an irq
5b912c10 96 */
a0cd9ca2 97int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
5b912c10 98{
5b912c10 99 unsigned long flags;
31d9d9b6 100 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
5b912c10 101
02725e74 102 if (!desc)
5b912c10 103 return -EINVAL;
6b8ff312 104 desc->irq_data.msi_desc = entry;
7fe3730d
ME
105 if (entry)
106 entry->irq = irq;
02725e74 107 irq_put_desc_unlock(desc, flags);
5b912c10
EB
108 return 0;
109}
110
dd87eb3a 111/**
a0cd9ca2 112 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
113 * @irq: Interrupt number
114 * @data: Pointer to chip specific data
115 *
116 * Set the hardware irq chip data for an irq
117 */
a0cd9ca2 118int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 119{
dd87eb3a 120 unsigned long flags;
31d9d9b6 121 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 122
02725e74 123 if (!desc)
dd87eb3a 124 return -EINVAL;
6b8ff312 125 desc->irq_data.chip_data = data;
02725e74 126 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
127 return 0;
128}
a0cd9ca2 129EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 130
f303a6dd
TG
131struct irq_data *irq_get_irq_data(unsigned int irq)
132{
133 struct irq_desc *desc = irq_to_desc(irq);
134
135 return desc ? &desc->irq_data : NULL;
136}
137EXPORT_SYMBOL_GPL(irq_get_irq_data);
138
c1594b77
TG
139static void irq_state_clr_disabled(struct irq_desc *desc)
140{
801a0e9a 141 irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
142}
143
144static void irq_state_set_disabled(struct irq_desc *desc)
145{
801a0e9a 146 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
147}
148
6e40262e
TG
149static void irq_state_clr_masked(struct irq_desc *desc)
150{
32f4125e 151 irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
152}
153
154static void irq_state_set_masked(struct irq_desc *desc)
155{
32f4125e 156 irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
157}
158
46999238
TG
159int irq_startup(struct irq_desc *desc)
160{
c1594b77 161 irq_state_clr_disabled(desc);
46999238
TG
162 desc->depth = 0;
163
3aae994f
TG
164 if (desc->irq_data.chip->irq_startup) {
165 int ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
6e40262e 166 irq_state_clr_masked(desc);
3aae994f
TG
167 return ret;
168 }
46999238 169
87923470 170 irq_enable(desc);
46999238
TG
171 return 0;
172}
173
174void irq_shutdown(struct irq_desc *desc)
175{
c1594b77 176 irq_state_set_disabled(desc);
46999238 177 desc->depth = 1;
50f7c032
TG
178 if (desc->irq_data.chip->irq_shutdown)
179 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
ed585a65 180 else if (desc->irq_data.chip->irq_disable)
50f7c032
TG
181 desc->irq_data.chip->irq_disable(&desc->irq_data);
182 else
183 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 184 irq_state_set_masked(desc);
46999238
TG
185}
186
87923470
TG
187void irq_enable(struct irq_desc *desc)
188{
c1594b77 189 irq_state_clr_disabled(desc);
50f7c032
TG
190 if (desc->irq_data.chip->irq_enable)
191 desc->irq_data.chip->irq_enable(&desc->irq_data);
192 else
193 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 194 irq_state_clr_masked(desc);
dd87eb3a
TG
195}
196
50f7c032 197void irq_disable(struct irq_desc *desc)
89d694b9 198{
c1594b77 199 irq_state_set_disabled(desc);
50f7c032
TG
200 if (desc->irq_data.chip->irq_disable) {
201 desc->irq_data.chip->irq_disable(&desc->irq_data);
a61d8258 202 irq_state_set_masked(desc);
50f7c032 203 }
89d694b9
TG
204}
205
31d9d9b6
MZ
206void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
207{
208 if (desc->irq_data.chip->irq_enable)
209 desc->irq_data.chip->irq_enable(&desc->irq_data);
210 else
211 desc->irq_data.chip->irq_unmask(&desc->irq_data);
212 cpumask_set_cpu(cpu, desc->percpu_enabled);
213}
214
215void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
216{
217 if (desc->irq_data.chip->irq_disable)
218 desc->irq_data.chip->irq_disable(&desc->irq_data);
219 else
220 desc->irq_data.chip->irq_mask(&desc->irq_data);
221 cpumask_clear_cpu(cpu, desc->percpu_enabled);
222}
223
9205e31d 224static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 225{
9205e31d
TG
226 if (desc->irq_data.chip->irq_mask_ack)
227 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
dd87eb3a 228 else {
e2c0f8ff 229 desc->irq_data.chip->irq_mask(&desc->irq_data);
22a49163
TG
230 if (desc->irq_data.chip->irq_ack)
231 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 232 }
6e40262e 233 irq_state_set_masked(desc);
0b1adaa0
TG
234}
235
d4d5e089 236void mask_irq(struct irq_desc *desc)
0b1adaa0 237{
e2c0f8ff
TG
238 if (desc->irq_data.chip->irq_mask) {
239 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 240 irq_state_set_masked(desc);
0b1adaa0
TG
241 }
242}
243
d4d5e089 244void unmask_irq(struct irq_desc *desc)
0b1adaa0 245{
0eda58b7
TG
246 if (desc->irq_data.chip->irq_unmask) {
247 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 248 irq_state_clr_masked(desc);
0b1adaa0 249 }
dd87eb3a
TG
250}
251
399b5da2
TG
252/*
253 * handle_nested_irq - Handle a nested irq from a irq thread
254 * @irq: the interrupt number
255 *
256 * Handle interrupts which are nested into a threaded interrupt
257 * handler. The handler function is called inside the calling
258 * threads context.
259 */
260void handle_nested_irq(unsigned int irq)
261{
262 struct irq_desc *desc = irq_to_desc(irq);
263 struct irqaction *action;
264 irqreturn_t action_ret;
265
266 might_sleep();
267
239007b8 268 raw_spin_lock_irq(&desc->lock);
399b5da2
TG
269
270 kstat_incr_irqs_this_cpu(irq, desc);
271
272 action = desc->action;
32f4125e 273 if (unlikely(!action || irqd_irq_disabled(&desc->irq_data)))
399b5da2
TG
274 goto out_unlock;
275
32f4125e 276 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
239007b8 277 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
278
279 action_ret = action->thread_fn(action->irq, action->dev_id);
280 if (!noirqdebug)
281 note_interrupt(irq, desc, action_ret);
282
239007b8 283 raw_spin_lock_irq(&desc->lock);
32f4125e 284 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
399b5da2
TG
285
286out_unlock:
239007b8 287 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
288}
289EXPORT_SYMBOL_GPL(handle_nested_irq);
290
fe200ae4
TG
291static bool irq_check_poll(struct irq_desc *desc)
292{
6954b75b 293 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
294 return false;
295 return irq_wait_for_poll(desc);
296}
297
dd87eb3a
TG
298/**
299 * handle_simple_irq - Simple and software-decoded IRQs.
300 * @irq: the interrupt number
301 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
302 *
303 * Simple interrupts are either sent from a demultiplexing interrupt
304 * handler or come from hardware, where no interrupt hardware control
305 * is necessary.
306 *
307 * Note: The caller is expected to handle the ack, clear, mask and
308 * unmask issues if necessary.
309 */
7ad5b3a5 310void
7d12e780 311handle_simple_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 312{
239007b8 313 raw_spin_lock(&desc->lock);
dd87eb3a 314
32f4125e 315 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
316 if (!irq_check_poll(desc))
317 goto out_unlock;
318
163ef309 319 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 320 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 321
32f4125e 322 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data)))
dd87eb3a
TG
323 goto out_unlock;
324
107781e7 325 handle_irq_event(desc);
dd87eb3a 326
dd87eb3a 327out_unlock:
239007b8 328 raw_spin_unlock(&desc->lock);
dd87eb3a 329}
edf76f83 330EXPORT_SYMBOL_GPL(handle_simple_irq);
dd87eb3a
TG
331
332/**
333 * handle_level_irq - Level type irq handler
334 * @irq: the interrupt number
335 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
336 *
337 * Level type interrupts are active as long as the hardware line has
338 * the active level. This may require to mask the interrupt and unmask
339 * it after the associated handler has acknowledged the device, so the
340 * interrupt line is back to inactive.
341 */
7ad5b3a5 342void
7d12e780 343handle_level_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 344{
239007b8 345 raw_spin_lock(&desc->lock);
9205e31d 346 mask_ack_irq(desc);
dd87eb3a 347
32f4125e 348 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
349 if (!irq_check_poll(desc))
350 goto out_unlock;
351
163ef309 352 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 353 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
354
355 /*
356 * If its disabled or no action available
357 * keep it masked and get out of here
358 */
32f4125e 359 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data)))
86998aa6 360 goto out_unlock;
dd87eb3a 361
1529866c 362 handle_irq_event(desc);
b25c340c 363
32f4125e 364 if (!irqd_irq_disabled(&desc->irq_data) && !(desc->istate & IRQS_ONESHOT))
0eda58b7 365 unmask_irq(desc);
86998aa6 366out_unlock:
239007b8 367 raw_spin_unlock(&desc->lock);
dd87eb3a 368}
14819ea1 369EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a 370
78129576
TG
371#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
372static inline void preflow_handler(struct irq_desc *desc)
373{
374 if (desc->preflow_handler)
375 desc->preflow_handler(&desc->irq_data);
376}
377#else
378static inline void preflow_handler(struct irq_desc *desc) { }
379#endif
380
dd87eb3a 381/**
47c2a3aa 382 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a
TG
383 * @irq: the interrupt number
384 * @desc: the interrupt description structure for this irq
dd87eb3a 385 *
47c2a3aa 386 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
387 * call when the interrupt has been serviced. This enables support
388 * for modern forms of interrupt handlers, which handle the flow
389 * details in hardware, transparently.
390 */
7ad5b3a5 391void
7d12e780 392handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 393{
239007b8 394 raw_spin_lock(&desc->lock);
dd87eb3a 395
32f4125e 396 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
397 if (!irq_check_poll(desc))
398 goto out;
dd87eb3a 399
163ef309 400 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 401 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
402
403 /*
404 * If its disabled or no action available
76d21601 405 * then mask it and get out of here:
dd87eb3a 406 */
32f4125e 407 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
2a0d6fb3 408 desc->istate |= IRQS_PENDING;
e2c0f8ff 409 mask_irq(desc);
dd87eb3a 410 goto out;
98bb244b 411 }
c69e3758
TG
412
413 if (desc->istate & IRQS_ONESHOT)
414 mask_irq(desc);
415
78129576 416 preflow_handler(desc);
a7ae4de5 417 handle_irq_event(desc);
77694b40
TG
418
419out_eoi:
0c5c1557 420 desc->irq_data.chip->irq_eoi(&desc->irq_data);
77694b40 421out_unlock:
239007b8 422 raw_spin_unlock(&desc->lock);
77694b40
TG
423 return;
424out:
425 if (!(desc->irq_data.chip->flags & IRQCHIP_EOI_IF_HANDLED))
426 goto out_eoi;
427 goto out_unlock;
dd87eb3a
TG
428}
429
430/**
431 * handle_edge_irq - edge type IRQ handler
432 * @irq: the interrupt number
433 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
434 *
435 * Interrupt occures on the falling and/or rising edge of a hardware
25985edc 436 * signal. The occurrence is latched into the irq controller hardware
dd87eb3a
TG
437 * and must be acked in order to be reenabled. After the ack another
438 * interrupt can happen on the same source even before the first one
dfff0615 439 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
440 * might be necessary to disable (mask) the interrupt depending on the
441 * controller hardware. This requires to reenable the interrupt inside
442 * of the loop which handles the interrupts which have arrived while
443 * the handler was running. If all pending interrupts are handled, the
444 * loop is left.
445 */
7ad5b3a5 446void
7d12e780 447handle_edge_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 448{
239007b8 449 raw_spin_lock(&desc->lock);
dd87eb3a 450
163ef309 451 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
452 /*
453 * If we're currently running this IRQ, or its disabled,
454 * we shouldn't process the IRQ. Mark it pending, handle
455 * the necessary masking and go out
456 */
32f4125e
TG
457 if (unlikely(irqd_irq_disabled(&desc->irq_data) ||
458 irqd_irq_inprogress(&desc->irq_data) || !desc->action)) {
fe200ae4 459 if (!irq_check_poll(desc)) {
2a0d6fb3 460 desc->istate |= IRQS_PENDING;
fe200ae4
TG
461 mask_ack_irq(desc);
462 goto out_unlock;
463 }
dd87eb3a 464 }
d6c88a50 465 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
466
467 /* Start handling the irq */
22a49163 468 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 469
dd87eb3a 470 do {
a60a5dc2 471 if (unlikely(!desc->action)) {
e2c0f8ff 472 mask_irq(desc);
dd87eb3a
TG
473 goto out_unlock;
474 }
475
476 /*
477 * When another irq arrived while we were handling
478 * one, we could have masked the irq.
479 * Renable it, if it was not disabled in meantime.
480 */
2a0d6fb3 481 if (unlikely(desc->istate & IRQS_PENDING)) {
32f4125e
TG
482 if (!irqd_irq_disabled(&desc->irq_data) &&
483 irqd_irq_masked(&desc->irq_data))
c1594b77 484 unmask_irq(desc);
dd87eb3a
TG
485 }
486
a60a5dc2 487 handle_irq_event(desc);
dd87eb3a 488
2a0d6fb3 489 } while ((desc->istate & IRQS_PENDING) &&
32f4125e 490 !irqd_irq_disabled(&desc->irq_data));
dd87eb3a 491
dd87eb3a 492out_unlock:
239007b8 493 raw_spin_unlock(&desc->lock);
dd87eb3a
TG
494}
495
0521c8fb
TG
496#ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
497/**
498 * handle_edge_eoi_irq - edge eoi type IRQ handler
499 * @irq: the interrupt number
500 * @desc: the interrupt description structure for this irq
501 *
502 * Similar as the above handle_edge_irq, but using eoi and w/o the
503 * mask/unmask logic.
504 */
505void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc)
506{
507 struct irq_chip *chip = irq_desc_get_chip(desc);
508
509 raw_spin_lock(&desc->lock);
510
511 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
512 /*
513 * If we're currently running this IRQ, or its disabled,
514 * we shouldn't process the IRQ. Mark it pending, handle
515 * the necessary masking and go out
516 */
517 if (unlikely(irqd_irq_disabled(&desc->irq_data) ||
518 irqd_irq_inprogress(&desc->irq_data) || !desc->action)) {
519 if (!irq_check_poll(desc)) {
520 desc->istate |= IRQS_PENDING;
521 goto out_eoi;
522 }
523 }
524 kstat_incr_irqs_this_cpu(irq, desc);
525
526 do {
527 if (unlikely(!desc->action))
528 goto out_eoi;
529
530 handle_irq_event(desc);
531
532 } while ((desc->istate & IRQS_PENDING) &&
533 !irqd_irq_disabled(&desc->irq_data));
534
ac0e0447 535out_eoi:
0521c8fb
TG
536 chip->irq_eoi(&desc->irq_data);
537 raw_spin_unlock(&desc->lock);
538}
539#endif
540
dd87eb3a 541/**
24b26d42 542 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a
TG
543 * @irq: the interrupt number
544 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
545 *
546 * Per CPU interrupts on SMP machines without locking requirements
547 */
7ad5b3a5 548void
7d12e780 549handle_percpu_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 550{
35e857cb 551 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 552
d6c88a50 553 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 554
849f061c
TG
555 if (chip->irq_ack)
556 chip->irq_ack(&desc->irq_data);
dd87eb3a 557
849f061c 558 handle_irq_event_percpu(desc, desc->action);
dd87eb3a 559
849f061c
TG
560 if (chip->irq_eoi)
561 chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
562}
563
31d9d9b6
MZ
564/**
565 * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
566 * @irq: the interrupt number
567 * @desc: the interrupt description structure for this irq
568 *
569 * Per CPU interrupts on SMP machines without locking requirements. Same as
570 * handle_percpu_irq() above but with the following extras:
571 *
572 * action->percpu_dev_id is a pointer to percpu variables which
573 * contain the real device id for the cpu on which this handler is
574 * called
575 */
576void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc)
577{
578 struct irq_chip *chip = irq_desc_get_chip(desc);
579 struct irqaction *action = desc->action;
580 void *dev_id = __this_cpu_ptr(action->percpu_dev_id);
581 irqreturn_t res;
582
583 kstat_incr_irqs_this_cpu(irq, desc);
584
585 if (chip->irq_ack)
586 chip->irq_ack(&desc->irq_data);
587
588 trace_irq_handler_entry(irq, action);
589 res = action->handler(irq, dev_id);
590 trace_irq_handler_exit(irq, action, res);
591
592 if (chip->irq_eoi)
593 chip->irq_eoi(&desc->irq_data);
594}
595
dd87eb3a 596void
3836ca08 597__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
a460e745 598 const char *name)
dd87eb3a 599{
dd87eb3a 600 unsigned long flags;
31d9d9b6 601 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
dd87eb3a 602
02725e74 603 if (!desc)
dd87eb3a 604 return;
dd87eb3a 605
091738a2 606 if (!handle) {
dd87eb3a 607 handle = handle_bad_irq;
091738a2
TG
608 } else {
609 if (WARN_ON(desc->irq_data.chip == &no_irq_chip))
02725e74 610 goto out;
f8b5473f 611 }
dd87eb3a 612
dd87eb3a
TG
613 /* Uninstall? */
614 if (handle == handle_bad_irq) {
6b8ff312 615 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 616 mask_ack_irq(desc);
801a0e9a 617 irq_state_set_disabled(desc);
dd87eb3a
TG
618 desc->depth = 1;
619 }
620 desc->handle_irq = handle;
a460e745 621 desc->name = name;
dd87eb3a
TG
622
623 if (handle != handle_bad_irq && is_chained) {
1ccb4e61
TG
624 irq_settings_set_noprobe(desc);
625 irq_settings_set_norequest(desc);
7f1b1244 626 irq_settings_set_nothread(desc);
46999238 627 irq_startup(desc);
dd87eb3a 628 }
02725e74
TG
629out:
630 irq_put_desc_busunlock(desc, flags);
dd87eb3a 631}
3836ca08 632EXPORT_SYMBOL_GPL(__irq_set_handler);
dd87eb3a
TG
633
634void
3836ca08 635irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
a460e745 636 irq_flow_handler_t handle, const char *name)
dd87eb3a 637{
35e857cb 638 irq_set_chip(irq, chip);
3836ca08 639 __irq_set_handler(irq, handle, 0, name);
dd87eb3a 640}
46f4f8f6 641
44247184 642void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 643{
46f4f8f6 644 unsigned long flags;
31d9d9b6 645 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
46f4f8f6 646
44247184 647 if (!desc)
46f4f8f6 648 return;
a005677b
TG
649 irq_settings_clr_and_set(desc, clr, set);
650
876dbd4c 651 irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
e1ef8241 652 IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
a005677b
TG
653 if (irq_settings_has_no_balance_set(desc))
654 irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
655 if (irq_settings_is_per_cpu(desc))
656 irqd_set(&desc->irq_data, IRQD_PER_CPU);
e1ef8241
TG
657 if (irq_settings_can_move_pcntxt(desc))
658 irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
0ef5ca1e
TG
659 if (irq_settings_is_level(desc))
660 irqd_set(&desc->irq_data, IRQD_LEVEL);
a005677b 661
876dbd4c
TG
662 irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc));
663
02725e74 664 irq_put_desc_unlock(desc, flags);
46f4f8f6 665}
edf76f83 666EXPORT_SYMBOL_GPL(irq_modify_status);
0fdb4b25
DD
667
668/**
669 * irq_cpu_online - Invoke all irq_cpu_online functions.
670 *
671 * Iterate through all irqs and invoke the chip.irq_cpu_online()
672 * for each.
673 */
674void irq_cpu_online(void)
675{
676 struct irq_desc *desc;
677 struct irq_chip *chip;
678 unsigned long flags;
679 unsigned int irq;
680
681 for_each_active_irq(irq) {
682 desc = irq_to_desc(irq);
683 if (!desc)
684 continue;
685
686 raw_spin_lock_irqsave(&desc->lock, flags);
687
688 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
689 if (chip && chip->irq_cpu_online &&
690 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 691 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
692 chip->irq_cpu_online(&desc->irq_data);
693
694 raw_spin_unlock_irqrestore(&desc->lock, flags);
695 }
696}
697
698/**
699 * irq_cpu_offline - Invoke all irq_cpu_offline functions.
700 *
701 * Iterate through all irqs and invoke the chip.irq_cpu_offline()
702 * for each.
703 */
704void irq_cpu_offline(void)
705{
706 struct irq_desc *desc;
707 struct irq_chip *chip;
708 unsigned long flags;
709 unsigned int irq;
710
711 for_each_active_irq(irq) {
712 desc = irq_to_desc(irq);
713 if (!desc)
714 continue;
715
716 raw_spin_lock_irqsave(&desc->lock, flags);
717
718 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
719 if (chip && chip->irq_cpu_offline &&
720 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 721 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
722 chip->irq_cpu_offline(&desc->irq_data);
723
724 raw_spin_unlock_irqrestore(&desc->lock, flags);
725 }
726}
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