genirq: Unmask oneshot irqs when thread was not woken
[deliverable/linux.git] / kernel / irq / chip.c
CommitLineData
dd87eb3a
TG
1/*
2 * linux/kernel/irq/chip.c
3 *
4 * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar
5 * Copyright (C) 2005-2006, Thomas Gleixner, Russell King
6 *
7 * This file contains the core interrupt handling code, for irq-chip
8 * based architectures.
9 *
10 * Detailed information is available in Documentation/DocBook/genericirq
11 */
12
13#include <linux/irq.h>
7fe3730d 14#include <linux/msi.h>
dd87eb3a
TG
15#include <linux/module.h>
16#include <linux/interrupt.h>
17#include <linux/kernel_stat.h>
18
19#include "internals.h"
20
21/**
a0cd9ca2 22 * irq_set_chip - set the irq chip for an irq
dd87eb3a
TG
23 * @irq: irq number
24 * @chip: pointer to irq chip description structure
25 */
a0cd9ca2 26int irq_set_chip(unsigned int irq, struct irq_chip *chip)
dd87eb3a 27{
dd87eb3a 28 unsigned long flags;
31d9d9b6 29 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 30
02725e74 31 if (!desc)
dd87eb3a 32 return -EINVAL;
dd87eb3a
TG
33
34 if (!chip)
35 chip = &no_irq_chip;
36
6b8ff312 37 desc->irq_data.chip = chip;
02725e74 38 irq_put_desc_unlock(desc, flags);
d72274e5
DD
39 /*
40 * For !CONFIG_SPARSE_IRQ make the irq show up in
41 * allocated_irqs. For the CONFIG_SPARSE_IRQ case, it is
42 * already marked, and this call is harmless.
43 */
44 irq_reserve_irq(irq);
dd87eb3a
TG
45 return 0;
46}
a0cd9ca2 47EXPORT_SYMBOL(irq_set_chip);
dd87eb3a
TG
48
49/**
a0cd9ca2 50 * irq_set_type - set the irq trigger type for an irq
dd87eb3a 51 * @irq: irq number
0c5d1eb7 52 * @type: IRQ_TYPE_{LEVEL,EDGE}_* value - see include/linux/irq.h
dd87eb3a 53 */
a0cd9ca2 54int irq_set_irq_type(unsigned int irq, unsigned int type)
dd87eb3a 55{
dd87eb3a 56 unsigned long flags;
31d9d9b6 57 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
02725e74 58 int ret = 0;
dd87eb3a 59
02725e74
TG
60 if (!desc)
61 return -EINVAL;
dd87eb3a 62
f2b662da 63 type &= IRQ_TYPE_SENSE_MASK;
02725e74
TG
64 if (type != IRQ_TYPE_NONE)
65 ret = __irq_set_trigger(desc, irq, type);
66 irq_put_desc_busunlock(desc, flags);
dd87eb3a
TG
67 return ret;
68}
a0cd9ca2 69EXPORT_SYMBOL(irq_set_irq_type);
dd87eb3a
TG
70
71/**
a0cd9ca2 72 * irq_set_handler_data - set irq handler data for an irq
dd87eb3a
TG
73 * @irq: Interrupt number
74 * @data: Pointer to interrupt specific data
75 *
76 * Set the hardware irq controller data for an irq
77 */
a0cd9ca2 78int irq_set_handler_data(unsigned int irq, void *data)
dd87eb3a 79{
dd87eb3a 80 unsigned long flags;
31d9d9b6 81 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 82
02725e74 83 if (!desc)
dd87eb3a 84 return -EINVAL;
6b8ff312 85 desc->irq_data.handler_data = data;
02725e74 86 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
87 return 0;
88}
a0cd9ca2 89EXPORT_SYMBOL(irq_set_handler_data);
dd87eb3a 90
5b912c10 91/**
a0cd9ca2 92 * irq_set_msi_desc - set MSI descriptor data for an irq
5b912c10 93 * @irq: Interrupt number
472900b8 94 * @entry: Pointer to MSI descriptor data
5b912c10 95 *
24b26d42 96 * Set the MSI descriptor entry for an irq
5b912c10 97 */
a0cd9ca2 98int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry)
5b912c10 99{
5b912c10 100 unsigned long flags;
31d9d9b6 101 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL);
5b912c10 102
02725e74 103 if (!desc)
5b912c10 104 return -EINVAL;
6b8ff312 105 desc->irq_data.msi_desc = entry;
7fe3730d
ME
106 if (entry)
107 entry->irq = irq;
02725e74 108 irq_put_desc_unlock(desc, flags);
5b912c10
EB
109 return 0;
110}
111
dd87eb3a 112/**
a0cd9ca2 113 * irq_set_chip_data - set irq chip data for an irq
dd87eb3a
TG
114 * @irq: Interrupt number
115 * @data: Pointer to chip specific data
116 *
117 * Set the hardware irq chip data for an irq
118 */
a0cd9ca2 119int irq_set_chip_data(unsigned int irq, void *data)
dd87eb3a 120{
dd87eb3a 121 unsigned long flags;
31d9d9b6 122 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
dd87eb3a 123
02725e74 124 if (!desc)
dd87eb3a 125 return -EINVAL;
6b8ff312 126 desc->irq_data.chip_data = data;
02725e74 127 irq_put_desc_unlock(desc, flags);
dd87eb3a
TG
128 return 0;
129}
a0cd9ca2 130EXPORT_SYMBOL(irq_set_chip_data);
dd87eb3a 131
f303a6dd
TG
132struct irq_data *irq_get_irq_data(unsigned int irq)
133{
134 struct irq_desc *desc = irq_to_desc(irq);
135
136 return desc ? &desc->irq_data : NULL;
137}
138EXPORT_SYMBOL_GPL(irq_get_irq_data);
139
c1594b77
TG
140static void irq_state_clr_disabled(struct irq_desc *desc)
141{
801a0e9a 142 irqd_clear(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
143}
144
145static void irq_state_set_disabled(struct irq_desc *desc)
146{
801a0e9a 147 irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
c1594b77
TG
148}
149
6e40262e
TG
150static void irq_state_clr_masked(struct irq_desc *desc)
151{
32f4125e 152 irqd_clear(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
153}
154
155static void irq_state_set_masked(struct irq_desc *desc)
156{
32f4125e 157 irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
6e40262e
TG
158}
159
46999238
TG
160int irq_startup(struct irq_desc *desc)
161{
c1594b77 162 irq_state_clr_disabled(desc);
46999238
TG
163 desc->depth = 0;
164
3aae994f
TG
165 if (desc->irq_data.chip->irq_startup) {
166 int ret = desc->irq_data.chip->irq_startup(&desc->irq_data);
6e40262e 167 irq_state_clr_masked(desc);
3aae994f
TG
168 return ret;
169 }
46999238 170
87923470 171 irq_enable(desc);
46999238
TG
172 return 0;
173}
174
175void irq_shutdown(struct irq_desc *desc)
176{
c1594b77 177 irq_state_set_disabled(desc);
46999238 178 desc->depth = 1;
50f7c032
TG
179 if (desc->irq_data.chip->irq_shutdown)
180 desc->irq_data.chip->irq_shutdown(&desc->irq_data);
ed585a65 181 else if (desc->irq_data.chip->irq_disable)
50f7c032
TG
182 desc->irq_data.chip->irq_disable(&desc->irq_data);
183 else
184 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 185 irq_state_set_masked(desc);
46999238
TG
186}
187
87923470
TG
188void irq_enable(struct irq_desc *desc)
189{
c1594b77 190 irq_state_clr_disabled(desc);
50f7c032
TG
191 if (desc->irq_data.chip->irq_enable)
192 desc->irq_data.chip->irq_enable(&desc->irq_data);
193 else
194 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 195 irq_state_clr_masked(desc);
dd87eb3a
TG
196}
197
50f7c032 198void irq_disable(struct irq_desc *desc)
89d694b9 199{
c1594b77 200 irq_state_set_disabled(desc);
50f7c032
TG
201 if (desc->irq_data.chip->irq_disable) {
202 desc->irq_data.chip->irq_disable(&desc->irq_data);
a61d8258 203 irq_state_set_masked(desc);
50f7c032 204 }
89d694b9
TG
205}
206
31d9d9b6
MZ
207void irq_percpu_enable(struct irq_desc *desc, unsigned int cpu)
208{
209 if (desc->irq_data.chip->irq_enable)
210 desc->irq_data.chip->irq_enable(&desc->irq_data);
211 else
212 desc->irq_data.chip->irq_unmask(&desc->irq_data);
213 cpumask_set_cpu(cpu, desc->percpu_enabled);
214}
215
216void irq_percpu_disable(struct irq_desc *desc, unsigned int cpu)
217{
218 if (desc->irq_data.chip->irq_disable)
219 desc->irq_data.chip->irq_disable(&desc->irq_data);
220 else
221 desc->irq_data.chip->irq_mask(&desc->irq_data);
222 cpumask_clear_cpu(cpu, desc->percpu_enabled);
223}
224
9205e31d 225static inline void mask_ack_irq(struct irq_desc *desc)
dd87eb3a 226{
9205e31d
TG
227 if (desc->irq_data.chip->irq_mask_ack)
228 desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
dd87eb3a 229 else {
e2c0f8ff 230 desc->irq_data.chip->irq_mask(&desc->irq_data);
22a49163
TG
231 if (desc->irq_data.chip->irq_ack)
232 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 233 }
6e40262e 234 irq_state_set_masked(desc);
0b1adaa0
TG
235}
236
d4d5e089 237void mask_irq(struct irq_desc *desc)
0b1adaa0 238{
e2c0f8ff
TG
239 if (desc->irq_data.chip->irq_mask) {
240 desc->irq_data.chip->irq_mask(&desc->irq_data);
6e40262e 241 irq_state_set_masked(desc);
0b1adaa0
TG
242 }
243}
244
d4d5e089 245void unmask_irq(struct irq_desc *desc)
0b1adaa0 246{
0eda58b7
TG
247 if (desc->irq_data.chip->irq_unmask) {
248 desc->irq_data.chip->irq_unmask(&desc->irq_data);
6e40262e 249 irq_state_clr_masked(desc);
0b1adaa0 250 }
dd87eb3a
TG
251}
252
399b5da2
TG
253/*
254 * handle_nested_irq - Handle a nested irq from a irq thread
255 * @irq: the interrupt number
256 *
257 * Handle interrupts which are nested into a threaded interrupt
258 * handler. The handler function is called inside the calling
259 * threads context.
260 */
261void handle_nested_irq(unsigned int irq)
262{
263 struct irq_desc *desc = irq_to_desc(irq);
264 struct irqaction *action;
265 irqreturn_t action_ret;
266
267 might_sleep();
268
239007b8 269 raw_spin_lock_irq(&desc->lock);
399b5da2
TG
270
271 kstat_incr_irqs_this_cpu(irq, desc);
272
273 action = desc->action;
32f4125e 274 if (unlikely(!action || irqd_irq_disabled(&desc->irq_data)))
399b5da2
TG
275 goto out_unlock;
276
32f4125e 277 irqd_set(&desc->irq_data, IRQD_IRQ_INPROGRESS);
239007b8 278 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
279
280 action_ret = action->thread_fn(action->irq, action->dev_id);
281 if (!noirqdebug)
282 note_interrupt(irq, desc, action_ret);
283
239007b8 284 raw_spin_lock_irq(&desc->lock);
32f4125e 285 irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS);
399b5da2
TG
286
287out_unlock:
239007b8 288 raw_spin_unlock_irq(&desc->lock);
399b5da2
TG
289}
290EXPORT_SYMBOL_GPL(handle_nested_irq);
291
fe200ae4
TG
292static bool irq_check_poll(struct irq_desc *desc)
293{
6954b75b 294 if (!(desc->istate & IRQS_POLL_INPROGRESS))
fe200ae4
TG
295 return false;
296 return irq_wait_for_poll(desc);
297}
298
dd87eb3a
TG
299/**
300 * handle_simple_irq - Simple and software-decoded IRQs.
301 * @irq: the interrupt number
302 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
303 *
304 * Simple interrupts are either sent from a demultiplexing interrupt
305 * handler or come from hardware, where no interrupt hardware control
306 * is necessary.
307 *
308 * Note: The caller is expected to handle the ack, clear, mask and
309 * unmask issues if necessary.
310 */
7ad5b3a5 311void
7d12e780 312handle_simple_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 313{
239007b8 314 raw_spin_lock(&desc->lock);
dd87eb3a 315
32f4125e 316 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
317 if (!irq_check_poll(desc))
318 goto out_unlock;
319
163ef309 320 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 321 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 322
32f4125e 323 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data)))
dd87eb3a
TG
324 goto out_unlock;
325
107781e7 326 handle_irq_event(desc);
dd87eb3a 327
dd87eb3a 328out_unlock:
239007b8 329 raw_spin_unlock(&desc->lock);
dd87eb3a 330}
edf76f83 331EXPORT_SYMBOL_GPL(handle_simple_irq);
dd87eb3a 332
ac563761
TG
333/*
334 * Called unconditionally from handle_level_irq() and only for oneshot
335 * interrupts from handle_fasteoi_irq()
336 */
337static void cond_unmask_irq(struct irq_desc *desc)
338{
339 /*
340 * We need to unmask in the following cases:
341 * - Standard level irq (IRQF_ONESHOT is not set)
342 * - Oneshot irq which did not wake the thread (caused by a
343 * spurious interrupt or a primary handler handling it
344 * completely).
345 */
346 if (!irqd_irq_disabled(&desc->irq_data) &&
347 irqd_irq_masked(&desc->irq_data) && !desc->threads_oneshot)
348 unmask_irq(desc);
349}
350
dd87eb3a
TG
351/**
352 * handle_level_irq - Level type irq handler
353 * @irq: the interrupt number
354 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
355 *
356 * Level type interrupts are active as long as the hardware line has
357 * the active level. This may require to mask the interrupt and unmask
358 * it after the associated handler has acknowledged the device, so the
359 * interrupt line is back to inactive.
360 */
7ad5b3a5 361void
7d12e780 362handle_level_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 363{
239007b8 364 raw_spin_lock(&desc->lock);
9205e31d 365 mask_ack_irq(desc);
dd87eb3a 366
32f4125e 367 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
368 if (!irq_check_poll(desc))
369 goto out_unlock;
370
163ef309 371 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 372 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
373
374 /*
375 * If its disabled or no action available
376 * keep it masked and get out of here
377 */
32f4125e 378 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data)))
86998aa6 379 goto out_unlock;
dd87eb3a 380
1529866c 381 handle_irq_event(desc);
b25c340c 382
ac563761
TG
383 cond_unmask_irq(desc);
384
86998aa6 385out_unlock:
239007b8 386 raw_spin_unlock(&desc->lock);
dd87eb3a 387}
14819ea1 388EXPORT_SYMBOL_GPL(handle_level_irq);
dd87eb3a 389
78129576
TG
390#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
391static inline void preflow_handler(struct irq_desc *desc)
392{
393 if (desc->preflow_handler)
394 desc->preflow_handler(&desc->irq_data);
395}
396#else
397static inline void preflow_handler(struct irq_desc *desc) { }
398#endif
399
dd87eb3a 400/**
47c2a3aa 401 * handle_fasteoi_irq - irq handler for transparent controllers
dd87eb3a
TG
402 * @irq: the interrupt number
403 * @desc: the interrupt description structure for this irq
dd87eb3a 404 *
47c2a3aa 405 * Only a single callback will be issued to the chip: an ->eoi()
dd87eb3a
TG
406 * call when the interrupt has been serviced. This enables support
407 * for modern forms of interrupt handlers, which handle the flow
408 * details in hardware, transparently.
409 */
7ad5b3a5 410void
7d12e780 411handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 412{
239007b8 413 raw_spin_lock(&desc->lock);
dd87eb3a 414
32f4125e 415 if (unlikely(irqd_irq_inprogress(&desc->irq_data)))
fe200ae4
TG
416 if (!irq_check_poll(desc))
417 goto out;
dd87eb3a 418
163ef309 419 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
d6c88a50 420 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
421
422 /*
423 * If its disabled or no action available
76d21601 424 * then mask it and get out of here:
dd87eb3a 425 */
32f4125e 426 if (unlikely(!desc->action || irqd_irq_disabled(&desc->irq_data))) {
2a0d6fb3 427 desc->istate |= IRQS_PENDING;
e2c0f8ff 428 mask_irq(desc);
dd87eb3a 429 goto out;
98bb244b 430 }
c69e3758
TG
431
432 if (desc->istate & IRQS_ONESHOT)
433 mask_irq(desc);
434
78129576 435 preflow_handler(desc);
a7ae4de5 436 handle_irq_event(desc);
77694b40 437
ac563761
TG
438 if (desc->istate & IRQS_ONESHOT)
439 cond_unmask_irq(desc);
440
77694b40 441out_eoi:
0c5c1557 442 desc->irq_data.chip->irq_eoi(&desc->irq_data);
77694b40 443out_unlock:
239007b8 444 raw_spin_unlock(&desc->lock);
77694b40
TG
445 return;
446out:
447 if (!(desc->irq_data.chip->flags & IRQCHIP_EOI_IF_HANDLED))
448 goto out_eoi;
449 goto out_unlock;
dd87eb3a
TG
450}
451
452/**
453 * handle_edge_irq - edge type IRQ handler
454 * @irq: the interrupt number
455 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
456 *
457 * Interrupt occures on the falling and/or rising edge of a hardware
25985edc 458 * signal. The occurrence is latched into the irq controller hardware
dd87eb3a
TG
459 * and must be acked in order to be reenabled. After the ack another
460 * interrupt can happen on the same source even before the first one
dfff0615 461 * is handled by the associated event handler. If this happens it
dd87eb3a
TG
462 * might be necessary to disable (mask) the interrupt depending on the
463 * controller hardware. This requires to reenable the interrupt inside
464 * of the loop which handles the interrupts which have arrived while
465 * the handler was running. If all pending interrupts are handled, the
466 * loop is left.
467 */
7ad5b3a5 468void
7d12e780 469handle_edge_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 470{
239007b8 471 raw_spin_lock(&desc->lock);
dd87eb3a 472
163ef309 473 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
dd87eb3a
TG
474 /*
475 * If we're currently running this IRQ, or its disabled,
476 * we shouldn't process the IRQ. Mark it pending, handle
477 * the necessary masking and go out
478 */
32f4125e
TG
479 if (unlikely(irqd_irq_disabled(&desc->irq_data) ||
480 irqd_irq_inprogress(&desc->irq_data) || !desc->action)) {
fe200ae4 481 if (!irq_check_poll(desc)) {
2a0d6fb3 482 desc->istate |= IRQS_PENDING;
fe200ae4
TG
483 mask_ack_irq(desc);
484 goto out_unlock;
485 }
dd87eb3a 486 }
d6c88a50 487 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a
TG
488
489 /* Start handling the irq */
22a49163 490 desc->irq_data.chip->irq_ack(&desc->irq_data);
dd87eb3a 491
dd87eb3a 492 do {
a60a5dc2 493 if (unlikely(!desc->action)) {
e2c0f8ff 494 mask_irq(desc);
dd87eb3a
TG
495 goto out_unlock;
496 }
497
498 /*
499 * When another irq arrived while we were handling
500 * one, we could have masked the irq.
501 * Renable it, if it was not disabled in meantime.
502 */
2a0d6fb3 503 if (unlikely(desc->istate & IRQS_PENDING)) {
32f4125e
TG
504 if (!irqd_irq_disabled(&desc->irq_data) &&
505 irqd_irq_masked(&desc->irq_data))
c1594b77 506 unmask_irq(desc);
dd87eb3a
TG
507 }
508
a60a5dc2 509 handle_irq_event(desc);
dd87eb3a 510
2a0d6fb3 511 } while ((desc->istate & IRQS_PENDING) &&
32f4125e 512 !irqd_irq_disabled(&desc->irq_data));
dd87eb3a 513
dd87eb3a 514out_unlock:
239007b8 515 raw_spin_unlock(&desc->lock);
dd87eb3a
TG
516}
517
0521c8fb
TG
518#ifdef CONFIG_IRQ_EDGE_EOI_HANDLER
519/**
520 * handle_edge_eoi_irq - edge eoi type IRQ handler
521 * @irq: the interrupt number
522 * @desc: the interrupt description structure for this irq
523 *
524 * Similar as the above handle_edge_irq, but using eoi and w/o the
525 * mask/unmask logic.
526 */
527void handle_edge_eoi_irq(unsigned int irq, struct irq_desc *desc)
528{
529 struct irq_chip *chip = irq_desc_get_chip(desc);
530
531 raw_spin_lock(&desc->lock);
532
533 desc->istate &= ~(IRQS_REPLAY | IRQS_WAITING);
534 /*
535 * If we're currently running this IRQ, or its disabled,
536 * we shouldn't process the IRQ. Mark it pending, handle
537 * the necessary masking and go out
538 */
539 if (unlikely(irqd_irq_disabled(&desc->irq_data) ||
540 irqd_irq_inprogress(&desc->irq_data) || !desc->action)) {
541 if (!irq_check_poll(desc)) {
542 desc->istate |= IRQS_PENDING;
543 goto out_eoi;
544 }
545 }
546 kstat_incr_irqs_this_cpu(irq, desc);
547
548 do {
549 if (unlikely(!desc->action))
550 goto out_eoi;
551
552 handle_irq_event(desc);
553
554 } while ((desc->istate & IRQS_PENDING) &&
555 !irqd_irq_disabled(&desc->irq_data));
556
ac0e0447 557out_eoi:
0521c8fb
TG
558 chip->irq_eoi(&desc->irq_data);
559 raw_spin_unlock(&desc->lock);
560}
561#endif
562
dd87eb3a 563/**
24b26d42 564 * handle_percpu_irq - Per CPU local irq handler
dd87eb3a
TG
565 * @irq: the interrupt number
566 * @desc: the interrupt description structure for this irq
dd87eb3a
TG
567 *
568 * Per CPU interrupts on SMP machines without locking requirements
569 */
7ad5b3a5 570void
7d12e780 571handle_percpu_irq(unsigned int irq, struct irq_desc *desc)
dd87eb3a 572{
35e857cb 573 struct irq_chip *chip = irq_desc_get_chip(desc);
dd87eb3a 574
d6c88a50 575 kstat_incr_irqs_this_cpu(irq, desc);
dd87eb3a 576
849f061c
TG
577 if (chip->irq_ack)
578 chip->irq_ack(&desc->irq_data);
dd87eb3a 579
849f061c 580 handle_irq_event_percpu(desc, desc->action);
dd87eb3a 581
849f061c
TG
582 if (chip->irq_eoi)
583 chip->irq_eoi(&desc->irq_data);
dd87eb3a
TG
584}
585
31d9d9b6
MZ
586/**
587 * handle_percpu_devid_irq - Per CPU local irq handler with per cpu dev ids
588 * @irq: the interrupt number
589 * @desc: the interrupt description structure for this irq
590 *
591 * Per CPU interrupts on SMP machines without locking requirements. Same as
592 * handle_percpu_irq() above but with the following extras:
593 *
594 * action->percpu_dev_id is a pointer to percpu variables which
595 * contain the real device id for the cpu on which this handler is
596 * called
597 */
598void handle_percpu_devid_irq(unsigned int irq, struct irq_desc *desc)
599{
600 struct irq_chip *chip = irq_desc_get_chip(desc);
601 struct irqaction *action = desc->action;
602 void *dev_id = __this_cpu_ptr(action->percpu_dev_id);
603 irqreturn_t res;
604
605 kstat_incr_irqs_this_cpu(irq, desc);
606
607 if (chip->irq_ack)
608 chip->irq_ack(&desc->irq_data);
609
610 trace_irq_handler_entry(irq, action);
611 res = action->handler(irq, dev_id);
612 trace_irq_handler_exit(irq, action, res);
613
614 if (chip->irq_eoi)
615 chip->irq_eoi(&desc->irq_data);
616}
617
dd87eb3a 618void
3836ca08 619__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
a460e745 620 const char *name)
dd87eb3a 621{
dd87eb3a 622 unsigned long flags;
31d9d9b6 623 struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, 0);
dd87eb3a 624
02725e74 625 if (!desc)
dd87eb3a 626 return;
dd87eb3a 627
091738a2 628 if (!handle) {
dd87eb3a 629 handle = handle_bad_irq;
091738a2
TG
630 } else {
631 if (WARN_ON(desc->irq_data.chip == &no_irq_chip))
02725e74 632 goto out;
f8b5473f 633 }
dd87eb3a 634
dd87eb3a
TG
635 /* Uninstall? */
636 if (handle == handle_bad_irq) {
6b8ff312 637 if (desc->irq_data.chip != &no_irq_chip)
9205e31d 638 mask_ack_irq(desc);
801a0e9a 639 irq_state_set_disabled(desc);
dd87eb3a
TG
640 desc->depth = 1;
641 }
642 desc->handle_irq = handle;
a460e745 643 desc->name = name;
dd87eb3a
TG
644
645 if (handle != handle_bad_irq && is_chained) {
1ccb4e61
TG
646 irq_settings_set_noprobe(desc);
647 irq_settings_set_norequest(desc);
7f1b1244 648 irq_settings_set_nothread(desc);
46999238 649 irq_startup(desc);
dd87eb3a 650 }
02725e74
TG
651out:
652 irq_put_desc_busunlock(desc, flags);
dd87eb3a 653}
3836ca08 654EXPORT_SYMBOL_GPL(__irq_set_handler);
dd87eb3a
TG
655
656void
3836ca08 657irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
a460e745 658 irq_flow_handler_t handle, const char *name)
dd87eb3a 659{
35e857cb 660 irq_set_chip(irq, chip);
3836ca08 661 __irq_set_handler(irq, handle, 0, name);
dd87eb3a 662}
46f4f8f6 663
44247184 664void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set)
46f4f8f6 665{
46f4f8f6 666 unsigned long flags;
31d9d9b6 667 struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0);
46f4f8f6 668
44247184 669 if (!desc)
46f4f8f6 670 return;
a005677b
TG
671 irq_settings_clr_and_set(desc, clr, set);
672
876dbd4c 673 irqd_clear(&desc->irq_data, IRQD_NO_BALANCING | IRQD_PER_CPU |
e1ef8241 674 IRQD_TRIGGER_MASK | IRQD_LEVEL | IRQD_MOVE_PCNTXT);
a005677b
TG
675 if (irq_settings_has_no_balance_set(desc))
676 irqd_set(&desc->irq_data, IRQD_NO_BALANCING);
677 if (irq_settings_is_per_cpu(desc))
678 irqd_set(&desc->irq_data, IRQD_PER_CPU);
e1ef8241
TG
679 if (irq_settings_can_move_pcntxt(desc))
680 irqd_set(&desc->irq_data, IRQD_MOVE_PCNTXT);
0ef5ca1e
TG
681 if (irq_settings_is_level(desc))
682 irqd_set(&desc->irq_data, IRQD_LEVEL);
a005677b 683
876dbd4c
TG
684 irqd_set(&desc->irq_data, irq_settings_get_trigger_mask(desc));
685
02725e74 686 irq_put_desc_unlock(desc, flags);
46f4f8f6 687}
edf76f83 688EXPORT_SYMBOL_GPL(irq_modify_status);
0fdb4b25
DD
689
690/**
691 * irq_cpu_online - Invoke all irq_cpu_online functions.
692 *
693 * Iterate through all irqs and invoke the chip.irq_cpu_online()
694 * for each.
695 */
696void irq_cpu_online(void)
697{
698 struct irq_desc *desc;
699 struct irq_chip *chip;
700 unsigned long flags;
701 unsigned int irq;
702
703 for_each_active_irq(irq) {
704 desc = irq_to_desc(irq);
705 if (!desc)
706 continue;
707
708 raw_spin_lock_irqsave(&desc->lock, flags);
709
710 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
711 if (chip && chip->irq_cpu_online &&
712 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 713 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
714 chip->irq_cpu_online(&desc->irq_data);
715
716 raw_spin_unlock_irqrestore(&desc->lock, flags);
717 }
718}
719
720/**
721 * irq_cpu_offline - Invoke all irq_cpu_offline functions.
722 *
723 * Iterate through all irqs and invoke the chip.irq_cpu_offline()
724 * for each.
725 */
726void irq_cpu_offline(void)
727{
728 struct irq_desc *desc;
729 struct irq_chip *chip;
730 unsigned long flags;
731 unsigned int irq;
732
733 for_each_active_irq(irq) {
734 desc = irq_to_desc(irq);
735 if (!desc)
736 continue;
737
738 raw_spin_lock_irqsave(&desc->lock, flags);
739
740 chip = irq_data_get_irq_chip(&desc->irq_data);
b3d42232
TG
741 if (chip && chip->irq_cpu_offline &&
742 (!(chip->flags & IRQCHIP_ONOFFLINE_ENABLED) ||
32f4125e 743 !irqd_irq_disabled(&desc->irq_data)))
0fdb4b25
DD
744 chip->irq_cpu_offline(&desc->irq_data);
745
746 raw_spin_unlock_irqrestore(&desc->lock, flags);
747 }
748}
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