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dd87eb3a TG |
1 | /* |
2 | * linux/kernel/irq/chip.c | |
3 | * | |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
5 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
6 | * | |
7 | * This file contains the core interrupt handling code, for irq-chip | |
8 | * based architectures. | |
9 | * | |
10 | * Detailed information is available in Documentation/DocBook/genericirq | |
11 | */ | |
12 | ||
13 | #include <linux/irq.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/kernel_stat.h> | |
17 | ||
18 | #include "internals.h" | |
19 | ||
3a16d713 EB |
20 | /** |
21 | * dynamic_irq_init - initialize a dynamically allocated irq | |
22 | * @irq: irq number to initialize | |
23 | */ | |
24 | void dynamic_irq_init(unsigned int irq) | |
25 | { | |
26 | struct irq_desc *desc; | |
27 | unsigned long flags; | |
28 | ||
29 | if (irq >= NR_IRQS) { | |
30 | printk(KERN_ERR "Trying to initialize invalid IRQ%d\n", irq); | |
31 | WARN_ON(1); | |
32 | return; | |
33 | } | |
34 | ||
35 | /* Ensure we don't have left over values from a previous use of this irq */ | |
36 | desc = irq_desc + irq; | |
37 | spin_lock_irqsave(&desc->lock, flags); | |
38 | desc->status = IRQ_DISABLED; | |
39 | desc->chip = &no_irq_chip; | |
40 | desc->handle_irq = handle_bad_irq; | |
41 | desc->depth = 1; | |
42 | desc->handler_data = NULL; | |
43 | desc->chip_data = NULL; | |
44 | desc->action = NULL; | |
45 | desc->irq_count = 0; | |
46 | desc->irqs_unhandled = 0; | |
47 | #ifdef CONFIG_SMP | |
48 | desc->affinity = CPU_MASK_ALL; | |
49 | #endif | |
50 | spin_unlock_irqrestore(&desc->lock, flags); | |
51 | } | |
52 | ||
53 | /** | |
54 | * dynamic_irq_cleanup - cleanup a dynamically allocated irq | |
55 | * @irq: irq number to initialize | |
56 | */ | |
57 | void dynamic_irq_cleanup(unsigned int irq) | |
58 | { | |
59 | struct irq_desc *desc; | |
60 | unsigned long flags; | |
61 | ||
62 | if (irq >= NR_IRQS) { | |
63 | printk(KERN_ERR "Trying to cleanup invalid IRQ%d\n", irq); | |
64 | WARN_ON(1); | |
65 | return; | |
66 | } | |
67 | ||
68 | desc = irq_desc + irq; | |
69 | spin_lock_irqsave(&desc->lock, flags); | |
1f80025e EB |
70 | if (desc->action) { |
71 | spin_unlock_irqrestore(&desc->lock, flags); | |
72 | printk(KERN_ERR "Destroying IRQ%d without calling free_irq\n", | |
73 | irq); | |
74 | WARN_ON(1); | |
75 | return; | |
76 | } | |
3a16d713 EB |
77 | desc->handle_irq = handle_bad_irq; |
78 | desc->chip = &no_irq_chip; | |
79 | spin_unlock_irqrestore(&desc->lock, flags); | |
80 | } | |
81 | ||
82 | ||
dd87eb3a TG |
83 | /** |
84 | * set_irq_chip - set the irq chip for an irq | |
85 | * @irq: irq number | |
86 | * @chip: pointer to irq chip description structure | |
87 | */ | |
88 | int set_irq_chip(unsigned int irq, struct irq_chip *chip) | |
89 | { | |
90 | struct irq_desc *desc; | |
91 | unsigned long flags; | |
92 | ||
93 | if (irq >= NR_IRQS) { | |
94 | printk(KERN_ERR "Trying to install chip for IRQ%d\n", irq); | |
95 | WARN_ON(1); | |
96 | return -EINVAL; | |
97 | } | |
98 | ||
99 | if (!chip) | |
100 | chip = &no_irq_chip; | |
101 | ||
102 | desc = irq_desc + irq; | |
103 | spin_lock_irqsave(&desc->lock, flags); | |
104 | irq_chip_set_defaults(chip); | |
105 | desc->chip = chip; | |
dd87eb3a TG |
106 | spin_unlock_irqrestore(&desc->lock, flags); |
107 | ||
108 | return 0; | |
109 | } | |
110 | EXPORT_SYMBOL(set_irq_chip); | |
111 | ||
112 | /** | |
113 | * set_irq_type - set the irq type for an irq | |
114 | * @irq: irq number | |
115 | * @type: interrupt type - see include/linux/interrupt.h | |
116 | */ | |
117 | int set_irq_type(unsigned int irq, unsigned int type) | |
118 | { | |
119 | struct irq_desc *desc; | |
120 | unsigned long flags; | |
121 | int ret = -ENXIO; | |
122 | ||
123 | if (irq >= NR_IRQS) { | |
124 | printk(KERN_ERR "Trying to set irq type for IRQ%d\n", irq); | |
125 | return -ENODEV; | |
126 | } | |
127 | ||
128 | desc = irq_desc + irq; | |
129 | if (desc->chip->set_type) { | |
130 | spin_lock_irqsave(&desc->lock, flags); | |
131 | ret = desc->chip->set_type(irq, type); | |
132 | spin_unlock_irqrestore(&desc->lock, flags); | |
133 | } | |
134 | return ret; | |
135 | } | |
136 | EXPORT_SYMBOL(set_irq_type); | |
137 | ||
138 | /** | |
139 | * set_irq_data - set irq type data for an irq | |
140 | * @irq: Interrupt number | |
141 | * @data: Pointer to interrupt specific data | |
142 | * | |
143 | * Set the hardware irq controller data for an irq | |
144 | */ | |
145 | int set_irq_data(unsigned int irq, void *data) | |
146 | { | |
147 | struct irq_desc *desc; | |
148 | unsigned long flags; | |
149 | ||
150 | if (irq >= NR_IRQS) { | |
151 | printk(KERN_ERR | |
152 | "Trying to install controller data for IRQ%d\n", irq); | |
153 | return -EINVAL; | |
154 | } | |
155 | ||
156 | desc = irq_desc + irq; | |
157 | spin_lock_irqsave(&desc->lock, flags); | |
158 | desc->handler_data = data; | |
159 | spin_unlock_irqrestore(&desc->lock, flags); | |
160 | return 0; | |
161 | } | |
162 | EXPORT_SYMBOL(set_irq_data); | |
163 | ||
164 | /** | |
165 | * set_irq_chip_data - set irq chip data for an irq | |
166 | * @irq: Interrupt number | |
167 | * @data: Pointer to chip specific data | |
168 | * | |
169 | * Set the hardware irq chip data for an irq | |
170 | */ | |
171 | int set_irq_chip_data(unsigned int irq, void *data) | |
172 | { | |
173 | struct irq_desc *desc = irq_desc + irq; | |
174 | unsigned long flags; | |
175 | ||
176 | if (irq >= NR_IRQS || !desc->chip) { | |
177 | printk(KERN_ERR "BUG: bad set_irq_chip_data(IRQ#%d)\n", irq); | |
178 | return -EINVAL; | |
179 | } | |
180 | ||
181 | spin_lock_irqsave(&desc->lock, flags); | |
182 | desc->chip_data = data; | |
183 | spin_unlock_irqrestore(&desc->lock, flags); | |
184 | ||
185 | return 0; | |
186 | } | |
187 | EXPORT_SYMBOL(set_irq_chip_data); | |
188 | ||
189 | /* | |
190 | * default enable function | |
191 | */ | |
192 | static void default_enable(unsigned int irq) | |
193 | { | |
194 | struct irq_desc *desc = irq_desc + irq; | |
195 | ||
196 | desc->chip->unmask(irq); | |
197 | desc->status &= ~IRQ_MASKED; | |
198 | } | |
199 | ||
200 | /* | |
201 | * default disable function | |
202 | */ | |
203 | static void default_disable(unsigned int irq) | |
204 | { | |
205 | struct irq_desc *desc = irq_desc + irq; | |
206 | ||
207 | if (!(desc->status & IRQ_DELAYED_DISABLE)) | |
2ff6fd8f | 208 | desc->chip->mask(irq); |
dd87eb3a TG |
209 | } |
210 | ||
211 | /* | |
212 | * default startup function | |
213 | */ | |
214 | static unsigned int default_startup(unsigned int irq) | |
215 | { | |
216 | irq_desc[irq].chip->enable(irq); | |
217 | ||
218 | return 0; | |
219 | } | |
220 | ||
221 | /* | |
222 | * Fixup enable/disable function pointers | |
223 | */ | |
224 | void irq_chip_set_defaults(struct irq_chip *chip) | |
225 | { | |
226 | if (!chip->enable) | |
227 | chip->enable = default_enable; | |
228 | if (!chip->disable) | |
229 | chip->disable = default_disable; | |
230 | if (!chip->startup) | |
231 | chip->startup = default_startup; | |
232 | if (!chip->shutdown) | |
233 | chip->shutdown = chip->disable; | |
234 | if (!chip->name) | |
235 | chip->name = chip->typename; | |
236 | } | |
237 | ||
238 | static inline void mask_ack_irq(struct irq_desc *desc, int irq) | |
239 | { | |
240 | if (desc->chip->mask_ack) | |
241 | desc->chip->mask_ack(irq); | |
242 | else { | |
243 | desc->chip->mask(irq); | |
244 | desc->chip->ack(irq); | |
245 | } | |
246 | } | |
247 | ||
248 | /** | |
249 | * handle_simple_irq - Simple and software-decoded IRQs. | |
250 | * @irq: the interrupt number | |
251 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
252 | * |
253 | * Simple interrupts are either sent from a demultiplexing interrupt | |
254 | * handler or come from hardware, where no interrupt hardware control | |
255 | * is necessary. | |
256 | * | |
257 | * Note: The caller is expected to handle the ack, clear, mask and | |
258 | * unmask issues if necessary. | |
259 | */ | |
260 | void fastcall | |
7d12e780 | 261 | handle_simple_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
262 | { |
263 | struct irqaction *action; | |
264 | irqreturn_t action_ret; | |
265 | const unsigned int cpu = smp_processor_id(); | |
266 | ||
267 | spin_lock(&desc->lock); | |
268 | ||
269 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
270 | goto out_unlock; | |
271 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
272 | kstat_cpu(cpu).irqs[irq]++; | |
273 | ||
274 | action = desc->action; | |
275 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) | |
276 | goto out_unlock; | |
277 | ||
278 | desc->status |= IRQ_INPROGRESS; | |
279 | spin_unlock(&desc->lock); | |
280 | ||
7d12e780 | 281 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 282 | if (!noirqdebug) |
7d12e780 | 283 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
284 | |
285 | spin_lock(&desc->lock); | |
286 | desc->status &= ~IRQ_INPROGRESS; | |
287 | out_unlock: | |
288 | spin_unlock(&desc->lock); | |
289 | } | |
290 | ||
291 | /** | |
292 | * handle_level_irq - Level type irq handler | |
293 | * @irq: the interrupt number | |
294 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
295 | * |
296 | * Level type interrupts are active as long as the hardware line has | |
297 | * the active level. This may require to mask the interrupt and unmask | |
298 | * it after the associated handler has acknowledged the device, so the | |
299 | * interrupt line is back to inactive. | |
300 | */ | |
301 | void fastcall | |
7d12e780 | 302 | handle_level_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
303 | { |
304 | unsigned int cpu = smp_processor_id(); | |
305 | struct irqaction *action; | |
306 | irqreturn_t action_ret; | |
307 | ||
308 | spin_lock(&desc->lock); | |
309 | mask_ack_irq(desc, irq); | |
310 | ||
311 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
86998aa6 | 312 | goto out_unlock; |
dd87eb3a TG |
313 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); |
314 | kstat_cpu(cpu).irqs[irq]++; | |
315 | ||
316 | /* | |
317 | * If its disabled or no action available | |
318 | * keep it masked and get out of here | |
319 | */ | |
320 | action = desc->action; | |
5a43a066 BH |
321 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
322 | desc->status |= IRQ_PENDING; | |
86998aa6 | 323 | goto out_unlock; |
5a43a066 | 324 | } |
dd87eb3a TG |
325 | |
326 | desc->status |= IRQ_INPROGRESS; | |
5a43a066 | 327 | desc->status &= ~IRQ_PENDING; |
dd87eb3a TG |
328 | spin_unlock(&desc->lock); |
329 | ||
7d12e780 | 330 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 331 | if (!noirqdebug) |
7d12e780 | 332 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
333 | |
334 | spin_lock(&desc->lock); | |
335 | desc->status &= ~IRQ_INPROGRESS; | |
dd87eb3a TG |
336 | if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) |
337 | desc->chip->unmask(irq); | |
86998aa6 | 338 | out_unlock: |
dd87eb3a TG |
339 | spin_unlock(&desc->lock); |
340 | } | |
341 | ||
342 | /** | |
47c2a3aa | 343 | * handle_fasteoi_irq - irq handler for transparent controllers |
dd87eb3a TG |
344 | * @irq: the interrupt number |
345 | * @desc: the interrupt description structure for this irq | |
dd87eb3a | 346 | * |
47c2a3aa | 347 | * Only a single callback will be issued to the chip: an ->eoi() |
dd87eb3a TG |
348 | * call when the interrupt has been serviced. This enables support |
349 | * for modern forms of interrupt handlers, which handle the flow | |
350 | * details in hardware, transparently. | |
351 | */ | |
352 | void fastcall | |
7d12e780 | 353 | handle_fasteoi_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
354 | { |
355 | unsigned int cpu = smp_processor_id(); | |
356 | struct irqaction *action; | |
357 | irqreturn_t action_ret; | |
358 | ||
359 | spin_lock(&desc->lock); | |
360 | ||
361 | if (unlikely(desc->status & IRQ_INPROGRESS)) | |
362 | goto out; | |
363 | ||
364 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
365 | kstat_cpu(cpu).irqs[irq]++; | |
366 | ||
367 | /* | |
368 | * If its disabled or no action available | |
369 | * keep it masked and get out of here | |
370 | */ | |
371 | action = desc->action; | |
98bb244b BH |
372 | if (unlikely(!action || (desc->status & IRQ_DISABLED))) { |
373 | desc->status |= IRQ_PENDING; | |
dd87eb3a | 374 | goto out; |
98bb244b | 375 | } |
dd87eb3a TG |
376 | |
377 | desc->status |= IRQ_INPROGRESS; | |
98bb244b | 378 | desc->status &= ~IRQ_PENDING; |
dd87eb3a TG |
379 | spin_unlock(&desc->lock); |
380 | ||
7d12e780 | 381 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 382 | if (!noirqdebug) |
7d12e780 | 383 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
384 | |
385 | spin_lock(&desc->lock); | |
386 | desc->status &= ~IRQ_INPROGRESS; | |
387 | out: | |
47c2a3aa | 388 | desc->chip->eoi(irq); |
dd87eb3a TG |
389 | |
390 | spin_unlock(&desc->lock); | |
391 | } | |
392 | ||
393 | /** | |
394 | * handle_edge_irq - edge type IRQ handler | |
395 | * @irq: the interrupt number | |
396 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
397 | * |
398 | * Interrupt occures on the falling and/or rising edge of a hardware | |
399 | * signal. The occurence is latched into the irq controller hardware | |
400 | * and must be acked in order to be reenabled. After the ack another | |
401 | * interrupt can happen on the same source even before the first one | |
402 | * is handled by the assosiacted event handler. If this happens it | |
403 | * might be necessary to disable (mask) the interrupt depending on the | |
404 | * controller hardware. This requires to reenable the interrupt inside | |
405 | * of the loop which handles the interrupts which have arrived while | |
406 | * the handler was running. If all pending interrupts are handled, the | |
407 | * loop is left. | |
408 | */ | |
409 | void fastcall | |
7d12e780 | 410 | handle_edge_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
411 | { |
412 | const unsigned int cpu = smp_processor_id(); | |
413 | ||
414 | spin_lock(&desc->lock); | |
415 | ||
416 | desc->status &= ~(IRQ_REPLAY | IRQ_WAITING); | |
417 | ||
418 | /* | |
419 | * If we're currently running this IRQ, or its disabled, | |
420 | * we shouldn't process the IRQ. Mark it pending, handle | |
421 | * the necessary masking and go out | |
422 | */ | |
423 | if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) || | |
424 | !desc->action)) { | |
425 | desc->status |= (IRQ_PENDING | IRQ_MASKED); | |
426 | mask_ack_irq(desc, irq); | |
427 | goto out_unlock; | |
428 | } | |
429 | ||
430 | kstat_cpu(cpu).irqs[irq]++; | |
431 | ||
432 | /* Start handling the irq */ | |
433 | desc->chip->ack(irq); | |
434 | ||
435 | /* Mark the IRQ currently in progress.*/ | |
436 | desc->status |= IRQ_INPROGRESS; | |
437 | ||
438 | do { | |
439 | struct irqaction *action = desc->action; | |
440 | irqreturn_t action_ret; | |
441 | ||
442 | if (unlikely(!action)) { | |
443 | desc->chip->mask(irq); | |
444 | goto out_unlock; | |
445 | } | |
446 | ||
447 | /* | |
448 | * When another irq arrived while we were handling | |
449 | * one, we could have masked the irq. | |
450 | * Renable it, if it was not disabled in meantime. | |
451 | */ | |
452 | if (unlikely((desc->status & | |
453 | (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) == | |
454 | (IRQ_PENDING | IRQ_MASKED))) { | |
455 | desc->chip->unmask(irq); | |
456 | desc->status &= ~IRQ_MASKED; | |
457 | } | |
458 | ||
459 | desc->status &= ~IRQ_PENDING; | |
460 | spin_unlock(&desc->lock); | |
7d12e780 | 461 | action_ret = handle_IRQ_event(irq, action); |
dd87eb3a | 462 | if (!noirqdebug) |
7d12e780 | 463 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
464 | spin_lock(&desc->lock); |
465 | ||
466 | } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING); | |
467 | ||
468 | desc->status &= ~IRQ_INPROGRESS; | |
469 | out_unlock: | |
470 | spin_unlock(&desc->lock); | |
471 | } | |
472 | ||
473 | #ifdef CONFIG_SMP | |
474 | /** | |
475 | * handle_percpu_IRQ - Per CPU local irq handler | |
476 | * @irq: the interrupt number | |
477 | * @desc: the interrupt description structure for this irq | |
dd87eb3a TG |
478 | * |
479 | * Per CPU interrupts on SMP machines without locking requirements | |
480 | */ | |
481 | void fastcall | |
7d12e780 | 482 | handle_percpu_irq(unsigned int irq, struct irq_desc *desc) |
dd87eb3a TG |
483 | { |
484 | irqreturn_t action_ret; | |
485 | ||
486 | kstat_this_cpu.irqs[irq]++; | |
487 | ||
488 | if (desc->chip->ack) | |
489 | desc->chip->ack(irq); | |
490 | ||
7d12e780 | 491 | action_ret = handle_IRQ_event(irq, desc->action); |
dd87eb3a | 492 | if (!noirqdebug) |
7d12e780 | 493 | note_interrupt(irq, desc, action_ret); |
dd87eb3a TG |
494 | |
495 | if (desc->chip->eoi) | |
496 | desc->chip->eoi(irq); | |
497 | } | |
498 | ||
499 | #endif /* CONFIG_SMP */ | |
500 | ||
501 | void | |
a460e745 IM |
502 | __set_irq_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained, |
503 | const char *name) | |
dd87eb3a TG |
504 | { |
505 | struct irq_desc *desc; | |
506 | unsigned long flags; | |
507 | ||
508 | if (irq >= NR_IRQS) { | |
509 | printk(KERN_ERR | |
510 | "Trying to install type control for IRQ%d\n", irq); | |
511 | return; | |
512 | } | |
513 | ||
514 | desc = irq_desc + irq; | |
515 | ||
516 | if (!handle) | |
517 | handle = handle_bad_irq; | |
518 | ||
f8b5473f TG |
519 | if (desc->chip == &no_irq_chip) { |
520 | printk(KERN_WARNING "Trying to install %sinterrupt handler " | |
521 | "for IRQ%d\n", is_chained ? "chained " : " ", irq); | |
522 | /* | |
523 | * Some ARM implementations install a handler for really dumb | |
524 | * interrupt hardware without setting an irq_chip. This worked | |
525 | * with the ARM no_irq_chip but the check in setup_irq would | |
526 | * prevent us to setup the interrupt at all. Switch it to | |
527 | * dummy_irq_chip for easy transition. | |
528 | */ | |
529 | desc->chip = &dummy_irq_chip; | |
530 | } | |
dd87eb3a TG |
531 | |
532 | spin_lock_irqsave(&desc->lock, flags); | |
533 | ||
534 | /* Uninstall? */ | |
535 | if (handle == handle_bad_irq) { | |
536 | if (desc->chip != &no_irq_chip) { | |
537 | desc->chip->mask(irq); | |
538 | desc->chip->ack(irq); | |
539 | } | |
540 | desc->status |= IRQ_DISABLED; | |
541 | desc->depth = 1; | |
542 | } | |
543 | desc->handle_irq = handle; | |
a460e745 | 544 | desc->name = name; |
dd87eb3a TG |
545 | |
546 | if (handle != handle_bad_irq && is_chained) { | |
547 | desc->status &= ~IRQ_DISABLED; | |
548 | desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE; | |
549 | desc->depth = 0; | |
550 | desc->chip->unmask(irq); | |
551 | } | |
552 | spin_unlock_irqrestore(&desc->lock, flags); | |
553 | } | |
554 | ||
555 | void | |
556 | set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, | |
57a58a94 | 557 | irq_flow_handler_t handle) |
dd87eb3a TG |
558 | { |
559 | set_irq_chip(irq, chip); | |
a460e745 | 560 | __set_irq_handler(irq, handle, 0, NULL); |
dd87eb3a TG |
561 | } |
562 | ||
a460e745 IM |
563 | void |
564 | set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, | |
565 | irq_flow_handler_t handle, const char *name) | |
dd87eb3a | 566 | { |
a460e745 IM |
567 | set_irq_chip(irq, chip); |
568 | __set_irq_handler(irq, handle, 0, name); | |
dd87eb3a | 569 | } |