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3795de23 TG |
1 | /* |
2 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar | |
3 | * Copyright (C) 2005-2006, Thomas Gleixner, Russell King | |
4 | * | |
5 | * This file contains the interrupt descriptor management code | |
6 | * | |
7 | * Detailed information is available in Documentation/DocBook/genericirq | |
8 | * | |
9 | */ | |
10 | #include <linux/irq.h> | |
11 | #include <linux/slab.h> | |
ec53cf23 | 12 | #include <linux/export.h> |
3795de23 TG |
13 | #include <linux/interrupt.h> |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/radix-tree.h> | |
1f5a5b87 | 16 | #include <linux/bitmap.h> |
76ba59f8 | 17 | #include <linux/irqdomain.h> |
3795de23 TG |
18 | |
19 | #include "internals.h" | |
20 | ||
21 | /* | |
22 | * lockdep: we want to handle all irq_desc locks as a single lock-class: | |
23 | */ | |
78f90d91 | 24 | static struct lock_class_key irq_desc_lock_class; |
3795de23 | 25 | |
fe051434 | 26 | #if defined(CONFIG_SMP) |
3795de23 TG |
27 | static void __init init_irq_default_affinity(void) |
28 | { | |
29 | alloc_cpumask_var(&irq_default_affinity, GFP_NOWAIT); | |
30 | cpumask_setall(irq_default_affinity); | |
31 | } | |
32 | #else | |
33 | static void __init init_irq_default_affinity(void) | |
34 | { | |
35 | } | |
36 | #endif | |
37 | ||
1f5a5b87 TG |
38 | #ifdef CONFIG_SMP |
39 | static int alloc_masks(struct irq_desc *desc, gfp_t gfp, int node) | |
40 | { | |
41 | if (!zalloc_cpumask_var_node(&desc->irq_data.affinity, gfp, node)) | |
42 | return -ENOMEM; | |
43 | ||
44 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
45 | if (!zalloc_cpumask_var_node(&desc->pending_mask, gfp, node)) { | |
46 | free_cpumask_var(desc->irq_data.affinity); | |
47 | return -ENOMEM; | |
48 | } | |
49 | #endif | |
50 | return 0; | |
51 | } | |
52 | ||
53 | static void desc_smp_init(struct irq_desc *desc, int node) | |
54 | { | |
1f5a5b87 | 55 | cpumask_copy(desc->irq_data.affinity, irq_default_affinity); |
b7b29338 TG |
56 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
57 | cpumask_clear(desc->pending_mask); | |
58 | #endif | |
449e9cae JL |
59 | #ifdef CONFIG_NUMA |
60 | desc->irq_common_data.node = node; | |
61 | #endif | |
b7b29338 TG |
62 | } |
63 | ||
1f5a5b87 TG |
64 | #else |
65 | static inline int | |
66 | alloc_masks(struct irq_desc *desc, gfp_t gfp, int node) { return 0; } | |
67 | static inline void desc_smp_init(struct irq_desc *desc, int node) { } | |
68 | #endif | |
69 | ||
b6873807 SAS |
70 | static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node, |
71 | struct module *owner) | |
1f5a5b87 | 72 | { |
6c9ae009 ED |
73 | int cpu; |
74 | ||
0d0b4c86 | 75 | desc->irq_data.common = &desc->irq_common_data; |
1f5a5b87 TG |
76 | desc->irq_data.irq = irq; |
77 | desc->irq_data.chip = &no_irq_chip; | |
78 | desc->irq_data.chip_data = NULL; | |
79 | desc->irq_data.handler_data = NULL; | |
80 | desc->irq_data.msi_desc = NULL; | |
f9e4989e | 81 | irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS); |
801a0e9a | 82 | irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED); |
1f5a5b87 TG |
83 | desc->handle_irq = handle_bad_irq; |
84 | desc->depth = 1; | |
b7b29338 TG |
85 | desc->irq_count = 0; |
86 | desc->irqs_unhandled = 0; | |
1f5a5b87 | 87 | desc->name = NULL; |
b6873807 | 88 | desc->owner = owner; |
6c9ae009 ED |
89 | for_each_possible_cpu(cpu) |
90 | *per_cpu_ptr(desc->kstat_irqs, cpu) = 0; | |
1f5a5b87 TG |
91 | desc_smp_init(desc, node); |
92 | } | |
93 | ||
3795de23 TG |
94 | int nr_irqs = NR_IRQS; |
95 | EXPORT_SYMBOL_GPL(nr_irqs); | |
96 | ||
a05a900a | 97 | static DEFINE_MUTEX(sparse_irq_lock); |
c1ee6264 | 98 | static DECLARE_BITMAP(allocated_irqs, IRQ_BITMAP_BITS); |
1f5a5b87 | 99 | |
3795de23 TG |
100 | #ifdef CONFIG_SPARSE_IRQ |
101 | ||
baa0d233 | 102 | static RADIX_TREE(irq_desc_tree, GFP_KERNEL); |
3795de23 | 103 | |
1f5a5b87 | 104 | static void irq_insert_desc(unsigned int irq, struct irq_desc *desc) |
3795de23 TG |
105 | { |
106 | radix_tree_insert(&irq_desc_tree, irq, desc); | |
107 | } | |
108 | ||
109 | struct irq_desc *irq_to_desc(unsigned int irq) | |
110 | { | |
111 | return radix_tree_lookup(&irq_desc_tree, irq); | |
112 | } | |
3911ff30 | 113 | EXPORT_SYMBOL(irq_to_desc); |
3795de23 | 114 | |
1f5a5b87 TG |
115 | static void delete_irq_desc(unsigned int irq) |
116 | { | |
117 | radix_tree_delete(&irq_desc_tree, irq); | |
118 | } | |
119 | ||
120 | #ifdef CONFIG_SMP | |
121 | static void free_masks(struct irq_desc *desc) | |
122 | { | |
123 | #ifdef CONFIG_GENERIC_PENDING_IRQ | |
124 | free_cpumask_var(desc->pending_mask); | |
125 | #endif | |
c0a19ebc | 126 | free_cpumask_var(desc->irq_data.affinity); |
1f5a5b87 TG |
127 | } |
128 | #else | |
129 | static inline void free_masks(struct irq_desc *desc) { } | |
130 | #endif | |
131 | ||
c291ee62 TG |
132 | void irq_lock_sparse(void) |
133 | { | |
134 | mutex_lock(&sparse_irq_lock); | |
135 | } | |
136 | ||
137 | void irq_unlock_sparse(void) | |
138 | { | |
139 | mutex_unlock(&sparse_irq_lock); | |
140 | } | |
141 | ||
b6873807 | 142 | static struct irq_desc *alloc_desc(int irq, int node, struct module *owner) |
1f5a5b87 TG |
143 | { |
144 | struct irq_desc *desc; | |
baa0d233 | 145 | gfp_t gfp = GFP_KERNEL; |
1f5a5b87 TG |
146 | |
147 | desc = kzalloc_node(sizeof(*desc), gfp, node); | |
148 | if (!desc) | |
149 | return NULL; | |
150 | /* allocate based on nr_cpu_ids */ | |
6c9ae009 | 151 | desc->kstat_irqs = alloc_percpu(unsigned int); |
1f5a5b87 TG |
152 | if (!desc->kstat_irqs) |
153 | goto err_desc; | |
154 | ||
155 | if (alloc_masks(desc, gfp, node)) | |
156 | goto err_kstat; | |
157 | ||
158 | raw_spin_lock_init(&desc->lock); | |
159 | lockdep_set_class(&desc->lock, &irq_desc_lock_class); | |
160 | ||
b6873807 | 161 | desc_set_defaults(irq, desc, node, owner); |
1f5a5b87 TG |
162 | |
163 | return desc; | |
164 | ||
165 | err_kstat: | |
6c9ae009 | 166 | free_percpu(desc->kstat_irqs); |
1f5a5b87 TG |
167 | err_desc: |
168 | kfree(desc); | |
169 | return NULL; | |
170 | } | |
171 | ||
172 | static void free_desc(unsigned int irq) | |
173 | { | |
174 | struct irq_desc *desc = irq_to_desc(irq); | |
1f5a5b87 | 175 | |
13bfe99e TG |
176 | unregister_irq_proc(irq, desc); |
177 | ||
c291ee62 TG |
178 | /* |
179 | * sparse_irq_lock protects also show_interrupts() and | |
180 | * kstat_irq_usr(). Once we deleted the descriptor from the | |
181 | * sparse tree we can free it. Access in proc will fail to | |
182 | * lookup the descriptor. | |
183 | */ | |
a05a900a | 184 | mutex_lock(&sparse_irq_lock); |
1f5a5b87 | 185 | delete_irq_desc(irq); |
a05a900a | 186 | mutex_unlock(&sparse_irq_lock); |
1f5a5b87 TG |
187 | |
188 | free_masks(desc); | |
6c9ae009 | 189 | free_percpu(desc->kstat_irqs); |
1f5a5b87 TG |
190 | kfree(desc); |
191 | } | |
192 | ||
b6873807 SAS |
193 | static int alloc_descs(unsigned int start, unsigned int cnt, int node, |
194 | struct module *owner) | |
1f5a5b87 TG |
195 | { |
196 | struct irq_desc *desc; | |
1f5a5b87 TG |
197 | int i; |
198 | ||
199 | for (i = 0; i < cnt; i++) { | |
b6873807 | 200 | desc = alloc_desc(start + i, node, owner); |
1f5a5b87 TG |
201 | if (!desc) |
202 | goto err; | |
a05a900a | 203 | mutex_lock(&sparse_irq_lock); |
1f5a5b87 | 204 | irq_insert_desc(start + i, desc); |
a05a900a | 205 | mutex_unlock(&sparse_irq_lock); |
1f5a5b87 TG |
206 | } |
207 | return start; | |
208 | ||
209 | err: | |
210 | for (i--; i >= 0; i--) | |
211 | free_desc(start + i); | |
212 | ||
a05a900a | 213 | mutex_lock(&sparse_irq_lock); |
1f5a5b87 | 214 | bitmap_clear(allocated_irqs, start, cnt); |
a05a900a | 215 | mutex_unlock(&sparse_irq_lock); |
1f5a5b87 TG |
216 | return -ENOMEM; |
217 | } | |
218 | ||
ed4dea6e | 219 | static int irq_expand_nr_irqs(unsigned int nr) |
e7bcecb7 | 220 | { |
ed4dea6e | 221 | if (nr > IRQ_BITMAP_BITS) |
e7bcecb7 | 222 | return -ENOMEM; |
ed4dea6e | 223 | nr_irqs = nr; |
e7bcecb7 TG |
224 | return 0; |
225 | } | |
226 | ||
3795de23 TG |
227 | int __init early_irq_init(void) |
228 | { | |
b683de2b | 229 | int i, initcnt, node = first_online_node; |
3795de23 | 230 | struct irq_desc *desc; |
3795de23 TG |
231 | |
232 | init_irq_default_affinity(); | |
233 | ||
b683de2b TG |
234 | /* Let arch update nr_irqs and return the nr of preallocated irqs */ |
235 | initcnt = arch_probe_nr_irqs(); | |
236 | printk(KERN_INFO "NR_IRQS:%d nr_irqs:%d %d\n", NR_IRQS, nr_irqs, initcnt); | |
3795de23 | 237 | |
c1ee6264 TG |
238 | if (WARN_ON(nr_irqs > IRQ_BITMAP_BITS)) |
239 | nr_irqs = IRQ_BITMAP_BITS; | |
240 | ||
241 | if (WARN_ON(initcnt > IRQ_BITMAP_BITS)) | |
242 | initcnt = IRQ_BITMAP_BITS; | |
243 | ||
244 | if (initcnt > nr_irqs) | |
245 | nr_irqs = initcnt; | |
246 | ||
b683de2b | 247 | for (i = 0; i < initcnt; i++) { |
b6873807 | 248 | desc = alloc_desc(i, node, NULL); |
aa99ec0f TG |
249 | set_bit(i, allocated_irqs); |
250 | irq_insert_desc(i, desc); | |
3795de23 | 251 | } |
3795de23 TG |
252 | return arch_early_irq_init(); |
253 | } | |
254 | ||
3795de23 TG |
255 | #else /* !CONFIG_SPARSE_IRQ */ |
256 | ||
257 | struct irq_desc irq_desc[NR_IRQS] __cacheline_aligned_in_smp = { | |
258 | [0 ... NR_IRQS-1] = { | |
3795de23 TG |
259 | .handle_irq = handle_bad_irq, |
260 | .depth = 1, | |
261 | .lock = __RAW_SPIN_LOCK_UNLOCKED(irq_desc->lock), | |
262 | } | |
263 | }; | |
264 | ||
3795de23 TG |
265 | int __init early_irq_init(void) |
266 | { | |
aa99ec0f | 267 | int count, i, node = first_online_node; |
3795de23 | 268 | struct irq_desc *desc; |
3795de23 TG |
269 | |
270 | init_irq_default_affinity(); | |
271 | ||
272 | printk(KERN_INFO "NR_IRQS:%d\n", NR_IRQS); | |
273 | ||
274 | desc = irq_desc; | |
275 | count = ARRAY_SIZE(irq_desc); | |
276 | ||
277 | for (i = 0; i < count; i++) { | |
6c9ae009 | 278 | desc[i].kstat_irqs = alloc_percpu(unsigned int); |
e7fbad30 LW |
279 | alloc_masks(&desc[i], GFP_KERNEL, node); |
280 | raw_spin_lock_init(&desc[i].lock); | |
154cd387 | 281 | lockdep_set_class(&desc[i].lock, &irq_desc_lock_class); |
b6873807 | 282 | desc_set_defaults(i, &desc[i], node, NULL); |
3795de23 TG |
283 | } |
284 | return arch_early_irq_init(); | |
285 | } | |
286 | ||
287 | struct irq_desc *irq_to_desc(unsigned int irq) | |
288 | { | |
289 | return (irq < NR_IRQS) ? irq_desc + irq : NULL; | |
290 | } | |
2c45aada | 291 | EXPORT_SYMBOL(irq_to_desc); |
3795de23 | 292 | |
1f5a5b87 TG |
293 | static void free_desc(unsigned int irq) |
294 | { | |
d8179bc0 TG |
295 | struct irq_desc *desc = irq_to_desc(irq); |
296 | unsigned long flags; | |
297 | ||
298 | raw_spin_lock_irqsave(&desc->lock, flags); | |
6783011b | 299 | desc_set_defaults(irq, desc, irq_desc_get_node(desc), NULL); |
d8179bc0 | 300 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1f5a5b87 TG |
301 | } |
302 | ||
b6873807 SAS |
303 | static inline int alloc_descs(unsigned int start, unsigned int cnt, int node, |
304 | struct module *owner) | |
1f5a5b87 | 305 | { |
b6873807 SAS |
306 | u32 i; |
307 | ||
308 | for (i = 0; i < cnt; i++) { | |
309 | struct irq_desc *desc = irq_to_desc(start + i); | |
310 | ||
311 | desc->owner = owner; | |
312 | } | |
1f5a5b87 TG |
313 | return start; |
314 | } | |
e7bcecb7 | 315 | |
ed4dea6e | 316 | static int irq_expand_nr_irqs(unsigned int nr) |
e7bcecb7 TG |
317 | { |
318 | return -ENOMEM; | |
319 | } | |
320 | ||
f63b6a05 TG |
321 | void irq_mark_irq(unsigned int irq) |
322 | { | |
323 | mutex_lock(&sparse_irq_lock); | |
324 | bitmap_set(allocated_irqs, irq, 1); | |
325 | mutex_unlock(&sparse_irq_lock); | |
326 | } | |
327 | ||
c940e01c TG |
328 | #ifdef CONFIG_GENERIC_IRQ_LEGACY |
329 | void irq_init_desc(unsigned int irq) | |
330 | { | |
d8179bc0 | 331 | free_desc(irq); |
c940e01c TG |
332 | } |
333 | #endif | |
334 | ||
3795de23 TG |
335 | #endif /* !CONFIG_SPARSE_IRQ */ |
336 | ||
fe12bc2c TG |
337 | /** |
338 | * generic_handle_irq - Invoke the handler for a particular irq | |
339 | * @irq: The irq number to handle | |
340 | * | |
341 | */ | |
342 | int generic_handle_irq(unsigned int irq) | |
343 | { | |
344 | struct irq_desc *desc = irq_to_desc(irq); | |
345 | ||
346 | if (!desc) | |
347 | return -EINVAL; | |
348 | generic_handle_irq_desc(irq, desc); | |
349 | return 0; | |
350 | } | |
edf76f83 | 351 | EXPORT_SYMBOL_GPL(generic_handle_irq); |
fe12bc2c | 352 | |
76ba59f8 MZ |
353 | #ifdef CONFIG_HANDLE_DOMAIN_IRQ |
354 | /** | |
355 | * __handle_domain_irq - Invoke the handler for a HW irq belonging to a domain | |
356 | * @domain: The domain where to perform the lookup | |
357 | * @hwirq: The HW irq number to convert to a logical one | |
358 | * @lookup: Whether to perform the domain lookup or not | |
359 | * @regs: Register file coming from the low-level handling code | |
360 | * | |
361 | * Returns: 0 on success, or -EINVAL if conversion has failed | |
362 | */ | |
363 | int __handle_domain_irq(struct irq_domain *domain, unsigned int hwirq, | |
364 | bool lookup, struct pt_regs *regs) | |
365 | { | |
366 | struct pt_regs *old_regs = set_irq_regs(regs); | |
367 | unsigned int irq = hwirq; | |
368 | int ret = 0; | |
369 | ||
370 | irq_enter(); | |
371 | ||
372 | #ifdef CONFIG_IRQ_DOMAIN | |
373 | if (lookup) | |
374 | irq = irq_find_mapping(domain, hwirq); | |
375 | #endif | |
376 | ||
377 | /* | |
378 | * Some hardware gives randomly wrong interrupts. Rather | |
379 | * than crashing, do something sensible. | |
380 | */ | |
381 | if (unlikely(!irq || irq >= nr_irqs)) { | |
382 | ack_bad_irq(irq); | |
383 | ret = -EINVAL; | |
384 | } else { | |
385 | generic_handle_irq(irq); | |
386 | } | |
387 | ||
388 | irq_exit(); | |
389 | set_irq_regs(old_regs); | |
390 | return ret; | |
391 | } | |
392 | #endif | |
393 | ||
1f5a5b87 TG |
394 | /* Dynamic interrupt handling */ |
395 | ||
396 | /** | |
397 | * irq_free_descs - free irq descriptors | |
398 | * @from: Start of descriptor range | |
399 | * @cnt: Number of consecutive irqs to free | |
400 | */ | |
401 | void irq_free_descs(unsigned int from, unsigned int cnt) | |
402 | { | |
1f5a5b87 TG |
403 | int i; |
404 | ||
405 | if (from >= nr_irqs || (from + cnt) > nr_irqs) | |
406 | return; | |
407 | ||
408 | for (i = 0; i < cnt; i++) | |
409 | free_desc(from + i); | |
410 | ||
a05a900a | 411 | mutex_lock(&sparse_irq_lock); |
1f5a5b87 | 412 | bitmap_clear(allocated_irqs, from, cnt); |
a05a900a | 413 | mutex_unlock(&sparse_irq_lock); |
1f5a5b87 | 414 | } |
edf76f83 | 415 | EXPORT_SYMBOL_GPL(irq_free_descs); |
1f5a5b87 TG |
416 | |
417 | /** | |
418 | * irq_alloc_descs - allocate and initialize a range of irq descriptors | |
419 | * @irq: Allocate for specific irq number if irq >= 0 | |
420 | * @from: Start the search from this irq number | |
421 | * @cnt: Number of consecutive irqs to allocate. | |
422 | * @node: Preferred node on which the irq descriptor should be allocated | |
d522a0d1 | 423 | * @owner: Owning module (can be NULL) |
1f5a5b87 TG |
424 | * |
425 | * Returns the first irq number or error code | |
426 | */ | |
427 | int __ref | |
b6873807 SAS |
428 | __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node, |
429 | struct module *owner) | |
1f5a5b87 | 430 | { |
1f5a5b87 TG |
431 | int start, ret; |
432 | ||
433 | if (!cnt) | |
434 | return -EINVAL; | |
435 | ||
c5182b88 MB |
436 | if (irq >= 0) { |
437 | if (from > irq) | |
438 | return -EINVAL; | |
439 | from = irq; | |
62a08ae2 TG |
440 | } else { |
441 | /* | |
442 | * For interrupts which are freely allocated the | |
443 | * architecture can force a lower bound to the @from | |
444 | * argument. x86 uses this to exclude the GSI space. | |
445 | */ | |
446 | from = arch_dynirq_lower_bound(from); | |
c5182b88 MB |
447 | } |
448 | ||
a05a900a | 449 | mutex_lock(&sparse_irq_lock); |
1f5a5b87 | 450 | |
ed4dea6e YL |
451 | start = bitmap_find_next_zero_area(allocated_irqs, IRQ_BITMAP_BITS, |
452 | from, cnt, 0); | |
1f5a5b87 TG |
453 | ret = -EEXIST; |
454 | if (irq >=0 && start != irq) | |
455 | goto err; | |
456 | ||
ed4dea6e YL |
457 | if (start + cnt > nr_irqs) { |
458 | ret = irq_expand_nr_irqs(start + cnt); | |
e7bcecb7 TG |
459 | if (ret) |
460 | goto err; | |
461 | } | |
1f5a5b87 TG |
462 | |
463 | bitmap_set(allocated_irqs, start, cnt); | |
a05a900a | 464 | mutex_unlock(&sparse_irq_lock); |
b6873807 | 465 | return alloc_descs(start, cnt, node, owner); |
1f5a5b87 TG |
466 | |
467 | err: | |
a05a900a | 468 | mutex_unlock(&sparse_irq_lock); |
1f5a5b87 TG |
469 | return ret; |
470 | } | |
b6873807 | 471 | EXPORT_SYMBOL_GPL(__irq_alloc_descs); |
1f5a5b87 | 472 | |
7b6ef126 TG |
473 | #ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ |
474 | /** | |
475 | * irq_alloc_hwirqs - Allocate an irq descriptor and initialize the hardware | |
476 | * @cnt: number of interrupts to allocate | |
477 | * @node: node on which to allocate | |
478 | * | |
479 | * Returns an interrupt number > 0 or 0, if the allocation fails. | |
480 | */ | |
481 | unsigned int irq_alloc_hwirqs(int cnt, int node) | |
482 | { | |
483 | int i, irq = __irq_alloc_descs(-1, 0, cnt, node, NULL); | |
484 | ||
485 | if (irq < 0) | |
486 | return 0; | |
487 | ||
488 | for (i = irq; cnt > 0; i++, cnt--) { | |
489 | if (arch_setup_hwirq(i, node)) | |
490 | goto err; | |
491 | irq_clear_status_flags(i, _IRQ_NOREQUEST); | |
492 | } | |
493 | return irq; | |
494 | ||
495 | err: | |
496 | for (i--; i >= irq; i--) { | |
497 | irq_set_status_flags(i, _IRQ_NOREQUEST | _IRQ_NOPROBE); | |
498 | arch_teardown_hwirq(i); | |
499 | } | |
500 | irq_free_descs(irq, cnt); | |
501 | return 0; | |
502 | } | |
503 | EXPORT_SYMBOL_GPL(irq_alloc_hwirqs); | |
504 | ||
505 | /** | |
506 | * irq_free_hwirqs - Free irq descriptor and cleanup the hardware | |
507 | * @from: Free from irq number | |
508 | * @cnt: number of interrupts to free | |
509 | * | |
510 | */ | |
511 | void irq_free_hwirqs(unsigned int from, int cnt) | |
512 | { | |
8844aad8 | 513 | int i, j; |
7b6ef126 | 514 | |
8844aad8 | 515 | for (i = from, j = cnt; j > 0; i++, j--) { |
7b6ef126 TG |
516 | irq_set_status_flags(i, _IRQ_NOREQUEST | _IRQ_NOPROBE); |
517 | arch_teardown_hwirq(i); | |
518 | } | |
519 | irq_free_descs(from, cnt); | |
520 | } | |
521 | EXPORT_SYMBOL_GPL(irq_free_hwirqs); | |
522 | #endif | |
523 | ||
a98d24b7 TG |
524 | /** |
525 | * irq_get_next_irq - get next allocated irq number | |
526 | * @offset: where to start the search | |
527 | * | |
528 | * Returns next irq number after offset or nr_irqs if none is found. | |
529 | */ | |
530 | unsigned int irq_get_next_irq(unsigned int offset) | |
531 | { | |
532 | return find_next_bit(allocated_irqs, nr_irqs, offset); | |
533 | } | |
534 | ||
d5eb4ad2 | 535 | struct irq_desc * |
31d9d9b6 MZ |
536 | __irq_get_desc_lock(unsigned int irq, unsigned long *flags, bool bus, |
537 | unsigned int check) | |
d5eb4ad2 TG |
538 | { |
539 | struct irq_desc *desc = irq_to_desc(irq); | |
540 | ||
541 | if (desc) { | |
31d9d9b6 MZ |
542 | if (check & _IRQ_DESC_CHECK) { |
543 | if ((check & _IRQ_DESC_PERCPU) && | |
544 | !irq_settings_is_per_cpu_devid(desc)) | |
545 | return NULL; | |
546 | ||
547 | if (!(check & _IRQ_DESC_PERCPU) && | |
548 | irq_settings_is_per_cpu_devid(desc)) | |
549 | return NULL; | |
550 | } | |
551 | ||
d5eb4ad2 TG |
552 | if (bus) |
553 | chip_bus_lock(desc); | |
554 | raw_spin_lock_irqsave(&desc->lock, *flags); | |
555 | } | |
556 | return desc; | |
557 | } | |
558 | ||
559 | void __irq_put_desc_unlock(struct irq_desc *desc, unsigned long flags, bool bus) | |
560 | { | |
561 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
562 | if (bus) | |
563 | chip_bus_sync_unlock(desc); | |
564 | } | |
565 | ||
31d9d9b6 MZ |
566 | int irq_set_percpu_devid(unsigned int irq) |
567 | { | |
568 | struct irq_desc *desc = irq_to_desc(irq); | |
569 | ||
570 | if (!desc) | |
571 | return -EINVAL; | |
572 | ||
573 | if (desc->percpu_enabled) | |
574 | return -EINVAL; | |
575 | ||
576 | desc->percpu_enabled = kzalloc(sizeof(*desc->percpu_enabled), GFP_KERNEL); | |
577 | ||
578 | if (!desc->percpu_enabled) | |
579 | return -ENOMEM; | |
580 | ||
581 | irq_set_percpu_devid_flags(irq); | |
582 | return 0; | |
583 | } | |
584 | ||
792d0018 TG |
585 | void kstat_incr_irq_this_cpu(unsigned int irq) |
586 | { | |
b51bf95c | 587 | kstat_incr_irqs_this_cpu(irq_to_desc(irq)); |
792d0018 TG |
588 | } |
589 | ||
c291ee62 TG |
590 | /** |
591 | * kstat_irqs_cpu - Get the statistics for an interrupt on a cpu | |
592 | * @irq: The interrupt number | |
593 | * @cpu: The cpu number | |
594 | * | |
595 | * Returns the sum of interrupt counts on @cpu since boot for | |
596 | * @irq. The caller must ensure that the interrupt is not removed | |
597 | * concurrently. | |
598 | */ | |
3795de23 TG |
599 | unsigned int kstat_irqs_cpu(unsigned int irq, int cpu) |
600 | { | |
601 | struct irq_desc *desc = irq_to_desc(irq); | |
6c9ae009 ED |
602 | |
603 | return desc && desc->kstat_irqs ? | |
604 | *per_cpu_ptr(desc->kstat_irqs, cpu) : 0; | |
3795de23 | 605 | } |
478735e3 | 606 | |
c291ee62 TG |
607 | /** |
608 | * kstat_irqs - Get the statistics for an interrupt | |
609 | * @irq: The interrupt number | |
610 | * | |
611 | * Returns the sum of interrupt counts on all cpus since boot for | |
612 | * @irq. The caller must ensure that the interrupt is not removed | |
613 | * concurrently. | |
614 | */ | |
478735e3 KH |
615 | unsigned int kstat_irqs(unsigned int irq) |
616 | { | |
617 | struct irq_desc *desc = irq_to_desc(irq); | |
618 | int cpu; | |
5e9662fa | 619 | unsigned int sum = 0; |
478735e3 | 620 | |
6c9ae009 | 621 | if (!desc || !desc->kstat_irqs) |
478735e3 KH |
622 | return 0; |
623 | for_each_possible_cpu(cpu) | |
6c9ae009 | 624 | sum += *per_cpu_ptr(desc->kstat_irqs, cpu); |
478735e3 KH |
625 | return sum; |
626 | } | |
c291ee62 TG |
627 | |
628 | /** | |
629 | * kstat_irqs_usr - Get the statistics for an interrupt | |
630 | * @irq: The interrupt number | |
631 | * | |
632 | * Returns the sum of interrupt counts on all cpus since boot for | |
633 | * @irq. Contrary to kstat_irqs() this can be called from any | |
634 | * preemptible context. It's protected against concurrent removal of | |
635 | * an interrupt descriptor when sparse irqs are enabled. | |
636 | */ | |
637 | unsigned int kstat_irqs_usr(unsigned int irq) | |
638 | { | |
7df0b278 | 639 | unsigned int sum; |
c291ee62 TG |
640 | |
641 | irq_lock_sparse(); | |
642 | sum = kstat_irqs(irq); | |
643 | irq_unlock_sparse(); | |
644 | return sum; | |
645 | } |