Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * linux/kernel/irq/manage.c | |
3 | * | |
a34db9b2 IM |
4 | * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar |
5 | * Copyright (C) 2005-2006 Thomas Gleixner | |
1da177e4 LT |
6 | * |
7 | * This file contains driver APIs to the irq subsystem. | |
8 | */ | |
9 | ||
97fd75b7 AM |
10 | #define pr_fmt(fmt) "genirq: " fmt |
11 | ||
1da177e4 | 12 | #include <linux/irq.h> |
3aa551c9 | 13 | #include <linux/kthread.h> |
1da177e4 LT |
14 | #include <linux/module.h> |
15 | #include <linux/random.h> | |
16 | #include <linux/interrupt.h> | |
1aeb272c | 17 | #include <linux/slab.h> |
3aa551c9 | 18 | #include <linux/sched.h> |
8bd75c77 | 19 | #include <linux/sched/rt.h> |
4d1d61a6 | 20 | #include <linux/task_work.h> |
1da177e4 LT |
21 | |
22 | #include "internals.h" | |
23 | ||
8d32a307 TG |
24 | #ifdef CONFIG_IRQ_FORCED_THREADING |
25 | __read_mostly bool force_irqthreads; | |
26 | ||
27 | static int __init setup_forced_irqthreads(char *arg) | |
28 | { | |
29 | force_irqthreads = true; | |
30 | return 0; | |
31 | } | |
32 | early_param("threadirqs", setup_forced_irqthreads); | |
33 | #endif | |
34 | ||
18258f72 | 35 | static void __synchronize_hardirq(struct irq_desc *desc) |
1da177e4 | 36 | { |
32f4125e | 37 | bool inprogress; |
1da177e4 | 38 | |
a98ce5c6 HX |
39 | do { |
40 | unsigned long flags; | |
41 | ||
42 | /* | |
43 | * Wait until we're out of the critical section. This might | |
44 | * give the wrong answer due to the lack of memory barriers. | |
45 | */ | |
32f4125e | 46 | while (irqd_irq_inprogress(&desc->irq_data)) |
a98ce5c6 HX |
47 | cpu_relax(); |
48 | ||
49 | /* Ok, that indicated we're done: double-check carefully. */ | |
239007b8 | 50 | raw_spin_lock_irqsave(&desc->lock, flags); |
32f4125e | 51 | inprogress = irqd_irq_inprogress(&desc->irq_data); |
239007b8 | 52 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
a98ce5c6 HX |
53 | |
54 | /* Oops, that failed? */ | |
32f4125e | 55 | } while (inprogress); |
18258f72 TG |
56 | } |
57 | ||
58 | /** | |
59 | * synchronize_hardirq - wait for pending hard IRQ handlers (on other CPUs) | |
60 | * @irq: interrupt number to wait for | |
61 | * | |
62 | * This function waits for any pending hard IRQ handlers for this | |
63 | * interrupt to complete before returning. If you use this | |
64 | * function while holding a resource the IRQ handler may need you | |
65 | * will deadlock. It does not take associated threaded handlers | |
66 | * into account. | |
67 | * | |
68 | * Do not use this for shutdown scenarios where you must be sure | |
69 | * that all parts (hardirq and threaded handler) have completed. | |
70 | * | |
02cea395 PZ |
71 | * Returns: false if a threaded handler is active. |
72 | * | |
18258f72 TG |
73 | * This function may be called - with care - from IRQ context. |
74 | */ | |
02cea395 | 75 | bool synchronize_hardirq(unsigned int irq) |
18258f72 TG |
76 | { |
77 | struct irq_desc *desc = irq_to_desc(irq); | |
3aa551c9 | 78 | |
02cea395 | 79 | if (desc) { |
18258f72 | 80 | __synchronize_hardirq(desc); |
02cea395 PZ |
81 | return !atomic_read(&desc->threads_active); |
82 | } | |
83 | ||
84 | return true; | |
18258f72 TG |
85 | } |
86 | EXPORT_SYMBOL(synchronize_hardirq); | |
87 | ||
88 | /** | |
89 | * synchronize_irq - wait for pending IRQ handlers (on other CPUs) | |
90 | * @irq: interrupt number to wait for | |
91 | * | |
92 | * This function waits for any pending IRQ handlers for this interrupt | |
93 | * to complete before returning. If you use this function while | |
94 | * holding a resource the IRQ handler may need you will deadlock. | |
95 | * | |
96 | * This function may be called - with care - from IRQ context. | |
97 | */ | |
98 | void synchronize_irq(unsigned int irq) | |
99 | { | |
100 | struct irq_desc *desc = irq_to_desc(irq); | |
101 | ||
102 | if (desc) { | |
103 | __synchronize_hardirq(desc); | |
104 | /* | |
105 | * We made sure that no hardirq handler is | |
106 | * running. Now verify that no threaded handlers are | |
107 | * active. | |
108 | */ | |
109 | wait_event(desc->wait_for_threads, | |
110 | !atomic_read(&desc->threads_active)); | |
111 | } | |
1da177e4 | 112 | } |
1da177e4 LT |
113 | EXPORT_SYMBOL(synchronize_irq); |
114 | ||
3aa551c9 TG |
115 | #ifdef CONFIG_SMP |
116 | cpumask_var_t irq_default_affinity; | |
117 | ||
771ee3b0 TG |
118 | /** |
119 | * irq_can_set_affinity - Check if the affinity of a given irq can be set | |
120 | * @irq: Interrupt to check | |
121 | * | |
122 | */ | |
123 | int irq_can_set_affinity(unsigned int irq) | |
124 | { | |
08678b08 | 125 | struct irq_desc *desc = irq_to_desc(irq); |
771ee3b0 | 126 | |
bce43032 TG |
127 | if (!desc || !irqd_can_balance(&desc->irq_data) || |
128 | !desc->irq_data.chip || !desc->irq_data.chip->irq_set_affinity) | |
771ee3b0 TG |
129 | return 0; |
130 | ||
131 | return 1; | |
132 | } | |
133 | ||
591d2fb0 TG |
134 | /** |
135 | * irq_set_thread_affinity - Notify irq threads to adjust affinity | |
136 | * @desc: irq descriptor which has affitnity changed | |
137 | * | |
138 | * We just set IRQTF_AFFINITY and delegate the affinity setting | |
139 | * to the interrupt thread itself. We can not call | |
140 | * set_cpus_allowed_ptr() here as we hold desc->lock and this | |
141 | * code can be called from hard interrupt context. | |
142 | */ | |
143 | void irq_set_thread_affinity(struct irq_desc *desc) | |
3aa551c9 TG |
144 | { |
145 | struct irqaction *action = desc->action; | |
146 | ||
147 | while (action) { | |
148 | if (action->thread) | |
591d2fb0 | 149 | set_bit(IRQTF_AFFINITY, &action->thread_flags); |
3aa551c9 TG |
150 | action = action->next; |
151 | } | |
152 | } | |
153 | ||
1fa46f1f | 154 | #ifdef CONFIG_GENERIC_PENDING_IRQ |
0ef5ca1e | 155 | static inline bool irq_can_move_pcntxt(struct irq_data *data) |
1fa46f1f | 156 | { |
0ef5ca1e | 157 | return irqd_can_move_in_process_context(data); |
1fa46f1f | 158 | } |
0ef5ca1e | 159 | static inline bool irq_move_pending(struct irq_data *data) |
1fa46f1f | 160 | { |
0ef5ca1e | 161 | return irqd_is_setaffinity_pending(data); |
1fa46f1f TG |
162 | } |
163 | static inline void | |
164 | irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) | |
165 | { | |
166 | cpumask_copy(desc->pending_mask, mask); | |
167 | } | |
168 | static inline void | |
169 | irq_get_pending(struct cpumask *mask, struct irq_desc *desc) | |
170 | { | |
171 | cpumask_copy(mask, desc->pending_mask); | |
172 | } | |
173 | #else | |
0ef5ca1e | 174 | static inline bool irq_can_move_pcntxt(struct irq_data *data) { return true; } |
cd22c0e4 | 175 | static inline bool irq_move_pending(struct irq_data *data) { return false; } |
1fa46f1f TG |
176 | static inline void |
177 | irq_copy_pending(struct irq_desc *desc, const struct cpumask *mask) { } | |
178 | static inline void | |
179 | irq_get_pending(struct cpumask *mask, struct irq_desc *desc) { } | |
180 | #endif | |
181 | ||
818b0f3b JL |
182 | int irq_do_set_affinity(struct irq_data *data, const struct cpumask *mask, |
183 | bool force) | |
184 | { | |
185 | struct irq_desc *desc = irq_data_to_desc(data); | |
186 | struct irq_chip *chip = irq_data_get_irq_chip(data); | |
187 | int ret; | |
188 | ||
01f8fa4f | 189 | ret = chip->irq_set_affinity(data, mask, force); |
818b0f3b JL |
190 | switch (ret) { |
191 | case IRQ_SET_MASK_OK: | |
2cb62547 | 192 | case IRQ_SET_MASK_OK_DONE: |
818b0f3b JL |
193 | cpumask_copy(data->affinity, mask); |
194 | case IRQ_SET_MASK_OK_NOCOPY: | |
195 | irq_set_thread_affinity(desc); | |
196 | ret = 0; | |
197 | } | |
198 | ||
199 | return ret; | |
200 | } | |
201 | ||
01f8fa4f TG |
202 | int irq_set_affinity_locked(struct irq_data *data, const struct cpumask *mask, |
203 | bool force) | |
771ee3b0 | 204 | { |
c2d0c555 DD |
205 | struct irq_chip *chip = irq_data_get_irq_chip(data); |
206 | struct irq_desc *desc = irq_data_to_desc(data); | |
1fa46f1f | 207 | int ret = 0; |
771ee3b0 | 208 | |
c2d0c555 | 209 | if (!chip || !chip->irq_set_affinity) |
771ee3b0 TG |
210 | return -EINVAL; |
211 | ||
0ef5ca1e | 212 | if (irq_can_move_pcntxt(data)) { |
01f8fa4f | 213 | ret = irq_do_set_affinity(data, mask, force); |
1fa46f1f | 214 | } else { |
c2d0c555 | 215 | irqd_set_move_pending(data); |
1fa46f1f | 216 | irq_copy_pending(desc, mask); |
57b150cc | 217 | } |
1fa46f1f | 218 | |
cd7eab44 BH |
219 | if (desc->affinity_notify) { |
220 | kref_get(&desc->affinity_notify->kref); | |
221 | schedule_work(&desc->affinity_notify->work); | |
222 | } | |
c2d0c555 DD |
223 | irqd_set(data, IRQD_AFFINITY_SET); |
224 | ||
225 | return ret; | |
226 | } | |
227 | ||
01f8fa4f | 228 | int __irq_set_affinity(unsigned int irq, const struct cpumask *mask, bool force) |
c2d0c555 DD |
229 | { |
230 | struct irq_desc *desc = irq_to_desc(irq); | |
231 | unsigned long flags; | |
232 | int ret; | |
233 | ||
234 | if (!desc) | |
235 | return -EINVAL; | |
236 | ||
237 | raw_spin_lock_irqsave(&desc->lock, flags); | |
01f8fa4f | 238 | ret = irq_set_affinity_locked(irq_desc_get_irq_data(desc), mask, force); |
239007b8 | 239 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1fa46f1f | 240 | return ret; |
771ee3b0 TG |
241 | } |
242 | ||
e7a297b0 PWJ |
243 | int irq_set_affinity_hint(unsigned int irq, const struct cpumask *m) |
244 | { | |
e7a297b0 | 245 | unsigned long flags; |
31d9d9b6 | 246 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
e7a297b0 PWJ |
247 | |
248 | if (!desc) | |
249 | return -EINVAL; | |
e7a297b0 | 250 | desc->affinity_hint = m; |
02725e74 | 251 | irq_put_desc_unlock(desc, flags); |
e2e64a93 | 252 | /* set the initial affinity to prevent every interrupt being on CPU0 */ |
4fe7ffb7 JB |
253 | if (m) |
254 | __irq_set_affinity(irq, m, false); | |
e7a297b0 PWJ |
255 | return 0; |
256 | } | |
257 | EXPORT_SYMBOL_GPL(irq_set_affinity_hint); | |
258 | ||
cd7eab44 BH |
259 | static void irq_affinity_notify(struct work_struct *work) |
260 | { | |
261 | struct irq_affinity_notify *notify = | |
262 | container_of(work, struct irq_affinity_notify, work); | |
263 | struct irq_desc *desc = irq_to_desc(notify->irq); | |
264 | cpumask_var_t cpumask; | |
265 | unsigned long flags; | |
266 | ||
1fa46f1f | 267 | if (!desc || !alloc_cpumask_var(&cpumask, GFP_KERNEL)) |
cd7eab44 BH |
268 | goto out; |
269 | ||
270 | raw_spin_lock_irqsave(&desc->lock, flags); | |
0ef5ca1e | 271 | if (irq_move_pending(&desc->irq_data)) |
1fa46f1f | 272 | irq_get_pending(cpumask, desc); |
cd7eab44 | 273 | else |
1fb0ef31 | 274 | cpumask_copy(cpumask, desc->irq_data.affinity); |
cd7eab44 BH |
275 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
276 | ||
277 | notify->notify(notify, cpumask); | |
278 | ||
279 | free_cpumask_var(cpumask); | |
280 | out: | |
281 | kref_put(¬ify->kref, notify->release); | |
282 | } | |
283 | ||
284 | /** | |
285 | * irq_set_affinity_notifier - control notification of IRQ affinity changes | |
286 | * @irq: Interrupt for which to enable/disable notification | |
287 | * @notify: Context for notification, or %NULL to disable | |
288 | * notification. Function pointers must be initialised; | |
289 | * the other fields will be initialised by this function. | |
290 | * | |
291 | * Must be called in process context. Notification may only be enabled | |
292 | * after the IRQ is allocated and must be disabled before the IRQ is | |
293 | * freed using free_irq(). | |
294 | */ | |
295 | int | |
296 | irq_set_affinity_notifier(unsigned int irq, struct irq_affinity_notify *notify) | |
297 | { | |
298 | struct irq_desc *desc = irq_to_desc(irq); | |
299 | struct irq_affinity_notify *old_notify; | |
300 | unsigned long flags; | |
301 | ||
302 | /* The release function is promised process context */ | |
303 | might_sleep(); | |
304 | ||
305 | if (!desc) | |
306 | return -EINVAL; | |
307 | ||
308 | /* Complete initialisation of *notify */ | |
309 | if (notify) { | |
310 | notify->irq = irq; | |
311 | kref_init(¬ify->kref); | |
312 | INIT_WORK(¬ify->work, irq_affinity_notify); | |
313 | } | |
314 | ||
315 | raw_spin_lock_irqsave(&desc->lock, flags); | |
316 | old_notify = desc->affinity_notify; | |
317 | desc->affinity_notify = notify; | |
318 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
319 | ||
320 | if (old_notify) | |
321 | kref_put(&old_notify->kref, old_notify->release); | |
322 | ||
323 | return 0; | |
324 | } | |
325 | EXPORT_SYMBOL_GPL(irq_set_affinity_notifier); | |
326 | ||
18404756 MK |
327 | #ifndef CONFIG_AUTO_IRQ_AFFINITY |
328 | /* | |
329 | * Generic version of the affinity autoselector. | |
330 | */ | |
3b8249e7 TG |
331 | static int |
332 | setup_affinity(unsigned int irq, struct irq_desc *desc, struct cpumask *mask) | |
18404756 | 333 | { |
569bda8d | 334 | struct cpumask *set = irq_default_affinity; |
818b0f3b | 335 | int node = desc->irq_data.node; |
569bda8d | 336 | |
b008207c | 337 | /* Excludes PER_CPU and NO_BALANCE interrupts */ |
18404756 MK |
338 | if (!irq_can_set_affinity(irq)) |
339 | return 0; | |
340 | ||
f6d87f4b TG |
341 | /* |
342 | * Preserve an userspace affinity setup, but make sure that | |
343 | * one of the targets is online. | |
344 | */ | |
2bdd1055 | 345 | if (irqd_has_set(&desc->irq_data, IRQD_AFFINITY_SET)) { |
569bda8d TG |
346 | if (cpumask_intersects(desc->irq_data.affinity, |
347 | cpu_online_mask)) | |
348 | set = desc->irq_data.affinity; | |
0c6f8a8b | 349 | else |
2bdd1055 | 350 | irqd_clear(&desc->irq_data, IRQD_AFFINITY_SET); |
f6d87f4b | 351 | } |
18404756 | 352 | |
3b8249e7 | 353 | cpumask_and(mask, cpu_online_mask, set); |
241fc640 PB |
354 | if (node != NUMA_NO_NODE) { |
355 | const struct cpumask *nodemask = cpumask_of_node(node); | |
356 | ||
357 | /* make sure at least one of the cpus in nodemask is online */ | |
358 | if (cpumask_intersects(mask, nodemask)) | |
359 | cpumask_and(mask, mask, nodemask); | |
360 | } | |
818b0f3b | 361 | irq_do_set_affinity(&desc->irq_data, mask, false); |
18404756 MK |
362 | return 0; |
363 | } | |
f6d87f4b | 364 | #else |
3b8249e7 TG |
365 | static inline int |
366 | setup_affinity(unsigned int irq, struct irq_desc *d, struct cpumask *mask) | |
f6d87f4b TG |
367 | { |
368 | return irq_select_affinity(irq); | |
369 | } | |
18404756 MK |
370 | #endif |
371 | ||
f6d87f4b TG |
372 | /* |
373 | * Called when affinity is set via /proc/irq | |
374 | */ | |
3b8249e7 | 375 | int irq_select_affinity_usr(unsigned int irq, struct cpumask *mask) |
f6d87f4b TG |
376 | { |
377 | struct irq_desc *desc = irq_to_desc(irq); | |
378 | unsigned long flags; | |
379 | int ret; | |
380 | ||
239007b8 | 381 | raw_spin_lock_irqsave(&desc->lock, flags); |
3b8249e7 | 382 | ret = setup_affinity(irq, desc, mask); |
239007b8 | 383 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
f6d87f4b TG |
384 | return ret; |
385 | } | |
386 | ||
387 | #else | |
3b8249e7 TG |
388 | static inline int |
389 | setup_affinity(unsigned int irq, struct irq_desc *desc, struct cpumask *mask) | |
f6d87f4b TG |
390 | { |
391 | return 0; | |
392 | } | |
1da177e4 LT |
393 | #endif |
394 | ||
8df2e02c | 395 | void __disable_irq(struct irq_desc *desc, unsigned int irq) |
0a0c5168 | 396 | { |
3aae994f | 397 | if (!desc->depth++) |
87923470 | 398 | irq_disable(desc); |
0a0c5168 RW |
399 | } |
400 | ||
02725e74 TG |
401 | static int __disable_irq_nosync(unsigned int irq) |
402 | { | |
403 | unsigned long flags; | |
31d9d9b6 | 404 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
02725e74 TG |
405 | |
406 | if (!desc) | |
407 | return -EINVAL; | |
8df2e02c | 408 | __disable_irq(desc, irq); |
02725e74 TG |
409 | irq_put_desc_busunlock(desc, flags); |
410 | return 0; | |
411 | } | |
412 | ||
1da177e4 LT |
413 | /** |
414 | * disable_irq_nosync - disable an irq without waiting | |
415 | * @irq: Interrupt to disable | |
416 | * | |
417 | * Disable the selected interrupt line. Disables and Enables are | |
418 | * nested. | |
419 | * Unlike disable_irq(), this function does not ensure existing | |
420 | * instances of the IRQ handler have completed before returning. | |
421 | * | |
422 | * This function may be called from IRQ context. | |
423 | */ | |
424 | void disable_irq_nosync(unsigned int irq) | |
425 | { | |
02725e74 | 426 | __disable_irq_nosync(irq); |
1da177e4 | 427 | } |
1da177e4 LT |
428 | EXPORT_SYMBOL(disable_irq_nosync); |
429 | ||
430 | /** | |
431 | * disable_irq - disable an irq and wait for completion | |
432 | * @irq: Interrupt to disable | |
433 | * | |
434 | * Disable the selected interrupt line. Enables and Disables are | |
435 | * nested. | |
436 | * This function waits for any pending IRQ handlers for this interrupt | |
437 | * to complete before returning. If you use this function while | |
438 | * holding a resource the IRQ handler may need you will deadlock. | |
439 | * | |
440 | * This function may be called - with care - from IRQ context. | |
441 | */ | |
442 | void disable_irq(unsigned int irq) | |
443 | { | |
02725e74 | 444 | if (!__disable_irq_nosync(irq)) |
1da177e4 LT |
445 | synchronize_irq(irq); |
446 | } | |
1da177e4 LT |
447 | EXPORT_SYMBOL(disable_irq); |
448 | ||
02cea395 PZ |
449 | /** |
450 | * disable_hardirq - disables an irq and waits for hardirq completion | |
451 | * @irq: Interrupt to disable | |
452 | * | |
453 | * Disable the selected interrupt line. Enables and Disables are | |
454 | * nested. | |
455 | * This function waits for any pending hard IRQ handlers for this | |
456 | * interrupt to complete before returning. If you use this function while | |
457 | * holding a resource the hard IRQ handler may need you will deadlock. | |
458 | * | |
459 | * When used to optimistically disable an interrupt from atomic context | |
460 | * the return value must be checked. | |
461 | * | |
462 | * Returns: false if a threaded handler is active. | |
463 | * | |
464 | * This function may be called - with care - from IRQ context. | |
465 | */ | |
466 | bool disable_hardirq(unsigned int irq) | |
467 | { | |
468 | if (!__disable_irq_nosync(irq)) | |
469 | return synchronize_hardirq(irq); | |
470 | ||
471 | return false; | |
472 | } | |
473 | EXPORT_SYMBOL_GPL(disable_hardirq); | |
474 | ||
8df2e02c | 475 | void __enable_irq(struct irq_desc *desc, unsigned int irq) |
1adb0850 TG |
476 | { |
477 | switch (desc->depth) { | |
478 | case 0: | |
0a0c5168 | 479 | err_out: |
b8c512f6 | 480 | WARN(1, KERN_WARNING "Unbalanced enable for IRQ %d\n", irq); |
1adb0850 TG |
481 | break; |
482 | case 1: { | |
c531e836 | 483 | if (desc->istate & IRQS_SUSPENDED) |
0a0c5168 | 484 | goto err_out; |
1adb0850 | 485 | /* Prevent probing on this irq: */ |
1ccb4e61 | 486 | irq_settings_set_noprobe(desc); |
3aae994f | 487 | irq_enable(desc); |
1adb0850 TG |
488 | check_irq_resend(desc, irq); |
489 | /* fall-through */ | |
490 | } | |
491 | default: | |
492 | desc->depth--; | |
493 | } | |
494 | } | |
495 | ||
1da177e4 LT |
496 | /** |
497 | * enable_irq - enable handling of an irq | |
498 | * @irq: Interrupt to enable | |
499 | * | |
500 | * Undoes the effect of one call to disable_irq(). If this | |
501 | * matches the last disable, processing of interrupts on this | |
502 | * IRQ line is re-enabled. | |
503 | * | |
70aedd24 | 504 | * This function may be called from IRQ context only when |
6b8ff312 | 505 | * desc->irq_data.chip->bus_lock and desc->chip->bus_sync_unlock are NULL ! |
1da177e4 LT |
506 | */ |
507 | void enable_irq(unsigned int irq) | |
508 | { | |
1da177e4 | 509 | unsigned long flags; |
31d9d9b6 | 510 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
1da177e4 | 511 | |
7d94f7ca | 512 | if (!desc) |
c2b5a251 | 513 | return; |
50f7c032 TG |
514 | if (WARN(!desc->irq_data.chip, |
515 | KERN_ERR "enable_irq before setup/request_irq: irq %u\n", irq)) | |
02725e74 | 516 | goto out; |
2656c366 | 517 | |
8df2e02c | 518 | __enable_irq(desc, irq); |
02725e74 TG |
519 | out: |
520 | irq_put_desc_busunlock(desc, flags); | |
1da177e4 | 521 | } |
1da177e4 LT |
522 | EXPORT_SYMBOL(enable_irq); |
523 | ||
0c5d1eb7 | 524 | static int set_irq_wake_real(unsigned int irq, unsigned int on) |
2db87321 | 525 | { |
08678b08 | 526 | struct irq_desc *desc = irq_to_desc(irq); |
2db87321 UKK |
527 | int ret = -ENXIO; |
528 | ||
60f96b41 SS |
529 | if (irq_desc_get_chip(desc)->flags & IRQCHIP_SKIP_SET_WAKE) |
530 | return 0; | |
531 | ||
2f7e99bb TG |
532 | if (desc->irq_data.chip->irq_set_wake) |
533 | ret = desc->irq_data.chip->irq_set_wake(&desc->irq_data, on); | |
2db87321 UKK |
534 | |
535 | return ret; | |
536 | } | |
537 | ||
ba9a2331 | 538 | /** |
a0cd9ca2 | 539 | * irq_set_irq_wake - control irq power management wakeup |
ba9a2331 TG |
540 | * @irq: interrupt to control |
541 | * @on: enable/disable power management wakeup | |
542 | * | |
15a647eb DB |
543 | * Enable/disable power management wakeup mode, which is |
544 | * disabled by default. Enables and disables must match, | |
545 | * just as they match for non-wakeup mode support. | |
546 | * | |
547 | * Wakeup mode lets this IRQ wake the system from sleep | |
548 | * states like "suspend to RAM". | |
ba9a2331 | 549 | */ |
a0cd9ca2 | 550 | int irq_set_irq_wake(unsigned int irq, unsigned int on) |
ba9a2331 | 551 | { |
ba9a2331 | 552 | unsigned long flags; |
31d9d9b6 | 553 | struct irq_desc *desc = irq_get_desc_buslock(irq, &flags, IRQ_GET_DESC_CHECK_GLOBAL); |
2db87321 | 554 | int ret = 0; |
ba9a2331 | 555 | |
13863a66 JJ |
556 | if (!desc) |
557 | return -EINVAL; | |
558 | ||
15a647eb DB |
559 | /* wakeup-capable irqs can be shared between drivers that |
560 | * don't need to have the same sleep mode behaviors. | |
561 | */ | |
15a647eb | 562 | if (on) { |
2db87321 UKK |
563 | if (desc->wake_depth++ == 0) { |
564 | ret = set_irq_wake_real(irq, on); | |
565 | if (ret) | |
566 | desc->wake_depth = 0; | |
567 | else | |
7f94226f | 568 | irqd_set(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 569 | } |
15a647eb DB |
570 | } else { |
571 | if (desc->wake_depth == 0) { | |
7a2c4770 | 572 | WARN(1, "Unbalanced IRQ %d wake disable\n", irq); |
2db87321 UKK |
573 | } else if (--desc->wake_depth == 0) { |
574 | ret = set_irq_wake_real(irq, on); | |
575 | if (ret) | |
576 | desc->wake_depth = 1; | |
577 | else | |
7f94226f | 578 | irqd_clear(&desc->irq_data, IRQD_WAKEUP_STATE); |
2db87321 | 579 | } |
15a647eb | 580 | } |
02725e74 | 581 | irq_put_desc_busunlock(desc, flags); |
ba9a2331 TG |
582 | return ret; |
583 | } | |
a0cd9ca2 | 584 | EXPORT_SYMBOL(irq_set_irq_wake); |
ba9a2331 | 585 | |
1da177e4 LT |
586 | /* |
587 | * Internal function that tells the architecture code whether a | |
588 | * particular irq has been exclusively allocated or is available | |
589 | * for driver use. | |
590 | */ | |
591 | int can_request_irq(unsigned int irq, unsigned long irqflags) | |
592 | { | |
cc8c3b78 | 593 | unsigned long flags; |
31d9d9b6 | 594 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); |
02725e74 | 595 | int canrequest = 0; |
1da177e4 | 596 | |
7d94f7ca YL |
597 | if (!desc) |
598 | return 0; | |
599 | ||
02725e74 | 600 | if (irq_settings_can_request(desc)) { |
2779db8d BH |
601 | if (!desc->action || |
602 | irqflags & desc->action->flags & IRQF_SHARED) | |
603 | canrequest = 1; | |
02725e74 TG |
604 | } |
605 | irq_put_desc_unlock(desc, flags); | |
606 | return canrequest; | |
1da177e4 LT |
607 | } |
608 | ||
0c5d1eb7 | 609 | int __irq_set_trigger(struct irq_desc *desc, unsigned int irq, |
b2ba2c30 | 610 | unsigned long flags) |
82736f4d | 611 | { |
6b8ff312 | 612 | struct irq_chip *chip = desc->irq_data.chip; |
d4d5e089 | 613 | int ret, unmask = 0; |
82736f4d | 614 | |
b2ba2c30 | 615 | if (!chip || !chip->irq_set_type) { |
82736f4d UKK |
616 | /* |
617 | * IRQF_TRIGGER_* but the PIC does not support multiple | |
618 | * flow-types? | |
619 | */ | |
97fd75b7 | 620 | pr_debug("No set_type function for IRQ %d (%s)\n", irq, |
f5d89470 | 621 | chip ? (chip->name ? : "unknown") : "unknown"); |
82736f4d UKK |
622 | return 0; |
623 | } | |
624 | ||
876dbd4c | 625 | flags &= IRQ_TYPE_SENSE_MASK; |
d4d5e089 TG |
626 | |
627 | if (chip->flags & IRQCHIP_SET_TYPE_MASKED) { | |
32f4125e | 628 | if (!irqd_irq_masked(&desc->irq_data)) |
d4d5e089 | 629 | mask_irq(desc); |
32f4125e | 630 | if (!irqd_irq_disabled(&desc->irq_data)) |
d4d5e089 TG |
631 | unmask = 1; |
632 | } | |
633 | ||
f2b662da | 634 | /* caller masked out all except trigger mode flags */ |
b2ba2c30 | 635 | ret = chip->irq_set_type(&desc->irq_data, flags); |
82736f4d | 636 | |
876dbd4c TG |
637 | switch (ret) { |
638 | case IRQ_SET_MASK_OK: | |
2cb62547 | 639 | case IRQ_SET_MASK_OK_DONE: |
876dbd4c TG |
640 | irqd_clear(&desc->irq_data, IRQD_TRIGGER_MASK); |
641 | irqd_set(&desc->irq_data, flags); | |
642 | ||
643 | case IRQ_SET_MASK_OK_NOCOPY: | |
644 | flags = irqd_get_trigger_type(&desc->irq_data); | |
645 | irq_settings_set_trigger_mask(desc, flags); | |
646 | irqd_clear(&desc->irq_data, IRQD_LEVEL); | |
647 | irq_settings_clr_level(desc); | |
648 | if (flags & IRQ_TYPE_LEVEL_MASK) { | |
649 | irq_settings_set_level(desc); | |
650 | irqd_set(&desc->irq_data, IRQD_LEVEL); | |
651 | } | |
46732475 | 652 | |
d4d5e089 | 653 | ret = 0; |
8fff39e0 | 654 | break; |
876dbd4c | 655 | default: |
97fd75b7 | 656 | pr_err("Setting trigger mode %lu for irq %u failed (%pF)\n", |
876dbd4c | 657 | flags, irq, chip->irq_set_type); |
0c5d1eb7 | 658 | } |
d4d5e089 TG |
659 | if (unmask) |
660 | unmask_irq(desc); | |
82736f4d UKK |
661 | return ret; |
662 | } | |
663 | ||
293a7a0a TG |
664 | #ifdef CONFIG_HARDIRQS_SW_RESEND |
665 | int irq_set_parent(int irq, int parent_irq) | |
666 | { | |
667 | unsigned long flags; | |
668 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, 0); | |
669 | ||
670 | if (!desc) | |
671 | return -EINVAL; | |
672 | ||
673 | desc->parent_irq = parent_irq; | |
674 | ||
675 | irq_put_desc_unlock(desc, flags); | |
676 | return 0; | |
677 | } | |
678 | #endif | |
679 | ||
b25c340c TG |
680 | /* |
681 | * Default primary interrupt handler for threaded interrupts. Is | |
682 | * assigned as primary handler when request_threaded_irq is called | |
683 | * with handler == NULL. Useful for oneshot interrupts. | |
684 | */ | |
685 | static irqreturn_t irq_default_primary_handler(int irq, void *dev_id) | |
686 | { | |
687 | return IRQ_WAKE_THREAD; | |
688 | } | |
689 | ||
399b5da2 TG |
690 | /* |
691 | * Primary handler for nested threaded interrupts. Should never be | |
692 | * called. | |
693 | */ | |
694 | static irqreturn_t irq_nested_primary_handler(int irq, void *dev_id) | |
695 | { | |
696 | WARN(1, "Primary handler called for nested irq %d\n", irq); | |
697 | return IRQ_NONE; | |
698 | } | |
699 | ||
3aa551c9 TG |
700 | static int irq_wait_for_interrupt(struct irqaction *action) |
701 | { | |
550acb19 IY |
702 | set_current_state(TASK_INTERRUPTIBLE); |
703 | ||
3aa551c9 | 704 | while (!kthread_should_stop()) { |
f48fe81e TG |
705 | |
706 | if (test_and_clear_bit(IRQTF_RUNTHREAD, | |
707 | &action->thread_flags)) { | |
3aa551c9 TG |
708 | __set_current_state(TASK_RUNNING); |
709 | return 0; | |
f48fe81e TG |
710 | } |
711 | schedule(); | |
550acb19 | 712 | set_current_state(TASK_INTERRUPTIBLE); |
3aa551c9 | 713 | } |
550acb19 | 714 | __set_current_state(TASK_RUNNING); |
3aa551c9 TG |
715 | return -1; |
716 | } | |
717 | ||
b25c340c TG |
718 | /* |
719 | * Oneshot interrupts keep the irq line masked until the threaded | |
720 | * handler finished. unmask if the interrupt has not been disabled and | |
721 | * is marked MASKED. | |
722 | */ | |
b5faba21 | 723 | static void irq_finalize_oneshot(struct irq_desc *desc, |
f3f79e38 | 724 | struct irqaction *action) |
b25c340c | 725 | { |
b5faba21 TG |
726 | if (!(desc->istate & IRQS_ONESHOT)) |
727 | return; | |
0b1adaa0 | 728 | again: |
3876ec9e | 729 | chip_bus_lock(desc); |
239007b8 | 730 | raw_spin_lock_irq(&desc->lock); |
0b1adaa0 TG |
731 | |
732 | /* | |
733 | * Implausible though it may be we need to protect us against | |
734 | * the following scenario: | |
735 | * | |
736 | * The thread is faster done than the hard interrupt handler | |
737 | * on the other CPU. If we unmask the irq line then the | |
738 | * interrupt can come in again and masks the line, leaves due | |
009b4c3b | 739 | * to IRQS_INPROGRESS and the irq line is masked forever. |
b5faba21 TG |
740 | * |
741 | * This also serializes the state of shared oneshot handlers | |
742 | * versus "desc->threads_onehsot |= action->thread_mask;" in | |
743 | * irq_wake_thread(). See the comment there which explains the | |
744 | * serialization. | |
0b1adaa0 | 745 | */ |
32f4125e | 746 | if (unlikely(irqd_irq_inprogress(&desc->irq_data))) { |
0b1adaa0 | 747 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 748 | chip_bus_sync_unlock(desc); |
0b1adaa0 TG |
749 | cpu_relax(); |
750 | goto again; | |
751 | } | |
752 | ||
b5faba21 TG |
753 | /* |
754 | * Now check again, whether the thread should run. Otherwise | |
755 | * we would clear the threads_oneshot bit of this thread which | |
756 | * was just set. | |
757 | */ | |
f3f79e38 | 758 | if (test_bit(IRQTF_RUNTHREAD, &action->thread_flags)) |
b5faba21 TG |
759 | goto out_unlock; |
760 | ||
761 | desc->threads_oneshot &= ~action->thread_mask; | |
762 | ||
32f4125e TG |
763 | if (!desc->threads_oneshot && !irqd_irq_disabled(&desc->irq_data) && |
764 | irqd_irq_masked(&desc->irq_data)) | |
328a4978 | 765 | unmask_threaded_irq(desc); |
32f4125e | 766 | |
b5faba21 | 767 | out_unlock: |
239007b8 | 768 | raw_spin_unlock_irq(&desc->lock); |
3876ec9e | 769 | chip_bus_sync_unlock(desc); |
b25c340c TG |
770 | } |
771 | ||
61f38261 | 772 | #ifdef CONFIG_SMP |
591d2fb0 | 773 | /* |
b04c644e | 774 | * Check whether we need to change the affinity of the interrupt thread. |
591d2fb0 TG |
775 | */ |
776 | static void | |
777 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) | |
778 | { | |
779 | cpumask_var_t mask; | |
04aa530e | 780 | bool valid = true; |
591d2fb0 TG |
781 | |
782 | if (!test_and_clear_bit(IRQTF_AFFINITY, &action->thread_flags)) | |
783 | return; | |
784 | ||
785 | /* | |
786 | * In case we are out of memory we set IRQTF_AFFINITY again and | |
787 | * try again next time | |
788 | */ | |
789 | if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { | |
790 | set_bit(IRQTF_AFFINITY, &action->thread_flags); | |
791 | return; | |
792 | } | |
793 | ||
239007b8 | 794 | raw_spin_lock_irq(&desc->lock); |
04aa530e TG |
795 | /* |
796 | * This code is triggered unconditionally. Check the affinity | |
797 | * mask pointer. For CPU_MASK_OFFSTACK=n this is optimized out. | |
798 | */ | |
799 | if (desc->irq_data.affinity) | |
800 | cpumask_copy(mask, desc->irq_data.affinity); | |
801 | else | |
802 | valid = false; | |
239007b8 | 803 | raw_spin_unlock_irq(&desc->lock); |
591d2fb0 | 804 | |
04aa530e TG |
805 | if (valid) |
806 | set_cpus_allowed_ptr(current, mask); | |
591d2fb0 TG |
807 | free_cpumask_var(mask); |
808 | } | |
61f38261 BP |
809 | #else |
810 | static inline void | |
811 | irq_thread_check_affinity(struct irq_desc *desc, struct irqaction *action) { } | |
812 | #endif | |
591d2fb0 | 813 | |
8d32a307 TG |
814 | /* |
815 | * Interrupts which are not explicitely requested as threaded | |
816 | * interrupts rely on the implicit bh/preempt disable of the hard irq | |
817 | * context. So we need to disable bh here to avoid deadlocks and other | |
818 | * side effects. | |
819 | */ | |
3a43e05f | 820 | static irqreturn_t |
8d32a307 TG |
821 | irq_forced_thread_fn(struct irq_desc *desc, struct irqaction *action) |
822 | { | |
3a43e05f SAS |
823 | irqreturn_t ret; |
824 | ||
8d32a307 | 825 | local_bh_disable(); |
3a43e05f | 826 | ret = action->thread_fn(action->irq, action->dev_id); |
f3f79e38 | 827 | irq_finalize_oneshot(desc, action); |
8d32a307 | 828 | local_bh_enable(); |
3a43e05f | 829 | return ret; |
8d32a307 TG |
830 | } |
831 | ||
832 | /* | |
f788e7bf | 833 | * Interrupts explicitly requested as threaded interrupts want to be |
8d32a307 TG |
834 | * preemtible - many of them need to sleep and wait for slow busses to |
835 | * complete. | |
836 | */ | |
3a43e05f SAS |
837 | static irqreturn_t irq_thread_fn(struct irq_desc *desc, |
838 | struct irqaction *action) | |
8d32a307 | 839 | { |
3a43e05f SAS |
840 | irqreturn_t ret; |
841 | ||
842 | ret = action->thread_fn(action->irq, action->dev_id); | |
f3f79e38 | 843 | irq_finalize_oneshot(desc, action); |
3a43e05f | 844 | return ret; |
8d32a307 TG |
845 | } |
846 | ||
7140ea19 IY |
847 | static void wake_threads_waitq(struct irq_desc *desc) |
848 | { | |
c685689f | 849 | if (atomic_dec_and_test(&desc->threads_active)) |
7140ea19 IY |
850 | wake_up(&desc->wait_for_threads); |
851 | } | |
852 | ||
67d12145 | 853 | static void irq_thread_dtor(struct callback_head *unused) |
4d1d61a6 ON |
854 | { |
855 | struct task_struct *tsk = current; | |
856 | struct irq_desc *desc; | |
857 | struct irqaction *action; | |
858 | ||
859 | if (WARN_ON_ONCE(!(current->flags & PF_EXITING))) | |
860 | return; | |
861 | ||
862 | action = kthread_data(tsk); | |
863 | ||
fb21affa | 864 | pr_err("exiting task \"%s\" (%d) is an active IRQ thread (irq %d)\n", |
19af395d | 865 | tsk->comm, tsk->pid, action->irq); |
4d1d61a6 ON |
866 | |
867 | ||
868 | desc = irq_to_desc(action->irq); | |
869 | /* | |
870 | * If IRQTF_RUNTHREAD is set, we need to decrement | |
871 | * desc->threads_active and wake possible waiters. | |
872 | */ | |
873 | if (test_and_clear_bit(IRQTF_RUNTHREAD, &action->thread_flags)) | |
874 | wake_threads_waitq(desc); | |
875 | ||
876 | /* Prevent a stale desc->threads_oneshot */ | |
877 | irq_finalize_oneshot(desc, action); | |
878 | } | |
879 | ||
3aa551c9 TG |
880 | /* |
881 | * Interrupt handler thread | |
882 | */ | |
883 | static int irq_thread(void *data) | |
884 | { | |
67d12145 | 885 | struct callback_head on_exit_work; |
3aa551c9 TG |
886 | struct irqaction *action = data; |
887 | struct irq_desc *desc = irq_to_desc(action->irq); | |
3a43e05f SAS |
888 | irqreturn_t (*handler_fn)(struct irq_desc *desc, |
889 | struct irqaction *action); | |
3aa551c9 | 890 | |
540b60e2 | 891 | if (force_irqthreads && test_bit(IRQTF_FORCED_THREAD, |
8d32a307 TG |
892 | &action->thread_flags)) |
893 | handler_fn = irq_forced_thread_fn; | |
894 | else | |
895 | handler_fn = irq_thread_fn; | |
896 | ||
41f9d29f | 897 | init_task_work(&on_exit_work, irq_thread_dtor); |
4d1d61a6 | 898 | task_work_add(current, &on_exit_work, false); |
3aa551c9 | 899 | |
f3de44ed SM |
900 | irq_thread_check_affinity(desc, action); |
901 | ||
3aa551c9 | 902 | while (!irq_wait_for_interrupt(action)) { |
7140ea19 | 903 | irqreturn_t action_ret; |
3aa551c9 | 904 | |
591d2fb0 TG |
905 | irq_thread_check_affinity(desc, action); |
906 | ||
7140ea19 | 907 | action_ret = handler_fn(desc, action); |
1e77d0a1 TG |
908 | if (action_ret == IRQ_HANDLED) |
909 | atomic_inc(&desc->threads_handled); | |
3aa551c9 | 910 | |
7140ea19 | 911 | wake_threads_waitq(desc); |
3aa551c9 TG |
912 | } |
913 | ||
7140ea19 IY |
914 | /* |
915 | * This is the regular exit path. __free_irq() is stopping the | |
916 | * thread via kthread_stop() after calling | |
917 | * synchronize_irq(). So neither IRQTF_RUNTHREAD nor the | |
e04268b0 TG |
918 | * oneshot mask bit can be set. We cannot verify that as we |
919 | * cannot touch the oneshot mask at this point anymore as | |
920 | * __setup_irq() might have given out currents thread_mask | |
921 | * again. | |
3aa551c9 | 922 | */ |
4d1d61a6 | 923 | task_work_cancel(current, irq_thread_dtor); |
3aa551c9 TG |
924 | return 0; |
925 | } | |
926 | ||
a92444c6 TG |
927 | /** |
928 | * irq_wake_thread - wake the irq thread for the action identified by dev_id | |
929 | * @irq: Interrupt line | |
930 | * @dev_id: Device identity for which the thread should be woken | |
931 | * | |
932 | */ | |
933 | void irq_wake_thread(unsigned int irq, void *dev_id) | |
934 | { | |
935 | struct irq_desc *desc = irq_to_desc(irq); | |
936 | struct irqaction *action; | |
937 | unsigned long flags; | |
938 | ||
939 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
940 | return; | |
941 | ||
942 | raw_spin_lock_irqsave(&desc->lock, flags); | |
943 | for (action = desc->action; action; action = action->next) { | |
944 | if (action->dev_id == dev_id) { | |
945 | if (action->thread) | |
946 | __irq_wake_thread(desc, action); | |
947 | break; | |
948 | } | |
949 | } | |
950 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
951 | } | |
952 | EXPORT_SYMBOL_GPL(irq_wake_thread); | |
953 | ||
8d32a307 TG |
954 | static void irq_setup_forced_threading(struct irqaction *new) |
955 | { | |
956 | if (!force_irqthreads) | |
957 | return; | |
958 | if (new->flags & (IRQF_NO_THREAD | IRQF_PERCPU | IRQF_ONESHOT)) | |
959 | return; | |
960 | ||
961 | new->flags |= IRQF_ONESHOT; | |
962 | ||
963 | if (!new->thread_fn) { | |
964 | set_bit(IRQTF_FORCED_THREAD, &new->thread_flags); | |
965 | new->thread_fn = new->handler; | |
966 | new->handler = irq_default_primary_handler; | |
967 | } | |
968 | } | |
969 | ||
c1bacbae TG |
970 | static int irq_request_resources(struct irq_desc *desc) |
971 | { | |
972 | struct irq_data *d = &desc->irq_data; | |
973 | struct irq_chip *c = d->chip; | |
974 | ||
975 | return c->irq_request_resources ? c->irq_request_resources(d) : 0; | |
976 | } | |
977 | ||
978 | static void irq_release_resources(struct irq_desc *desc) | |
979 | { | |
980 | struct irq_data *d = &desc->irq_data; | |
981 | struct irq_chip *c = d->chip; | |
982 | ||
983 | if (c->irq_release_resources) | |
984 | c->irq_release_resources(d); | |
985 | } | |
986 | ||
1da177e4 LT |
987 | /* |
988 | * Internal function to register an irqaction - typically used to | |
989 | * allocate special interrupts that are part of the architecture. | |
990 | */ | |
d3c60047 | 991 | static int |
327ec569 | 992 | __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new) |
1da177e4 | 993 | { |
f17c7545 | 994 | struct irqaction *old, **old_ptr; |
b5faba21 | 995 | unsigned long flags, thread_mask = 0; |
3b8249e7 TG |
996 | int ret, nested, shared = 0; |
997 | cpumask_var_t mask; | |
1da177e4 | 998 | |
7d94f7ca | 999 | if (!desc) |
c2b5a251 MW |
1000 | return -EINVAL; |
1001 | ||
6b8ff312 | 1002 | if (desc->irq_data.chip == &no_irq_chip) |
1da177e4 | 1003 | return -ENOSYS; |
b6873807 SAS |
1004 | if (!try_module_get(desc->owner)) |
1005 | return -ENODEV; | |
1da177e4 | 1006 | |
3aa551c9 | 1007 | /* |
399b5da2 TG |
1008 | * Check whether the interrupt nests into another interrupt |
1009 | * thread. | |
1010 | */ | |
1ccb4e61 | 1011 | nested = irq_settings_is_nested_thread(desc); |
399b5da2 | 1012 | if (nested) { |
b6873807 SAS |
1013 | if (!new->thread_fn) { |
1014 | ret = -EINVAL; | |
1015 | goto out_mput; | |
1016 | } | |
399b5da2 TG |
1017 | /* |
1018 | * Replace the primary handler which was provided from | |
1019 | * the driver for non nested interrupt handling by the | |
1020 | * dummy function which warns when called. | |
1021 | */ | |
1022 | new->handler = irq_nested_primary_handler; | |
8d32a307 | 1023 | } else { |
7f1b1244 PM |
1024 | if (irq_settings_can_thread(desc)) |
1025 | irq_setup_forced_threading(new); | |
399b5da2 TG |
1026 | } |
1027 | ||
3aa551c9 | 1028 | /* |
399b5da2 TG |
1029 | * Create a handler thread when a thread function is supplied |
1030 | * and the interrupt does not nest into another interrupt | |
1031 | * thread. | |
3aa551c9 | 1032 | */ |
399b5da2 | 1033 | if (new->thread_fn && !nested) { |
3aa551c9 | 1034 | struct task_struct *t; |
ee238713 IS |
1035 | static const struct sched_param param = { |
1036 | .sched_priority = MAX_USER_RT_PRIO/2, | |
1037 | }; | |
3aa551c9 TG |
1038 | |
1039 | t = kthread_create(irq_thread, new, "irq/%d-%s", irq, | |
1040 | new->name); | |
b6873807 SAS |
1041 | if (IS_ERR(t)) { |
1042 | ret = PTR_ERR(t); | |
1043 | goto out_mput; | |
1044 | } | |
ee238713 | 1045 | |
bbfe65c2 | 1046 | sched_setscheduler_nocheck(t, SCHED_FIFO, ¶m); |
ee238713 | 1047 | |
3aa551c9 TG |
1048 | /* |
1049 | * We keep the reference to the task struct even if | |
1050 | * the thread dies to avoid that the interrupt code | |
1051 | * references an already freed task_struct. | |
1052 | */ | |
1053 | get_task_struct(t); | |
1054 | new->thread = t; | |
04aa530e TG |
1055 | /* |
1056 | * Tell the thread to set its affinity. This is | |
1057 | * important for shared interrupt handlers as we do | |
1058 | * not invoke setup_affinity() for the secondary | |
1059 | * handlers as everything is already set up. Even for | |
1060 | * interrupts marked with IRQF_NO_BALANCE this is | |
1061 | * correct as we want the thread to move to the cpu(s) | |
1062 | * on which the requesting code placed the interrupt. | |
1063 | */ | |
1064 | set_bit(IRQTF_AFFINITY, &new->thread_flags); | |
3aa551c9 TG |
1065 | } |
1066 | ||
3b8249e7 TG |
1067 | if (!alloc_cpumask_var(&mask, GFP_KERNEL)) { |
1068 | ret = -ENOMEM; | |
1069 | goto out_thread; | |
1070 | } | |
1071 | ||
dc9b229a TG |
1072 | /* |
1073 | * Drivers are often written to work w/o knowledge about the | |
1074 | * underlying irq chip implementation, so a request for a | |
1075 | * threaded irq without a primary hard irq context handler | |
1076 | * requires the ONESHOT flag to be set. Some irq chips like | |
1077 | * MSI based interrupts are per se one shot safe. Check the | |
1078 | * chip flags, so we can avoid the unmask dance at the end of | |
1079 | * the threaded handler for those. | |
1080 | */ | |
1081 | if (desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE) | |
1082 | new->flags &= ~IRQF_ONESHOT; | |
1083 | ||
1da177e4 LT |
1084 | /* |
1085 | * The following block of code has to be executed atomically | |
1086 | */ | |
239007b8 | 1087 | raw_spin_lock_irqsave(&desc->lock, flags); |
f17c7545 IM |
1088 | old_ptr = &desc->action; |
1089 | old = *old_ptr; | |
06fcb0c6 | 1090 | if (old) { |
e76de9f8 TG |
1091 | /* |
1092 | * Can't share interrupts unless both agree to and are | |
1093 | * the same type (level, edge, polarity). So both flag | |
3cca53b0 | 1094 | * fields must have IRQF_SHARED set and the bits which |
9d591edd TG |
1095 | * set the trigger type must match. Also all must |
1096 | * agree on ONESHOT. | |
e76de9f8 | 1097 | */ |
3cca53b0 | 1098 | if (!((old->flags & new->flags) & IRQF_SHARED) || |
9d591edd | 1099 | ((old->flags ^ new->flags) & IRQF_TRIGGER_MASK) || |
f5d89470 | 1100 | ((old->flags ^ new->flags) & IRQF_ONESHOT)) |
f5163427 DS |
1101 | goto mismatch; |
1102 | ||
f5163427 | 1103 | /* All handlers must agree on per-cpuness */ |
3cca53b0 TG |
1104 | if ((old->flags & IRQF_PERCPU) != |
1105 | (new->flags & IRQF_PERCPU)) | |
f5163427 | 1106 | goto mismatch; |
1da177e4 LT |
1107 | |
1108 | /* add new interrupt at end of irq queue */ | |
1109 | do { | |
52abb700 TG |
1110 | /* |
1111 | * Or all existing action->thread_mask bits, | |
1112 | * so we can find the next zero bit for this | |
1113 | * new action. | |
1114 | */ | |
b5faba21 | 1115 | thread_mask |= old->thread_mask; |
f17c7545 IM |
1116 | old_ptr = &old->next; |
1117 | old = *old_ptr; | |
1da177e4 LT |
1118 | } while (old); |
1119 | shared = 1; | |
1120 | } | |
1121 | ||
b5faba21 | 1122 | /* |
52abb700 TG |
1123 | * Setup the thread mask for this irqaction for ONESHOT. For |
1124 | * !ONESHOT irqs the thread mask is 0 so we can avoid a | |
1125 | * conditional in irq_wake_thread(). | |
b5faba21 | 1126 | */ |
52abb700 TG |
1127 | if (new->flags & IRQF_ONESHOT) { |
1128 | /* | |
1129 | * Unlikely to have 32 resp 64 irqs sharing one line, | |
1130 | * but who knows. | |
1131 | */ | |
1132 | if (thread_mask == ~0UL) { | |
1133 | ret = -EBUSY; | |
1134 | goto out_mask; | |
1135 | } | |
1136 | /* | |
1137 | * The thread_mask for the action is or'ed to | |
1138 | * desc->thread_active to indicate that the | |
1139 | * IRQF_ONESHOT thread handler has been woken, but not | |
1140 | * yet finished. The bit is cleared when a thread | |
1141 | * completes. When all threads of a shared interrupt | |
1142 | * line have completed desc->threads_active becomes | |
1143 | * zero and the interrupt line is unmasked. See | |
1144 | * handle.c:irq_wake_thread() for further information. | |
1145 | * | |
1146 | * If no thread is woken by primary (hard irq context) | |
1147 | * interrupt handlers, then desc->threads_active is | |
1148 | * also checked for zero to unmask the irq line in the | |
1149 | * affected hard irq flow handlers | |
1150 | * (handle_[fasteoi|level]_irq). | |
1151 | * | |
1152 | * The new action gets the first zero bit of | |
1153 | * thread_mask assigned. See the loop above which or's | |
1154 | * all existing action->thread_mask bits. | |
1155 | */ | |
1156 | new->thread_mask = 1 << ffz(thread_mask); | |
1c6c6952 | 1157 | |
dc9b229a TG |
1158 | } else if (new->handler == irq_default_primary_handler && |
1159 | !(desc->irq_data.chip->flags & IRQCHIP_ONESHOT_SAFE)) { | |
1c6c6952 TG |
1160 | /* |
1161 | * The interrupt was requested with handler = NULL, so | |
1162 | * we use the default primary handler for it. But it | |
1163 | * does not have the oneshot flag set. In combination | |
1164 | * with level interrupts this is deadly, because the | |
1165 | * default primary handler just wakes the thread, then | |
1166 | * the irq lines is reenabled, but the device still | |
1167 | * has the level irq asserted. Rinse and repeat.... | |
1168 | * | |
1169 | * While this works for edge type interrupts, we play | |
1170 | * it safe and reject unconditionally because we can't | |
1171 | * say for sure which type this interrupt really | |
1172 | * has. The type flags are unreliable as the | |
1173 | * underlying chip implementation can override them. | |
1174 | */ | |
97fd75b7 | 1175 | pr_err("Threaded irq requested with handler=NULL and !ONESHOT for irq %d\n", |
1c6c6952 TG |
1176 | irq); |
1177 | ret = -EINVAL; | |
1178 | goto out_mask; | |
b5faba21 | 1179 | } |
b5faba21 | 1180 | |
1da177e4 | 1181 | if (!shared) { |
c1bacbae TG |
1182 | ret = irq_request_resources(desc); |
1183 | if (ret) { | |
1184 | pr_err("Failed to request resources for %s (irq %d) on irqchip %s\n", | |
1185 | new->name, irq, desc->irq_data.chip->name); | |
1186 | goto out_mask; | |
1187 | } | |
1188 | ||
3aa551c9 TG |
1189 | init_waitqueue_head(&desc->wait_for_threads); |
1190 | ||
e76de9f8 | 1191 | /* Setup the type (level, edge polarity) if configured: */ |
3cca53b0 | 1192 | if (new->flags & IRQF_TRIGGER_MASK) { |
f2b662da DB |
1193 | ret = __irq_set_trigger(desc, irq, |
1194 | new->flags & IRQF_TRIGGER_MASK); | |
82736f4d | 1195 | |
3aa551c9 | 1196 | if (ret) |
3b8249e7 | 1197 | goto out_mask; |
091738a2 | 1198 | } |
6a6de9ef | 1199 | |
009b4c3b | 1200 | desc->istate &= ~(IRQS_AUTODETECT | IRQS_SPURIOUS_DISABLED | \ |
32f4125e TG |
1201 | IRQS_ONESHOT | IRQS_WAITING); |
1202 | irqd_clear(&desc->irq_data, IRQD_IRQ_INPROGRESS); | |
94d39e1f | 1203 | |
a005677b TG |
1204 | if (new->flags & IRQF_PERCPU) { |
1205 | irqd_set(&desc->irq_data, IRQD_PER_CPU); | |
1206 | irq_settings_set_per_cpu(desc); | |
1207 | } | |
6a58fb3b | 1208 | |
b25c340c | 1209 | if (new->flags & IRQF_ONESHOT) |
3d67baec | 1210 | desc->istate |= IRQS_ONESHOT; |
b25c340c | 1211 | |
1ccb4e61 | 1212 | if (irq_settings_can_autoenable(desc)) |
b4bc724e | 1213 | irq_startup(desc, true); |
46999238 | 1214 | else |
e76de9f8 TG |
1215 | /* Undo nested disables: */ |
1216 | desc->depth = 1; | |
18404756 | 1217 | |
612e3684 | 1218 | /* Exclude IRQ from balancing if requested */ |
a005677b TG |
1219 | if (new->flags & IRQF_NOBALANCING) { |
1220 | irq_settings_set_no_balancing(desc); | |
1221 | irqd_set(&desc->irq_data, IRQD_NO_BALANCING); | |
1222 | } | |
612e3684 | 1223 | |
18404756 | 1224 | /* Set default affinity mask once everything is setup */ |
3b8249e7 | 1225 | setup_affinity(irq, desc, mask); |
0c5d1eb7 | 1226 | |
876dbd4c TG |
1227 | } else if (new->flags & IRQF_TRIGGER_MASK) { |
1228 | unsigned int nmsk = new->flags & IRQF_TRIGGER_MASK; | |
1229 | unsigned int omsk = irq_settings_get_trigger_mask(desc); | |
1230 | ||
1231 | if (nmsk != omsk) | |
1232 | /* hope the handler works with current trigger mode */ | |
97fd75b7 | 1233 | pr_warning("irq %d uses trigger mode %u; requested %u\n", |
876dbd4c | 1234 | irq, nmsk, omsk); |
1da177e4 | 1235 | } |
82736f4d | 1236 | |
69ab8494 | 1237 | new->irq = irq; |
f17c7545 | 1238 | *old_ptr = new; |
82736f4d | 1239 | |
cab303be TG |
1240 | irq_pm_install_action(desc, new); |
1241 | ||
8528b0f1 LT |
1242 | /* Reset broken irq detection when installing new handler */ |
1243 | desc->irq_count = 0; | |
1244 | desc->irqs_unhandled = 0; | |
1adb0850 TG |
1245 | |
1246 | /* | |
1247 | * Check whether we disabled the irq via the spurious handler | |
1248 | * before. Reenable it and give it another chance. | |
1249 | */ | |
7acdd53e TG |
1250 | if (shared && (desc->istate & IRQS_SPURIOUS_DISABLED)) { |
1251 | desc->istate &= ~IRQS_SPURIOUS_DISABLED; | |
8df2e02c | 1252 | __enable_irq(desc, irq); |
1adb0850 TG |
1253 | } |
1254 | ||
239007b8 | 1255 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 | 1256 | |
69ab8494 TG |
1257 | /* |
1258 | * Strictly no need to wake it up, but hung_task complains | |
1259 | * when no hard interrupt wakes the thread up. | |
1260 | */ | |
1261 | if (new->thread) | |
1262 | wake_up_process(new->thread); | |
1263 | ||
2c6927a3 | 1264 | register_irq_proc(irq, desc); |
1da177e4 LT |
1265 | new->dir = NULL; |
1266 | register_handler_proc(irq, new); | |
4f5058c3 | 1267 | free_cpumask_var(mask); |
1da177e4 LT |
1268 | |
1269 | return 0; | |
f5163427 DS |
1270 | |
1271 | mismatch: | |
3cca53b0 | 1272 | if (!(new->flags & IRQF_PROBE_SHARED)) { |
97fd75b7 | 1273 | pr_err("Flags mismatch irq %d. %08x (%s) vs. %08x (%s)\n", |
f5d89470 TG |
1274 | irq, new->flags, new->name, old->flags, old->name); |
1275 | #ifdef CONFIG_DEBUG_SHIRQ | |
13e87ec6 | 1276 | dump_stack(); |
3f050447 | 1277 | #endif |
f5d89470 | 1278 | } |
3aa551c9 TG |
1279 | ret = -EBUSY; |
1280 | ||
3b8249e7 | 1281 | out_mask: |
1c389795 | 1282 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
3b8249e7 TG |
1283 | free_cpumask_var(mask); |
1284 | ||
3aa551c9 | 1285 | out_thread: |
3aa551c9 TG |
1286 | if (new->thread) { |
1287 | struct task_struct *t = new->thread; | |
1288 | ||
1289 | new->thread = NULL; | |
05d74efa | 1290 | kthread_stop(t); |
3aa551c9 TG |
1291 | put_task_struct(t); |
1292 | } | |
b6873807 SAS |
1293 | out_mput: |
1294 | module_put(desc->owner); | |
3aa551c9 | 1295 | return ret; |
1da177e4 LT |
1296 | } |
1297 | ||
d3c60047 TG |
1298 | /** |
1299 | * setup_irq - setup an interrupt | |
1300 | * @irq: Interrupt line to setup | |
1301 | * @act: irqaction for the interrupt | |
1302 | * | |
1303 | * Used to statically setup interrupts in the early boot process. | |
1304 | */ | |
1305 | int setup_irq(unsigned int irq, struct irqaction *act) | |
1306 | { | |
986c011d | 1307 | int retval; |
d3c60047 TG |
1308 | struct irq_desc *desc = irq_to_desc(irq); |
1309 | ||
31d9d9b6 MZ |
1310 | if (WARN_ON(irq_settings_is_per_cpu_devid(desc))) |
1311 | return -EINVAL; | |
986c011d DD |
1312 | chip_bus_lock(desc); |
1313 | retval = __setup_irq(irq, desc, act); | |
1314 | chip_bus_sync_unlock(desc); | |
1315 | ||
1316 | return retval; | |
d3c60047 | 1317 | } |
eb53b4e8 | 1318 | EXPORT_SYMBOL_GPL(setup_irq); |
d3c60047 | 1319 | |
31d9d9b6 | 1320 | /* |
cbf94f06 MD |
1321 | * Internal function to unregister an irqaction - used to free |
1322 | * regular and special interrupts that are part of the architecture. | |
1da177e4 | 1323 | */ |
cbf94f06 | 1324 | static struct irqaction *__free_irq(unsigned int irq, void *dev_id) |
1da177e4 | 1325 | { |
d3c60047 | 1326 | struct irq_desc *desc = irq_to_desc(irq); |
f17c7545 | 1327 | struct irqaction *action, **action_ptr; |
1da177e4 LT |
1328 | unsigned long flags; |
1329 | ||
ae88a23b | 1330 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); |
7d94f7ca | 1331 | |
7d94f7ca | 1332 | if (!desc) |
f21cfb25 | 1333 | return NULL; |
1da177e4 | 1334 | |
239007b8 | 1335 | raw_spin_lock_irqsave(&desc->lock, flags); |
ae88a23b IM |
1336 | |
1337 | /* | |
1338 | * There can be multiple actions per IRQ descriptor, find the right | |
1339 | * one based on the dev_id: | |
1340 | */ | |
f17c7545 | 1341 | action_ptr = &desc->action; |
1da177e4 | 1342 | for (;;) { |
f17c7545 | 1343 | action = *action_ptr; |
1da177e4 | 1344 | |
ae88a23b IM |
1345 | if (!action) { |
1346 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
239007b8 | 1347 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
1da177e4 | 1348 | |
f21cfb25 | 1349 | return NULL; |
ae88a23b | 1350 | } |
1da177e4 | 1351 | |
8316e381 IM |
1352 | if (action->dev_id == dev_id) |
1353 | break; | |
f17c7545 | 1354 | action_ptr = &action->next; |
ae88a23b | 1355 | } |
dbce706e | 1356 | |
ae88a23b | 1357 | /* Found it - now remove it from the list of entries: */ |
f17c7545 | 1358 | *action_ptr = action->next; |
ae88a23b | 1359 | |
cab303be TG |
1360 | irq_pm_remove_action(desc, action); |
1361 | ||
ae88a23b | 1362 | /* If this was the last handler, shut down the IRQ line: */ |
c1bacbae | 1363 | if (!desc->action) { |
46999238 | 1364 | irq_shutdown(desc); |
c1bacbae TG |
1365 | irq_release_resources(desc); |
1366 | } | |
3aa551c9 | 1367 | |
e7a297b0 PWJ |
1368 | #ifdef CONFIG_SMP |
1369 | /* make sure affinity_hint is cleaned up */ | |
1370 | if (WARN_ON_ONCE(desc->affinity_hint)) | |
1371 | desc->affinity_hint = NULL; | |
1372 | #endif | |
1373 | ||
239007b8 | 1374 | raw_spin_unlock_irqrestore(&desc->lock, flags); |
ae88a23b IM |
1375 | |
1376 | unregister_handler_proc(irq, action); | |
1377 | ||
1378 | /* Make sure it's not being used on another CPU: */ | |
1379 | synchronize_irq(irq); | |
1da177e4 | 1380 | |
70edcd77 | 1381 | #ifdef CONFIG_DEBUG_SHIRQ |
ae88a23b IM |
1382 | /* |
1383 | * It's a shared IRQ -- the driver ought to be prepared for an IRQ | |
1384 | * event to happen even now it's being freed, so let's make sure that | |
1385 | * is so by doing an extra call to the handler .... | |
1386 | * | |
1387 | * ( We do this after actually deregistering it, to make sure that a | |
1388 | * 'real' IRQ doesn't run in * parallel with our fake. ) | |
1389 | */ | |
1390 | if (action->flags & IRQF_SHARED) { | |
1391 | local_irq_save(flags); | |
1392 | action->handler(irq, dev_id); | |
1393 | local_irq_restore(flags); | |
1da177e4 | 1394 | } |
ae88a23b | 1395 | #endif |
2d860ad7 LT |
1396 | |
1397 | if (action->thread) { | |
05d74efa | 1398 | kthread_stop(action->thread); |
2d860ad7 LT |
1399 | put_task_struct(action->thread); |
1400 | } | |
1401 | ||
b6873807 | 1402 | module_put(desc->owner); |
f21cfb25 MD |
1403 | return action; |
1404 | } | |
1405 | ||
cbf94f06 MD |
1406 | /** |
1407 | * remove_irq - free an interrupt | |
1408 | * @irq: Interrupt line to free | |
1409 | * @act: irqaction for the interrupt | |
1410 | * | |
1411 | * Used to remove interrupts statically setup by the early boot process. | |
1412 | */ | |
1413 | void remove_irq(unsigned int irq, struct irqaction *act) | |
1414 | { | |
31d9d9b6 MZ |
1415 | struct irq_desc *desc = irq_to_desc(irq); |
1416 | ||
1417 | if (desc && !WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
1418 | __free_irq(irq, act->dev_id); | |
cbf94f06 | 1419 | } |
eb53b4e8 | 1420 | EXPORT_SYMBOL_GPL(remove_irq); |
cbf94f06 | 1421 | |
f21cfb25 MD |
1422 | /** |
1423 | * free_irq - free an interrupt allocated with request_irq | |
1424 | * @irq: Interrupt line to free | |
1425 | * @dev_id: Device identity to free | |
1426 | * | |
1427 | * Remove an interrupt handler. The handler is removed and if the | |
1428 | * interrupt line is no longer in use by any driver it is disabled. | |
1429 | * On a shared IRQ the caller must ensure the interrupt is disabled | |
1430 | * on the card it drives before calling this function. The function | |
1431 | * does not return until any executing interrupts for this IRQ | |
1432 | * have completed. | |
1433 | * | |
1434 | * This function must not be called from interrupt context. | |
1435 | */ | |
1436 | void free_irq(unsigned int irq, void *dev_id) | |
1437 | { | |
70aedd24 TG |
1438 | struct irq_desc *desc = irq_to_desc(irq); |
1439 | ||
31d9d9b6 | 1440 | if (!desc || WARN_ON(irq_settings_is_per_cpu_devid(desc))) |
70aedd24 TG |
1441 | return; |
1442 | ||
cd7eab44 BH |
1443 | #ifdef CONFIG_SMP |
1444 | if (WARN_ON(desc->affinity_notify)) | |
1445 | desc->affinity_notify = NULL; | |
1446 | #endif | |
1447 | ||
3876ec9e | 1448 | chip_bus_lock(desc); |
cbf94f06 | 1449 | kfree(__free_irq(irq, dev_id)); |
3876ec9e | 1450 | chip_bus_sync_unlock(desc); |
1da177e4 | 1451 | } |
1da177e4 LT |
1452 | EXPORT_SYMBOL(free_irq); |
1453 | ||
1454 | /** | |
3aa551c9 | 1455 | * request_threaded_irq - allocate an interrupt line |
1da177e4 | 1456 | * @irq: Interrupt line to allocate |
3aa551c9 TG |
1457 | * @handler: Function to be called when the IRQ occurs. |
1458 | * Primary handler for threaded interrupts | |
b25c340c TG |
1459 | * If NULL and thread_fn != NULL the default |
1460 | * primary handler is installed | |
f48fe81e TG |
1461 | * @thread_fn: Function called from the irq handler thread |
1462 | * If NULL, no irq thread is created | |
1da177e4 LT |
1463 | * @irqflags: Interrupt type flags |
1464 | * @devname: An ascii name for the claiming device | |
1465 | * @dev_id: A cookie passed back to the handler function | |
1466 | * | |
1467 | * This call allocates interrupt resources and enables the | |
1468 | * interrupt line and IRQ handling. From the point this | |
1469 | * call is made your handler function may be invoked. Since | |
1470 | * your handler function must clear any interrupt the board | |
1471 | * raises, you must take care both to initialise your hardware | |
1472 | * and to set up the interrupt handler in the right order. | |
1473 | * | |
3aa551c9 | 1474 | * If you want to set up a threaded irq handler for your device |
6d21af4f | 1475 | * then you need to supply @handler and @thread_fn. @handler is |
3aa551c9 TG |
1476 | * still called in hard interrupt context and has to check |
1477 | * whether the interrupt originates from the device. If yes it | |
1478 | * needs to disable the interrupt on the device and return | |
39a2eddb | 1479 | * IRQ_WAKE_THREAD which will wake up the handler thread and run |
3aa551c9 TG |
1480 | * @thread_fn. This split handler design is necessary to support |
1481 | * shared interrupts. | |
1482 | * | |
1da177e4 LT |
1483 | * Dev_id must be globally unique. Normally the address of the |
1484 | * device data structure is used as the cookie. Since the handler | |
1485 | * receives this value it makes sense to use it. | |
1486 | * | |
1487 | * If your interrupt is shared you must pass a non NULL dev_id | |
1488 | * as this is required when freeing the interrupt. | |
1489 | * | |
1490 | * Flags: | |
1491 | * | |
3cca53b0 | 1492 | * IRQF_SHARED Interrupt is shared |
0c5d1eb7 | 1493 | * IRQF_TRIGGER_* Specify active edge(s) or level |
1da177e4 LT |
1494 | * |
1495 | */ | |
3aa551c9 TG |
1496 | int request_threaded_irq(unsigned int irq, irq_handler_t handler, |
1497 | irq_handler_t thread_fn, unsigned long irqflags, | |
1498 | const char *devname, void *dev_id) | |
1da177e4 | 1499 | { |
06fcb0c6 | 1500 | struct irqaction *action; |
08678b08 | 1501 | struct irq_desc *desc; |
d3c60047 | 1502 | int retval; |
1da177e4 LT |
1503 | |
1504 | /* | |
1505 | * Sanity-check: shared interrupts must pass in a real dev-ID, | |
1506 | * otherwise we'll have trouble later trying to figure out | |
1507 | * which interrupt is which (messes up the interrupt freeing | |
1508 | * logic etc). | |
17f48034 RW |
1509 | * |
1510 | * Also IRQF_COND_SUSPEND only makes sense for shared interrupts and | |
1511 | * it cannot be set along with IRQF_NO_SUSPEND. | |
1da177e4 | 1512 | */ |
17f48034 RW |
1513 | if (((irqflags & IRQF_SHARED) && !dev_id) || |
1514 | (!(irqflags & IRQF_SHARED) && (irqflags & IRQF_COND_SUSPEND)) || | |
1515 | ((irqflags & IRQF_NO_SUSPEND) && (irqflags & IRQF_COND_SUSPEND))) | |
1da177e4 | 1516 | return -EINVAL; |
7d94f7ca | 1517 | |
cb5bc832 | 1518 | desc = irq_to_desc(irq); |
7d94f7ca | 1519 | if (!desc) |
1da177e4 | 1520 | return -EINVAL; |
7d94f7ca | 1521 | |
31d9d9b6 MZ |
1522 | if (!irq_settings_can_request(desc) || |
1523 | WARN_ON(irq_settings_is_per_cpu_devid(desc))) | |
6550c775 | 1524 | return -EINVAL; |
b25c340c TG |
1525 | |
1526 | if (!handler) { | |
1527 | if (!thread_fn) | |
1528 | return -EINVAL; | |
1529 | handler = irq_default_primary_handler; | |
1530 | } | |
1da177e4 | 1531 | |
45535732 | 1532 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); |
1da177e4 LT |
1533 | if (!action) |
1534 | return -ENOMEM; | |
1535 | ||
1536 | action->handler = handler; | |
3aa551c9 | 1537 | action->thread_fn = thread_fn; |
1da177e4 | 1538 | action->flags = irqflags; |
1da177e4 | 1539 | action->name = devname; |
1da177e4 LT |
1540 | action->dev_id = dev_id; |
1541 | ||
3876ec9e | 1542 | chip_bus_lock(desc); |
d3c60047 | 1543 | retval = __setup_irq(irq, desc, action); |
3876ec9e | 1544 | chip_bus_sync_unlock(desc); |
70aedd24 | 1545 | |
377bf1e4 AV |
1546 | if (retval) |
1547 | kfree(action); | |
1548 | ||
6d83f94d | 1549 | #ifdef CONFIG_DEBUG_SHIRQ_FIXME |
6ce51c43 | 1550 | if (!retval && (irqflags & IRQF_SHARED)) { |
a304e1b8 DW |
1551 | /* |
1552 | * It's a shared IRQ -- the driver ought to be prepared for it | |
1553 | * to happen immediately, so let's make sure.... | |
377bf1e4 AV |
1554 | * We disable the irq to make sure that a 'real' IRQ doesn't |
1555 | * run in parallel with our fake. | |
a304e1b8 | 1556 | */ |
59845b1f | 1557 | unsigned long flags; |
a304e1b8 | 1558 | |
377bf1e4 | 1559 | disable_irq(irq); |
59845b1f | 1560 | local_irq_save(flags); |
377bf1e4 | 1561 | |
59845b1f | 1562 | handler(irq, dev_id); |
377bf1e4 | 1563 | |
59845b1f | 1564 | local_irq_restore(flags); |
377bf1e4 | 1565 | enable_irq(irq); |
a304e1b8 DW |
1566 | } |
1567 | #endif | |
1da177e4 LT |
1568 | return retval; |
1569 | } | |
3aa551c9 | 1570 | EXPORT_SYMBOL(request_threaded_irq); |
ae731f8d MZ |
1571 | |
1572 | /** | |
1573 | * request_any_context_irq - allocate an interrupt line | |
1574 | * @irq: Interrupt line to allocate | |
1575 | * @handler: Function to be called when the IRQ occurs. | |
1576 | * Threaded handler for threaded interrupts. | |
1577 | * @flags: Interrupt type flags | |
1578 | * @name: An ascii name for the claiming device | |
1579 | * @dev_id: A cookie passed back to the handler function | |
1580 | * | |
1581 | * This call allocates interrupt resources and enables the | |
1582 | * interrupt line and IRQ handling. It selects either a | |
1583 | * hardirq or threaded handling method depending on the | |
1584 | * context. | |
1585 | * | |
1586 | * On failure, it returns a negative value. On success, | |
1587 | * it returns either IRQC_IS_HARDIRQ or IRQC_IS_NESTED. | |
1588 | */ | |
1589 | int request_any_context_irq(unsigned int irq, irq_handler_t handler, | |
1590 | unsigned long flags, const char *name, void *dev_id) | |
1591 | { | |
1592 | struct irq_desc *desc = irq_to_desc(irq); | |
1593 | int ret; | |
1594 | ||
1595 | if (!desc) | |
1596 | return -EINVAL; | |
1597 | ||
1ccb4e61 | 1598 | if (irq_settings_is_nested_thread(desc)) { |
ae731f8d MZ |
1599 | ret = request_threaded_irq(irq, NULL, handler, |
1600 | flags, name, dev_id); | |
1601 | return !ret ? IRQC_IS_NESTED : ret; | |
1602 | } | |
1603 | ||
1604 | ret = request_irq(irq, handler, flags, name, dev_id); | |
1605 | return !ret ? IRQC_IS_HARDIRQ : ret; | |
1606 | } | |
1607 | EXPORT_SYMBOL_GPL(request_any_context_irq); | |
31d9d9b6 | 1608 | |
1e7c5fd2 | 1609 | void enable_percpu_irq(unsigned int irq, unsigned int type) |
31d9d9b6 MZ |
1610 | { |
1611 | unsigned int cpu = smp_processor_id(); | |
1612 | unsigned long flags; | |
1613 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
1614 | ||
1615 | if (!desc) | |
1616 | return; | |
1617 | ||
1e7c5fd2 MZ |
1618 | type &= IRQ_TYPE_SENSE_MASK; |
1619 | if (type != IRQ_TYPE_NONE) { | |
1620 | int ret; | |
1621 | ||
1622 | ret = __irq_set_trigger(desc, irq, type); | |
1623 | ||
1624 | if (ret) { | |
32cffdde | 1625 | WARN(1, "failed to set type for IRQ%d\n", irq); |
1e7c5fd2 MZ |
1626 | goto out; |
1627 | } | |
1628 | } | |
1629 | ||
31d9d9b6 | 1630 | irq_percpu_enable(desc, cpu); |
1e7c5fd2 | 1631 | out: |
31d9d9b6 MZ |
1632 | irq_put_desc_unlock(desc, flags); |
1633 | } | |
36a5df85 | 1634 | EXPORT_SYMBOL_GPL(enable_percpu_irq); |
31d9d9b6 MZ |
1635 | |
1636 | void disable_percpu_irq(unsigned int irq) | |
1637 | { | |
1638 | unsigned int cpu = smp_processor_id(); | |
1639 | unsigned long flags; | |
1640 | struct irq_desc *desc = irq_get_desc_lock(irq, &flags, IRQ_GET_DESC_CHECK_PERCPU); | |
1641 | ||
1642 | if (!desc) | |
1643 | return; | |
1644 | ||
1645 | irq_percpu_disable(desc, cpu); | |
1646 | irq_put_desc_unlock(desc, flags); | |
1647 | } | |
36a5df85 | 1648 | EXPORT_SYMBOL_GPL(disable_percpu_irq); |
31d9d9b6 MZ |
1649 | |
1650 | /* | |
1651 | * Internal function to unregister a percpu irqaction. | |
1652 | */ | |
1653 | static struct irqaction *__free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
1654 | { | |
1655 | struct irq_desc *desc = irq_to_desc(irq); | |
1656 | struct irqaction *action; | |
1657 | unsigned long flags; | |
1658 | ||
1659 | WARN(in_interrupt(), "Trying to free IRQ %d from IRQ context!\n", irq); | |
1660 | ||
1661 | if (!desc) | |
1662 | return NULL; | |
1663 | ||
1664 | raw_spin_lock_irqsave(&desc->lock, flags); | |
1665 | ||
1666 | action = desc->action; | |
1667 | if (!action || action->percpu_dev_id != dev_id) { | |
1668 | WARN(1, "Trying to free already-free IRQ %d\n", irq); | |
1669 | goto bad; | |
1670 | } | |
1671 | ||
1672 | if (!cpumask_empty(desc->percpu_enabled)) { | |
1673 | WARN(1, "percpu IRQ %d still enabled on CPU%d!\n", | |
1674 | irq, cpumask_first(desc->percpu_enabled)); | |
1675 | goto bad; | |
1676 | } | |
1677 | ||
1678 | /* Found it - now remove it from the list of entries: */ | |
1679 | desc->action = NULL; | |
1680 | ||
1681 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1682 | ||
1683 | unregister_handler_proc(irq, action); | |
1684 | ||
1685 | module_put(desc->owner); | |
1686 | return action; | |
1687 | ||
1688 | bad: | |
1689 | raw_spin_unlock_irqrestore(&desc->lock, flags); | |
1690 | return NULL; | |
1691 | } | |
1692 | ||
1693 | /** | |
1694 | * remove_percpu_irq - free a per-cpu interrupt | |
1695 | * @irq: Interrupt line to free | |
1696 | * @act: irqaction for the interrupt | |
1697 | * | |
1698 | * Used to remove interrupts statically setup by the early boot process. | |
1699 | */ | |
1700 | void remove_percpu_irq(unsigned int irq, struct irqaction *act) | |
1701 | { | |
1702 | struct irq_desc *desc = irq_to_desc(irq); | |
1703 | ||
1704 | if (desc && irq_settings_is_per_cpu_devid(desc)) | |
1705 | __free_percpu_irq(irq, act->percpu_dev_id); | |
1706 | } | |
1707 | ||
1708 | /** | |
1709 | * free_percpu_irq - free an interrupt allocated with request_percpu_irq | |
1710 | * @irq: Interrupt line to free | |
1711 | * @dev_id: Device identity to free | |
1712 | * | |
1713 | * Remove a percpu interrupt handler. The handler is removed, but | |
1714 | * the interrupt line is not disabled. This must be done on each | |
1715 | * CPU before calling this function. The function does not return | |
1716 | * until any executing interrupts for this IRQ have completed. | |
1717 | * | |
1718 | * This function must not be called from interrupt context. | |
1719 | */ | |
1720 | void free_percpu_irq(unsigned int irq, void __percpu *dev_id) | |
1721 | { | |
1722 | struct irq_desc *desc = irq_to_desc(irq); | |
1723 | ||
1724 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
1725 | return; | |
1726 | ||
1727 | chip_bus_lock(desc); | |
1728 | kfree(__free_percpu_irq(irq, dev_id)); | |
1729 | chip_bus_sync_unlock(desc); | |
1730 | } | |
1731 | ||
1732 | /** | |
1733 | * setup_percpu_irq - setup a per-cpu interrupt | |
1734 | * @irq: Interrupt line to setup | |
1735 | * @act: irqaction for the interrupt | |
1736 | * | |
1737 | * Used to statically setup per-cpu interrupts in the early boot process. | |
1738 | */ | |
1739 | int setup_percpu_irq(unsigned int irq, struct irqaction *act) | |
1740 | { | |
1741 | struct irq_desc *desc = irq_to_desc(irq); | |
1742 | int retval; | |
1743 | ||
1744 | if (!desc || !irq_settings_is_per_cpu_devid(desc)) | |
1745 | return -EINVAL; | |
1746 | chip_bus_lock(desc); | |
1747 | retval = __setup_irq(irq, desc, act); | |
1748 | chip_bus_sync_unlock(desc); | |
1749 | ||
1750 | return retval; | |
1751 | } | |
1752 | ||
1753 | /** | |
1754 | * request_percpu_irq - allocate a percpu interrupt line | |
1755 | * @irq: Interrupt line to allocate | |
1756 | * @handler: Function to be called when the IRQ occurs. | |
1757 | * @devname: An ascii name for the claiming device | |
1758 | * @dev_id: A percpu cookie passed back to the handler function | |
1759 | * | |
1760 | * This call allocates interrupt resources, but doesn't | |
1761 | * automatically enable the interrupt. It has to be done on each | |
1762 | * CPU using enable_percpu_irq(). | |
1763 | * | |
1764 | * Dev_id must be globally unique. It is a per-cpu variable, and | |
1765 | * the handler gets called with the interrupted CPU's instance of | |
1766 | * that variable. | |
1767 | */ | |
1768 | int request_percpu_irq(unsigned int irq, irq_handler_t handler, | |
1769 | const char *devname, void __percpu *dev_id) | |
1770 | { | |
1771 | struct irqaction *action; | |
1772 | struct irq_desc *desc; | |
1773 | int retval; | |
1774 | ||
1775 | if (!dev_id) | |
1776 | return -EINVAL; | |
1777 | ||
1778 | desc = irq_to_desc(irq); | |
1779 | if (!desc || !irq_settings_can_request(desc) || | |
1780 | !irq_settings_is_per_cpu_devid(desc)) | |
1781 | return -EINVAL; | |
1782 | ||
1783 | action = kzalloc(sizeof(struct irqaction), GFP_KERNEL); | |
1784 | if (!action) | |
1785 | return -ENOMEM; | |
1786 | ||
1787 | action->handler = handler; | |
2ed0e645 | 1788 | action->flags = IRQF_PERCPU | IRQF_NO_SUSPEND; |
31d9d9b6 MZ |
1789 | action->name = devname; |
1790 | action->percpu_dev_id = dev_id; | |
1791 | ||
1792 | chip_bus_lock(desc); | |
1793 | retval = __setup_irq(irq, desc, action); | |
1794 | chip_bus_sync_unlock(desc); | |
1795 | ||
1796 | if (retval) | |
1797 | kfree(action); | |
1798 | ||
1799 | return retval; | |
1800 | } | |
1b7047ed MZ |
1801 | |
1802 | /** | |
1803 | * irq_get_irqchip_state - returns the irqchip state of a interrupt. | |
1804 | * @irq: Interrupt line that is forwarded to a VM | |
1805 | * @which: One of IRQCHIP_STATE_* the caller wants to know about | |
1806 | * @state: a pointer to a boolean where the state is to be storeed | |
1807 | * | |
1808 | * This call snapshots the internal irqchip state of an | |
1809 | * interrupt, returning into @state the bit corresponding to | |
1810 | * stage @which | |
1811 | * | |
1812 | * This function should be called with preemption disabled if the | |
1813 | * interrupt controller has per-cpu registers. | |
1814 | */ | |
1815 | int irq_get_irqchip_state(unsigned int irq, enum irqchip_irq_state which, | |
1816 | bool *state) | |
1817 | { | |
1818 | struct irq_desc *desc; | |
1819 | struct irq_data *data; | |
1820 | struct irq_chip *chip; | |
1821 | unsigned long flags; | |
1822 | int err = -EINVAL; | |
1823 | ||
1824 | desc = irq_get_desc_buslock(irq, &flags, 0); | |
1825 | if (!desc) | |
1826 | return err; | |
1827 | ||
1828 | data = irq_desc_get_irq_data(desc); | |
1829 | ||
1830 | do { | |
1831 | chip = irq_data_get_irq_chip(data); | |
1832 | if (chip->irq_get_irqchip_state) | |
1833 | break; | |
1834 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
1835 | data = data->parent_data; | |
1836 | #else | |
1837 | data = NULL; | |
1838 | #endif | |
1839 | } while (data); | |
1840 | ||
1841 | if (data) | |
1842 | err = chip->irq_get_irqchip_state(data, which, state); | |
1843 | ||
1844 | irq_put_desc_busunlock(desc, flags); | |
1845 | return err; | |
1846 | } | |
1847 | ||
1848 | /** | |
1849 | * irq_set_irqchip_state - set the state of a forwarded interrupt. | |
1850 | * @irq: Interrupt line that is forwarded to a VM | |
1851 | * @which: State to be restored (one of IRQCHIP_STATE_*) | |
1852 | * @val: Value corresponding to @which | |
1853 | * | |
1854 | * This call sets the internal irqchip state of an interrupt, | |
1855 | * depending on the value of @which. | |
1856 | * | |
1857 | * This function should be called with preemption disabled if the | |
1858 | * interrupt controller has per-cpu registers. | |
1859 | */ | |
1860 | int irq_set_irqchip_state(unsigned int irq, enum irqchip_irq_state which, | |
1861 | bool val) | |
1862 | { | |
1863 | struct irq_desc *desc; | |
1864 | struct irq_data *data; | |
1865 | struct irq_chip *chip; | |
1866 | unsigned long flags; | |
1867 | int err = -EINVAL; | |
1868 | ||
1869 | desc = irq_get_desc_buslock(irq, &flags, 0); | |
1870 | if (!desc) | |
1871 | return err; | |
1872 | ||
1873 | data = irq_desc_get_irq_data(desc); | |
1874 | ||
1875 | do { | |
1876 | chip = irq_data_get_irq_chip(data); | |
1877 | if (chip->irq_set_irqchip_state) | |
1878 | break; | |
1879 | #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY | |
1880 | data = data->parent_data; | |
1881 | #else | |
1882 | data = NULL; | |
1883 | #endif | |
1884 | } while (data); | |
1885 | ||
1886 | if (data) | |
1887 | err = chip->irq_set_irqchip_state(data, which, val); | |
1888 | ||
1889 | irq_put_desc_busunlock(desc, flags); | |
1890 | return err; | |
1891 | } |