Commit | Line | Data |
---|---|---|
f8381cba TG |
1 | /* |
2 | * linux/kernel/time/tick-broadcast.c | |
3 | * | |
4 | * This file contains functions which emulate a local clock-event | |
5 | * device via a broadcast event source. | |
6 | * | |
7 | * Copyright(C) 2005-2006, Thomas Gleixner <tglx@linutronix.de> | |
8 | * Copyright(C) 2005-2007, Red Hat, Inc., Ingo Molnar | |
9 | * Copyright(C) 2006-2007, Timesys Corp., Thomas Gleixner | |
10 | * | |
11 | * This code is licenced under the GPL version 2. For details see | |
12 | * kernel-base/COPYING. | |
13 | */ | |
14 | #include <linux/cpu.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/hrtimer.h> | |
d7b90689 | 17 | #include <linux/interrupt.h> |
f8381cba TG |
18 | #include <linux/percpu.h> |
19 | #include <linux/profile.h> | |
20 | #include <linux/sched.h> | |
12ad1000 | 21 | #include <linux/smp.h> |
f8381cba TG |
22 | |
23 | #include "tick-internal.h" | |
24 | ||
25 | /* | |
26 | * Broadcast support for broken x86 hardware, where the local apic | |
27 | * timer stops in C3 state. | |
28 | */ | |
29 | ||
a52f5c56 | 30 | static struct tick_device tick_broadcast_device; |
6b954823 RR |
31 | /* FIXME: Use cpumask_var_t. */ |
32 | static DECLARE_BITMAP(tick_broadcast_mask, NR_CPUS); | |
33 | static DECLARE_BITMAP(tmpmask, NR_CPUS); | |
b5f91da0 | 34 | static DEFINE_RAW_SPINLOCK(tick_broadcast_lock); |
aa276e1c | 35 | static int tick_broadcast_force; |
f8381cba | 36 | |
5590a536 TG |
37 | #ifdef CONFIG_TICK_ONESHOT |
38 | static void tick_broadcast_clear_oneshot(int cpu); | |
39 | #else | |
40 | static inline void tick_broadcast_clear_oneshot(int cpu) { } | |
41 | #endif | |
42 | ||
289f480a IM |
43 | /* |
44 | * Debugging: see timer_list.c | |
45 | */ | |
46 | struct tick_device *tick_get_broadcast_device(void) | |
47 | { | |
48 | return &tick_broadcast_device; | |
49 | } | |
50 | ||
6b954823 | 51 | struct cpumask *tick_get_broadcast_mask(void) |
289f480a | 52 | { |
6b954823 | 53 | return to_cpumask(tick_broadcast_mask); |
289f480a IM |
54 | } |
55 | ||
f8381cba TG |
56 | /* |
57 | * Start the device in periodic mode | |
58 | */ | |
59 | static void tick_broadcast_start_periodic(struct clock_event_device *bc) | |
60 | { | |
18de5bc4 | 61 | if (bc) |
f8381cba TG |
62 | tick_setup_periodic(bc, 1); |
63 | } | |
64 | ||
65 | /* | |
66 | * Check, if the device can be utilized as broadcast device: | |
67 | */ | |
68 | int tick_check_broadcast_device(struct clock_event_device *dev) | |
69 | { | |
4a93232d VP |
70 | if ((tick_broadcast_device.evtdev && |
71 | tick_broadcast_device.evtdev->rating >= dev->rating) || | |
72 | (dev->features & CLOCK_EVT_FEAT_C3STOP)) | |
f8381cba TG |
73 | return 0; |
74 | ||
c1be8430 | 75 | clockevents_exchange_device(tick_broadcast_device.evtdev, dev); |
f8381cba | 76 | tick_broadcast_device.evtdev = dev; |
6b954823 | 77 | if (!cpumask_empty(tick_get_broadcast_mask())) |
f8381cba TG |
78 | tick_broadcast_start_periodic(dev); |
79 | return 1; | |
80 | } | |
81 | ||
82 | /* | |
83 | * Check, if the device is the broadcast device | |
84 | */ | |
85 | int tick_is_broadcast_device(struct clock_event_device *dev) | |
86 | { | |
87 | return (dev && tick_broadcast_device.evtdev == dev); | |
88 | } | |
89 | ||
12ad1000 MR |
90 | static void err_broadcast(const struct cpumask *mask) |
91 | { | |
92 | pr_crit_once("Failed to broadcast timer tick. Some CPUs may be unresponsive.\n"); | |
93 | } | |
94 | ||
5d1d9a29 MR |
95 | static void tick_device_setup_broadcast_func(struct clock_event_device *dev) |
96 | { | |
97 | if (!dev->broadcast) | |
98 | dev->broadcast = tick_broadcast; | |
99 | if (!dev->broadcast) { | |
100 | pr_warn_once("%s depends on broadcast, but no broadcast function available\n", | |
101 | dev->name); | |
102 | dev->broadcast = err_broadcast; | |
103 | } | |
104 | } | |
105 | ||
f8381cba TG |
106 | /* |
107 | * Check, if the device is disfunctional and a place holder, which | |
108 | * needs to be handled by the broadcast device. | |
109 | */ | |
110 | int tick_device_uses_broadcast(struct clock_event_device *dev, int cpu) | |
111 | { | |
112 | unsigned long flags; | |
113 | int ret = 0; | |
114 | ||
b5f91da0 | 115 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
f8381cba TG |
116 | |
117 | /* | |
118 | * Devices might be registered with both periodic and oneshot | |
119 | * mode disabled. This signals, that the device needs to be | |
120 | * operated from the broadcast device and is a placeholder for | |
121 | * the cpu local device. | |
122 | */ | |
123 | if (!tick_device_is_functional(dev)) { | |
124 | dev->event_handler = tick_handle_periodic; | |
5d1d9a29 | 125 | tick_device_setup_broadcast_func(dev); |
6b954823 | 126 | cpumask_set_cpu(cpu, tick_get_broadcast_mask()); |
f8381cba TG |
127 | tick_broadcast_start_periodic(tick_broadcast_device.evtdev); |
128 | ret = 1; | |
5590a536 TG |
129 | } else { |
130 | /* | |
131 | * When the new device is not affected by the stop | |
132 | * feature and the cpu is marked in the broadcast mask | |
133 | * then clear the broadcast bit. | |
134 | */ | |
135 | if (!(dev->features & CLOCK_EVT_FEAT_C3STOP)) { | |
136 | int cpu = smp_processor_id(); | |
6b954823 | 137 | cpumask_clear_cpu(cpu, tick_get_broadcast_mask()); |
5590a536 | 138 | tick_broadcast_clear_oneshot(cpu); |
5d1d9a29 MR |
139 | } else { |
140 | tick_device_setup_broadcast_func(dev); | |
5590a536 TG |
141 | } |
142 | } | |
b5f91da0 | 143 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
f8381cba TG |
144 | return ret; |
145 | } | |
146 | ||
12572dbb MR |
147 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
148 | int tick_receive_broadcast(void) | |
149 | { | |
150 | struct tick_device *td = this_cpu_ptr(&tick_cpu_device); | |
151 | struct clock_event_device *evt = td->evtdev; | |
152 | ||
153 | if (!evt) | |
154 | return -ENODEV; | |
155 | ||
156 | if (!evt->event_handler) | |
157 | return -EINVAL; | |
158 | ||
159 | evt->event_handler(evt); | |
160 | return 0; | |
161 | } | |
162 | #endif | |
163 | ||
f8381cba | 164 | /* |
6b954823 | 165 | * Broadcast the event to the cpus, which are set in the mask (mangled). |
f8381cba | 166 | */ |
6b954823 | 167 | static void tick_do_broadcast(struct cpumask *mask) |
f8381cba | 168 | { |
186e3cb8 | 169 | int cpu = smp_processor_id(); |
f8381cba TG |
170 | struct tick_device *td; |
171 | ||
172 | /* | |
173 | * Check, if the current cpu is in the mask | |
174 | */ | |
6b954823 RR |
175 | if (cpumask_test_cpu(cpu, mask)) { |
176 | cpumask_clear_cpu(cpu, mask); | |
f8381cba TG |
177 | td = &per_cpu(tick_cpu_device, cpu); |
178 | td->evtdev->event_handler(td->evtdev); | |
f8381cba TG |
179 | } |
180 | ||
6b954823 | 181 | if (!cpumask_empty(mask)) { |
f8381cba TG |
182 | /* |
183 | * It might be necessary to actually check whether the devices | |
184 | * have different broadcast functions. For now, just use the | |
185 | * one of the first device. This works as long as we have this | |
186 | * misfeature only on x86 (lapic) | |
187 | */ | |
6b954823 RR |
188 | td = &per_cpu(tick_cpu_device, cpumask_first(mask)); |
189 | td->evtdev->broadcast(mask); | |
f8381cba | 190 | } |
f8381cba TG |
191 | } |
192 | ||
193 | /* | |
194 | * Periodic broadcast: | |
195 | * - invoke the broadcast handlers | |
196 | */ | |
197 | static void tick_do_periodic_broadcast(void) | |
198 | { | |
b5f91da0 | 199 | raw_spin_lock(&tick_broadcast_lock); |
f8381cba | 200 | |
6b954823 RR |
201 | cpumask_and(to_cpumask(tmpmask), |
202 | cpu_online_mask, tick_get_broadcast_mask()); | |
203 | tick_do_broadcast(to_cpumask(tmpmask)); | |
f8381cba | 204 | |
b5f91da0 | 205 | raw_spin_unlock(&tick_broadcast_lock); |
f8381cba TG |
206 | } |
207 | ||
208 | /* | |
209 | * Event handler for periodic broadcast ticks | |
210 | */ | |
211 | static void tick_handle_periodic_broadcast(struct clock_event_device *dev) | |
212 | { | |
d4496b39 TG |
213 | ktime_t next; |
214 | ||
f8381cba TG |
215 | tick_do_periodic_broadcast(); |
216 | ||
217 | /* | |
218 | * The device is in periodic mode. No reprogramming necessary: | |
219 | */ | |
220 | if (dev->mode == CLOCK_EVT_MODE_PERIODIC) | |
221 | return; | |
222 | ||
223 | /* | |
224 | * Setup the next period for devices, which do not have | |
d4496b39 | 225 | * periodic mode. We read dev->next_event first and add to it |
698f9315 | 226 | * when the event already expired. clockevents_program_event() |
d4496b39 TG |
227 | * sets dev->next_event only when the event is really |
228 | * programmed to the device. | |
f8381cba | 229 | */ |
d4496b39 TG |
230 | for (next = dev->next_event; ;) { |
231 | next = ktime_add(next, tick_period); | |
f8381cba | 232 | |
d1748302 | 233 | if (!clockevents_program_event(dev, next, false)) |
f8381cba TG |
234 | return; |
235 | tick_do_periodic_broadcast(); | |
236 | } | |
237 | } | |
238 | ||
239 | /* | |
240 | * Powerstate information: The system enters/leaves a state, where | |
241 | * affected devices might stop | |
242 | */ | |
f833bab8 | 243 | static void tick_do_broadcast_on_off(unsigned long *reason) |
f8381cba TG |
244 | { |
245 | struct clock_event_device *bc, *dev; | |
246 | struct tick_device *td; | |
f833bab8 | 247 | unsigned long flags; |
9c17bcda | 248 | int cpu, bc_stopped; |
f8381cba | 249 | |
b5f91da0 | 250 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
f8381cba TG |
251 | |
252 | cpu = smp_processor_id(); | |
253 | td = &per_cpu(tick_cpu_device, cpu); | |
254 | dev = td->evtdev; | |
255 | bc = tick_broadcast_device.evtdev; | |
256 | ||
257 | /* | |
1595f452 | 258 | * Is the device not affected by the powerstate ? |
f8381cba | 259 | */ |
1595f452 | 260 | if (!dev || !(dev->features & CLOCK_EVT_FEAT_C3STOP)) |
f8381cba TG |
261 | goto out; |
262 | ||
3dfbc884 TG |
263 | if (!tick_device_is_functional(dev)) |
264 | goto out; | |
1595f452 | 265 | |
6b954823 | 266 | bc_stopped = cpumask_empty(tick_get_broadcast_mask()); |
9c17bcda | 267 | |
1595f452 TG |
268 | switch (*reason) { |
269 | case CLOCK_EVT_NOTIFY_BROADCAST_ON: | |
270 | case CLOCK_EVT_NOTIFY_BROADCAST_FORCE: | |
6b954823 RR |
271 | if (!cpumask_test_cpu(cpu, tick_get_broadcast_mask())) { |
272 | cpumask_set_cpu(cpu, tick_get_broadcast_mask()); | |
07454bff TG |
273 | if (tick_broadcast_device.mode == |
274 | TICKDEV_MODE_PERIODIC) | |
2344abbc | 275 | clockevents_shutdown(dev); |
f8381cba | 276 | } |
3dfbc884 | 277 | if (*reason == CLOCK_EVT_NOTIFY_BROADCAST_FORCE) |
aa276e1c | 278 | tick_broadcast_force = 1; |
1595f452 TG |
279 | break; |
280 | case CLOCK_EVT_NOTIFY_BROADCAST_OFF: | |
aa276e1c | 281 | if (!tick_broadcast_force && |
6b954823 RR |
282 | cpumask_test_cpu(cpu, tick_get_broadcast_mask())) { |
283 | cpumask_clear_cpu(cpu, tick_get_broadcast_mask()); | |
07454bff TG |
284 | if (tick_broadcast_device.mode == |
285 | TICKDEV_MODE_PERIODIC) | |
f8381cba TG |
286 | tick_setup_periodic(dev, 0); |
287 | } | |
1595f452 | 288 | break; |
f8381cba TG |
289 | } |
290 | ||
6b954823 | 291 | if (cpumask_empty(tick_get_broadcast_mask())) { |
9c17bcda | 292 | if (!bc_stopped) |
2344abbc | 293 | clockevents_shutdown(bc); |
9c17bcda | 294 | } else if (bc_stopped) { |
f8381cba TG |
295 | if (tick_broadcast_device.mode == TICKDEV_MODE_PERIODIC) |
296 | tick_broadcast_start_periodic(bc); | |
79bf2bb3 TG |
297 | else |
298 | tick_broadcast_setup_oneshot(bc); | |
f8381cba TG |
299 | } |
300 | out: | |
b5f91da0 | 301 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
f8381cba TG |
302 | } |
303 | ||
304 | /* | |
305 | * Powerstate information: The system enters/leaves a state, where | |
306 | * affected devices might stop. | |
307 | */ | |
308 | void tick_broadcast_on_off(unsigned long reason, int *oncpu) | |
309 | { | |
6b954823 | 310 | if (!cpumask_test_cpu(*oncpu, cpu_online_mask)) |
833df317 | 311 | printk(KERN_ERR "tick-broadcast: ignoring broadcast for " |
72fcde96 | 312 | "offline CPU #%d\n", *oncpu); |
bf020cb7 | 313 | else |
f833bab8 | 314 | tick_do_broadcast_on_off(&reason); |
f8381cba TG |
315 | } |
316 | ||
317 | /* | |
318 | * Set the periodic handler depending on broadcast on/off | |
319 | */ | |
320 | void tick_set_periodic_handler(struct clock_event_device *dev, int broadcast) | |
321 | { | |
322 | if (!broadcast) | |
323 | dev->event_handler = tick_handle_periodic; | |
324 | else | |
325 | dev->event_handler = tick_handle_periodic_broadcast; | |
326 | } | |
327 | ||
328 | /* | |
329 | * Remove a CPU from broadcasting | |
330 | */ | |
331 | void tick_shutdown_broadcast(unsigned int *cpup) | |
332 | { | |
333 | struct clock_event_device *bc; | |
334 | unsigned long flags; | |
335 | unsigned int cpu = *cpup; | |
336 | ||
b5f91da0 | 337 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
f8381cba TG |
338 | |
339 | bc = tick_broadcast_device.evtdev; | |
6b954823 | 340 | cpumask_clear_cpu(cpu, tick_get_broadcast_mask()); |
f8381cba TG |
341 | |
342 | if (tick_broadcast_device.mode == TICKDEV_MODE_PERIODIC) { | |
6b954823 | 343 | if (bc && cpumask_empty(tick_get_broadcast_mask())) |
2344abbc | 344 | clockevents_shutdown(bc); |
f8381cba TG |
345 | } |
346 | ||
b5f91da0 | 347 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
f8381cba | 348 | } |
79bf2bb3 | 349 | |
6321dd60 TG |
350 | void tick_suspend_broadcast(void) |
351 | { | |
352 | struct clock_event_device *bc; | |
353 | unsigned long flags; | |
354 | ||
b5f91da0 | 355 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
6321dd60 TG |
356 | |
357 | bc = tick_broadcast_device.evtdev; | |
18de5bc4 | 358 | if (bc) |
2344abbc | 359 | clockevents_shutdown(bc); |
6321dd60 | 360 | |
b5f91da0 | 361 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
6321dd60 TG |
362 | } |
363 | ||
364 | int tick_resume_broadcast(void) | |
365 | { | |
366 | struct clock_event_device *bc; | |
367 | unsigned long flags; | |
368 | int broadcast = 0; | |
369 | ||
b5f91da0 | 370 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
6321dd60 TG |
371 | |
372 | bc = tick_broadcast_device.evtdev; | |
6321dd60 | 373 | |
cd05a1f8 | 374 | if (bc) { |
18de5bc4 TG |
375 | clockevents_set_mode(bc, CLOCK_EVT_MODE_RESUME); |
376 | ||
cd05a1f8 TG |
377 | switch (tick_broadcast_device.mode) { |
378 | case TICKDEV_MODE_PERIODIC: | |
6b954823 | 379 | if (!cpumask_empty(tick_get_broadcast_mask())) |
cd05a1f8 | 380 | tick_broadcast_start_periodic(bc); |
6b954823 RR |
381 | broadcast = cpumask_test_cpu(smp_processor_id(), |
382 | tick_get_broadcast_mask()); | |
cd05a1f8 TG |
383 | break; |
384 | case TICKDEV_MODE_ONESHOT: | |
a6371f80 SS |
385 | if (!cpumask_empty(tick_get_broadcast_mask())) |
386 | broadcast = tick_resume_broadcast_oneshot(bc); | |
cd05a1f8 TG |
387 | break; |
388 | } | |
6321dd60 | 389 | } |
b5f91da0 | 390 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
6321dd60 TG |
391 | |
392 | return broadcast; | |
393 | } | |
394 | ||
395 | ||
79bf2bb3 TG |
396 | #ifdef CONFIG_TICK_ONESHOT |
397 | ||
6b954823 RR |
398 | /* FIXME: use cpumask_var_t. */ |
399 | static DECLARE_BITMAP(tick_broadcast_oneshot_mask, NR_CPUS); | |
79bf2bb3 | 400 | |
289f480a | 401 | /* |
6b954823 | 402 | * Exposed for debugging: see timer_list.c |
289f480a | 403 | */ |
6b954823 | 404 | struct cpumask *tick_get_broadcast_oneshot_mask(void) |
289f480a | 405 | { |
6b954823 | 406 | return to_cpumask(tick_broadcast_oneshot_mask); |
289f480a IM |
407 | } |
408 | ||
79bf2bb3 TG |
409 | static int tick_broadcast_set_event(ktime_t expires, int force) |
410 | { | |
411 | struct clock_event_device *bc = tick_broadcast_device.evtdev; | |
1fb9b7d2 | 412 | |
b9a6a235 TG |
413 | if (bc->mode != CLOCK_EVT_MODE_ONESHOT) |
414 | clockevents_set_mode(bc, CLOCK_EVT_MODE_ONESHOT); | |
415 | ||
d1748302 | 416 | return clockevents_program_event(bc, expires, force); |
79bf2bb3 TG |
417 | } |
418 | ||
cd05a1f8 TG |
419 | int tick_resume_broadcast_oneshot(struct clock_event_device *bc) |
420 | { | |
421 | clockevents_set_mode(bc, CLOCK_EVT_MODE_ONESHOT); | |
b7e113dc | 422 | return 0; |
cd05a1f8 TG |
423 | } |
424 | ||
fb02fbc1 TG |
425 | /* |
426 | * Called from irq_enter() when idle was interrupted to reenable the | |
427 | * per cpu device. | |
428 | */ | |
429 | void tick_check_oneshot_broadcast(int cpu) | |
430 | { | |
6b954823 | 431 | if (cpumask_test_cpu(cpu, to_cpumask(tick_broadcast_oneshot_mask))) { |
fb02fbc1 TG |
432 | struct tick_device *td = &per_cpu(tick_cpu_device, cpu); |
433 | ||
434 | clockevents_set_mode(td->evtdev, CLOCK_EVT_MODE_ONESHOT); | |
435 | } | |
436 | } | |
437 | ||
79bf2bb3 TG |
438 | /* |
439 | * Handle oneshot mode broadcasting | |
440 | */ | |
441 | static void tick_handle_oneshot_broadcast(struct clock_event_device *dev) | |
442 | { | |
443 | struct tick_device *td; | |
cdc6f27d | 444 | ktime_t now, next_event; |
79bf2bb3 TG |
445 | int cpu; |
446 | ||
b5f91da0 | 447 | raw_spin_lock(&tick_broadcast_lock); |
79bf2bb3 TG |
448 | again: |
449 | dev->next_event.tv64 = KTIME_MAX; | |
cdc6f27d | 450 | next_event.tv64 = KTIME_MAX; |
6b954823 | 451 | cpumask_clear(to_cpumask(tmpmask)); |
79bf2bb3 TG |
452 | now = ktime_get(); |
453 | /* Find all expired events */ | |
6b954823 | 454 | for_each_cpu(cpu, tick_get_broadcast_oneshot_mask()) { |
79bf2bb3 TG |
455 | td = &per_cpu(tick_cpu_device, cpu); |
456 | if (td->evtdev->next_event.tv64 <= now.tv64) | |
6b954823 | 457 | cpumask_set_cpu(cpu, to_cpumask(tmpmask)); |
cdc6f27d TG |
458 | else if (td->evtdev->next_event.tv64 < next_event.tv64) |
459 | next_event.tv64 = td->evtdev->next_event.tv64; | |
79bf2bb3 TG |
460 | } |
461 | ||
462 | /* | |
cdc6f27d TG |
463 | * Wakeup the cpus which have an expired event. |
464 | */ | |
6b954823 | 465 | tick_do_broadcast(to_cpumask(tmpmask)); |
cdc6f27d TG |
466 | |
467 | /* | |
468 | * Two reasons for reprogram: | |
469 | * | |
470 | * - The global event did not expire any CPU local | |
471 | * events. This happens in dyntick mode, as the maximum PIT | |
472 | * delta is quite small. | |
473 | * | |
474 | * - There are pending events on sleeping CPUs which were not | |
475 | * in the event mask | |
79bf2bb3 | 476 | */ |
cdc6f27d | 477 | if (next_event.tv64 != KTIME_MAX) { |
79bf2bb3 | 478 | /* |
cdc6f27d TG |
479 | * Rearm the broadcast device. If event expired, |
480 | * repeat the above | |
79bf2bb3 | 481 | */ |
cdc6f27d | 482 | if (tick_broadcast_set_event(next_event, 0)) |
79bf2bb3 TG |
483 | goto again; |
484 | } | |
b5f91da0 | 485 | raw_spin_unlock(&tick_broadcast_lock); |
79bf2bb3 TG |
486 | } |
487 | ||
488 | /* | |
489 | * Powerstate information: The system enters/leaves a state, where | |
490 | * affected devices might stop | |
491 | */ | |
492 | void tick_broadcast_oneshot_control(unsigned long reason) | |
493 | { | |
494 | struct clock_event_device *bc, *dev; | |
495 | struct tick_device *td; | |
496 | unsigned long flags; | |
497 | int cpu; | |
498 | ||
79bf2bb3 TG |
499 | /* |
500 | * Periodic mode does not care about the enter/exit of power | |
501 | * states | |
502 | */ | |
503 | if (tick_broadcast_device.mode == TICKDEV_MODE_PERIODIC) | |
7372b0b1 | 504 | return; |
79bf2bb3 | 505 | |
7372b0b1 AK |
506 | /* |
507 | * We are called with preemtion disabled from the depth of the | |
508 | * idle code, so we can't be moved away. | |
509 | */ | |
79bf2bb3 TG |
510 | cpu = smp_processor_id(); |
511 | td = &per_cpu(tick_cpu_device, cpu); | |
512 | dev = td->evtdev; | |
513 | ||
514 | if (!(dev->features & CLOCK_EVT_FEAT_C3STOP)) | |
7372b0b1 AK |
515 | return; |
516 | ||
517 | bc = tick_broadcast_device.evtdev; | |
79bf2bb3 | 518 | |
7372b0b1 | 519 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
79bf2bb3 | 520 | if (reason == CLOCK_EVT_NOTIFY_BROADCAST_ENTER) { |
6b954823 RR |
521 | if (!cpumask_test_cpu(cpu, tick_get_broadcast_oneshot_mask())) { |
522 | cpumask_set_cpu(cpu, tick_get_broadcast_oneshot_mask()); | |
79bf2bb3 TG |
523 | clockevents_set_mode(dev, CLOCK_EVT_MODE_SHUTDOWN); |
524 | if (dev->next_event.tv64 < bc->next_event.tv64) | |
525 | tick_broadcast_set_event(dev->next_event, 1); | |
526 | } | |
527 | } else { | |
6b954823 RR |
528 | if (cpumask_test_cpu(cpu, tick_get_broadcast_oneshot_mask())) { |
529 | cpumask_clear_cpu(cpu, | |
530 | tick_get_broadcast_oneshot_mask()); | |
79bf2bb3 TG |
531 | clockevents_set_mode(dev, CLOCK_EVT_MODE_ONESHOT); |
532 | if (dev->next_event.tv64 != KTIME_MAX) | |
533 | tick_program_event(dev->next_event, 1); | |
534 | } | |
535 | } | |
b5f91da0 | 536 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
79bf2bb3 TG |
537 | } |
538 | ||
5590a536 TG |
539 | /* |
540 | * Reset the one shot broadcast for a cpu | |
541 | * | |
542 | * Called with tick_broadcast_lock held | |
543 | */ | |
544 | static void tick_broadcast_clear_oneshot(int cpu) | |
545 | { | |
6b954823 | 546 | cpumask_clear_cpu(cpu, tick_get_broadcast_oneshot_mask()); |
5590a536 TG |
547 | } |
548 | ||
6b954823 RR |
549 | static void tick_broadcast_init_next_event(struct cpumask *mask, |
550 | ktime_t expires) | |
7300711e TG |
551 | { |
552 | struct tick_device *td; | |
553 | int cpu; | |
554 | ||
5db0e1e9 | 555 | for_each_cpu(cpu, mask) { |
7300711e TG |
556 | td = &per_cpu(tick_cpu_device, cpu); |
557 | if (td->evtdev) | |
558 | td->evtdev->next_event = expires; | |
559 | } | |
560 | } | |
561 | ||
79bf2bb3 | 562 | /** |
8dce39c2 | 563 | * tick_broadcast_setup_oneshot - setup the broadcast device |
79bf2bb3 TG |
564 | */ |
565 | void tick_broadcast_setup_oneshot(struct clock_event_device *bc) | |
566 | { | |
07f4beb0 TG |
567 | int cpu = smp_processor_id(); |
568 | ||
9c17bcda TG |
569 | /* Set it up only once ! */ |
570 | if (bc->event_handler != tick_handle_oneshot_broadcast) { | |
7300711e | 571 | int was_periodic = bc->mode == CLOCK_EVT_MODE_PERIODIC; |
7300711e | 572 | |
9c17bcda | 573 | bc->event_handler = tick_handle_oneshot_broadcast; |
7300711e TG |
574 | |
575 | /* Take the do_timer update */ | |
576 | tick_do_timer_cpu = cpu; | |
577 | ||
578 | /* | |
579 | * We must be careful here. There might be other CPUs | |
580 | * waiting for periodic broadcast. We need to set the | |
581 | * oneshot_mask bits for those and program the | |
582 | * broadcast device to fire. | |
583 | */ | |
6b954823 RR |
584 | cpumask_copy(to_cpumask(tmpmask), tick_get_broadcast_mask()); |
585 | cpumask_clear_cpu(cpu, to_cpumask(tmpmask)); | |
586 | cpumask_or(tick_get_broadcast_oneshot_mask(), | |
587 | tick_get_broadcast_oneshot_mask(), | |
588 | to_cpumask(tmpmask)); | |
589 | ||
590 | if (was_periodic && !cpumask_empty(to_cpumask(tmpmask))) { | |
b435092f | 591 | clockevents_set_mode(bc, CLOCK_EVT_MODE_ONESHOT); |
6b954823 RR |
592 | tick_broadcast_init_next_event(to_cpumask(tmpmask), |
593 | tick_next_period); | |
7300711e TG |
594 | tick_broadcast_set_event(tick_next_period, 1); |
595 | } else | |
596 | bc->next_event.tv64 = KTIME_MAX; | |
07f4beb0 TG |
597 | } else { |
598 | /* | |
599 | * The first cpu which switches to oneshot mode sets | |
600 | * the bit for all other cpus which are in the general | |
601 | * (periodic) broadcast mask. So the bit is set and | |
602 | * would prevent the first broadcast enter after this | |
603 | * to program the bc device. | |
604 | */ | |
605 | tick_broadcast_clear_oneshot(cpu); | |
9c17bcda | 606 | } |
79bf2bb3 TG |
607 | } |
608 | ||
609 | /* | |
610 | * Select oneshot operating mode for the broadcast device | |
611 | */ | |
612 | void tick_broadcast_switch_to_oneshot(void) | |
613 | { | |
614 | struct clock_event_device *bc; | |
615 | unsigned long flags; | |
616 | ||
b5f91da0 | 617 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
fa4da365 SS |
618 | |
619 | tick_broadcast_device.mode = TICKDEV_MODE_ONESHOT; | |
79bf2bb3 TG |
620 | bc = tick_broadcast_device.evtdev; |
621 | if (bc) | |
622 | tick_broadcast_setup_oneshot(bc); | |
77b0d60c | 623 | |
b5f91da0 | 624 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
79bf2bb3 TG |
625 | } |
626 | ||
627 | ||
628 | /* | |
629 | * Remove a dead CPU from broadcasting | |
630 | */ | |
631 | void tick_shutdown_broadcast_oneshot(unsigned int *cpup) | |
632 | { | |
79bf2bb3 TG |
633 | unsigned long flags; |
634 | unsigned int cpu = *cpup; | |
635 | ||
b5f91da0 | 636 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
79bf2bb3 | 637 | |
31d9b393 TG |
638 | /* |
639 | * Clear the broadcast mask flag for the dead cpu, but do not | |
640 | * stop the broadcast device! | |
641 | */ | |
6b954823 | 642 | cpumask_clear_cpu(cpu, tick_get_broadcast_oneshot_mask()); |
79bf2bb3 | 643 | |
b5f91da0 | 644 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
79bf2bb3 TG |
645 | } |
646 | ||
27ce4cb4 TG |
647 | /* |
648 | * Check, whether the broadcast device is in one shot mode | |
649 | */ | |
650 | int tick_broadcast_oneshot_active(void) | |
651 | { | |
652 | return tick_broadcast_device.mode == TICKDEV_MODE_ONESHOT; | |
653 | } | |
654 | ||
3a142a06 TG |
655 | /* |
656 | * Check whether the broadcast device supports oneshot. | |
657 | */ | |
658 | bool tick_broadcast_oneshot_available(void) | |
659 | { | |
660 | struct clock_event_device *bc = tick_broadcast_device.evtdev; | |
661 | ||
662 | return bc ? bc->features & CLOCK_EVT_FEAT_ONESHOT : false; | |
663 | } | |
664 | ||
79bf2bb3 | 665 | #endif |