Commit | Line | Data |
---|---|---|
f8381cba TG |
1 | /* |
2 | * linux/kernel/time/tick-broadcast.c | |
3 | * | |
4 | * This file contains functions which emulate a local clock-event | |
5 | * device via a broadcast event source. | |
6 | * | |
7 | * Copyright(C) 2005-2006, Thomas Gleixner <tglx@linutronix.de> | |
8 | * Copyright(C) 2005-2007, Red Hat, Inc., Ingo Molnar | |
9 | * Copyright(C) 2006-2007, Timesys Corp., Thomas Gleixner | |
10 | * | |
11 | * This code is licenced under the GPL version 2. For details see | |
12 | * kernel-base/COPYING. | |
13 | */ | |
14 | #include <linux/cpu.h> | |
15 | #include <linux/err.h> | |
16 | #include <linux/hrtimer.h> | |
d7b90689 | 17 | #include <linux/interrupt.h> |
f8381cba TG |
18 | #include <linux/percpu.h> |
19 | #include <linux/profile.h> | |
20 | #include <linux/sched.h> | |
12ad1000 | 21 | #include <linux/smp.h> |
f8381cba TG |
22 | |
23 | #include "tick-internal.h" | |
24 | ||
25 | /* | |
26 | * Broadcast support for broken x86 hardware, where the local apic | |
27 | * timer stops in C3 state. | |
28 | */ | |
29 | ||
a52f5c56 | 30 | static struct tick_device tick_broadcast_device; |
b352bc1c TG |
31 | static cpumask_var_t tick_broadcast_mask; |
32 | static cpumask_var_t tmpmask; | |
b5f91da0 | 33 | static DEFINE_RAW_SPINLOCK(tick_broadcast_lock); |
aa276e1c | 34 | static int tick_broadcast_force; |
f8381cba | 35 | |
5590a536 TG |
36 | #ifdef CONFIG_TICK_ONESHOT |
37 | static void tick_broadcast_clear_oneshot(int cpu); | |
38 | #else | |
39 | static inline void tick_broadcast_clear_oneshot(int cpu) { } | |
40 | #endif | |
41 | ||
289f480a IM |
42 | /* |
43 | * Debugging: see timer_list.c | |
44 | */ | |
45 | struct tick_device *tick_get_broadcast_device(void) | |
46 | { | |
47 | return &tick_broadcast_device; | |
48 | } | |
49 | ||
6b954823 | 50 | struct cpumask *tick_get_broadcast_mask(void) |
289f480a | 51 | { |
b352bc1c | 52 | return tick_broadcast_mask; |
289f480a IM |
53 | } |
54 | ||
f8381cba TG |
55 | /* |
56 | * Start the device in periodic mode | |
57 | */ | |
58 | static void tick_broadcast_start_periodic(struct clock_event_device *bc) | |
59 | { | |
18de5bc4 | 60 | if (bc) |
f8381cba TG |
61 | tick_setup_periodic(bc, 1); |
62 | } | |
63 | ||
64 | /* | |
65 | * Check, if the device can be utilized as broadcast device: | |
66 | */ | |
67 | int tick_check_broadcast_device(struct clock_event_device *dev) | |
68 | { | |
4a93232d VP |
69 | if ((tick_broadcast_device.evtdev && |
70 | tick_broadcast_device.evtdev->rating >= dev->rating) || | |
71 | (dev->features & CLOCK_EVT_FEAT_C3STOP)) | |
f8381cba TG |
72 | return 0; |
73 | ||
c1be8430 | 74 | clockevents_exchange_device(tick_broadcast_device.evtdev, dev); |
f8381cba | 75 | tick_broadcast_device.evtdev = dev; |
b352bc1c | 76 | if (!cpumask_empty(tick_broadcast_mask)) |
f8381cba TG |
77 | tick_broadcast_start_periodic(dev); |
78 | return 1; | |
79 | } | |
80 | ||
81 | /* | |
82 | * Check, if the device is the broadcast device | |
83 | */ | |
84 | int tick_is_broadcast_device(struct clock_event_device *dev) | |
85 | { | |
86 | return (dev && tick_broadcast_device.evtdev == dev); | |
87 | } | |
88 | ||
12ad1000 MR |
89 | static void err_broadcast(const struct cpumask *mask) |
90 | { | |
91 | pr_crit_once("Failed to broadcast timer tick. Some CPUs may be unresponsive.\n"); | |
92 | } | |
93 | ||
5d1d9a29 MR |
94 | static void tick_device_setup_broadcast_func(struct clock_event_device *dev) |
95 | { | |
96 | if (!dev->broadcast) | |
97 | dev->broadcast = tick_broadcast; | |
98 | if (!dev->broadcast) { | |
99 | pr_warn_once("%s depends on broadcast, but no broadcast function available\n", | |
100 | dev->name); | |
101 | dev->broadcast = err_broadcast; | |
102 | } | |
103 | } | |
104 | ||
f8381cba TG |
105 | /* |
106 | * Check, if the device is disfunctional and a place holder, which | |
107 | * needs to be handled by the broadcast device. | |
108 | */ | |
109 | int tick_device_uses_broadcast(struct clock_event_device *dev, int cpu) | |
110 | { | |
111 | unsigned long flags; | |
112 | int ret = 0; | |
113 | ||
b5f91da0 | 114 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
f8381cba TG |
115 | |
116 | /* | |
117 | * Devices might be registered with both periodic and oneshot | |
118 | * mode disabled. This signals, that the device needs to be | |
119 | * operated from the broadcast device and is a placeholder for | |
120 | * the cpu local device. | |
121 | */ | |
122 | if (!tick_device_is_functional(dev)) { | |
123 | dev->event_handler = tick_handle_periodic; | |
5d1d9a29 | 124 | tick_device_setup_broadcast_func(dev); |
b352bc1c | 125 | cpumask_set_cpu(cpu, tick_broadcast_mask); |
f8381cba TG |
126 | tick_broadcast_start_periodic(tick_broadcast_device.evtdev); |
127 | ret = 1; | |
5590a536 TG |
128 | } else { |
129 | /* | |
130 | * When the new device is not affected by the stop | |
131 | * feature and the cpu is marked in the broadcast mask | |
132 | * then clear the broadcast bit. | |
133 | */ | |
134 | if (!(dev->features & CLOCK_EVT_FEAT_C3STOP)) { | |
135 | int cpu = smp_processor_id(); | |
b352bc1c | 136 | cpumask_clear_cpu(cpu, tick_broadcast_mask); |
5590a536 | 137 | tick_broadcast_clear_oneshot(cpu); |
5d1d9a29 MR |
138 | } else { |
139 | tick_device_setup_broadcast_func(dev); | |
5590a536 TG |
140 | } |
141 | } | |
b5f91da0 | 142 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
f8381cba TG |
143 | return ret; |
144 | } | |
145 | ||
12572dbb MR |
146 | #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST |
147 | int tick_receive_broadcast(void) | |
148 | { | |
149 | struct tick_device *td = this_cpu_ptr(&tick_cpu_device); | |
150 | struct clock_event_device *evt = td->evtdev; | |
151 | ||
152 | if (!evt) | |
153 | return -ENODEV; | |
154 | ||
155 | if (!evt->event_handler) | |
156 | return -EINVAL; | |
157 | ||
158 | evt->event_handler(evt); | |
159 | return 0; | |
160 | } | |
161 | #endif | |
162 | ||
f8381cba | 163 | /* |
6b954823 | 164 | * Broadcast the event to the cpus, which are set in the mask (mangled). |
f8381cba | 165 | */ |
6b954823 | 166 | static void tick_do_broadcast(struct cpumask *mask) |
f8381cba | 167 | { |
186e3cb8 | 168 | int cpu = smp_processor_id(); |
f8381cba TG |
169 | struct tick_device *td; |
170 | ||
171 | /* | |
172 | * Check, if the current cpu is in the mask | |
173 | */ | |
6b954823 RR |
174 | if (cpumask_test_cpu(cpu, mask)) { |
175 | cpumask_clear_cpu(cpu, mask); | |
f8381cba TG |
176 | td = &per_cpu(tick_cpu_device, cpu); |
177 | td->evtdev->event_handler(td->evtdev); | |
f8381cba TG |
178 | } |
179 | ||
6b954823 | 180 | if (!cpumask_empty(mask)) { |
f8381cba TG |
181 | /* |
182 | * It might be necessary to actually check whether the devices | |
183 | * have different broadcast functions. For now, just use the | |
184 | * one of the first device. This works as long as we have this | |
185 | * misfeature only on x86 (lapic) | |
186 | */ | |
6b954823 RR |
187 | td = &per_cpu(tick_cpu_device, cpumask_first(mask)); |
188 | td->evtdev->broadcast(mask); | |
f8381cba | 189 | } |
f8381cba TG |
190 | } |
191 | ||
192 | /* | |
193 | * Periodic broadcast: | |
194 | * - invoke the broadcast handlers | |
195 | */ | |
196 | static void tick_do_periodic_broadcast(void) | |
197 | { | |
b5f91da0 | 198 | raw_spin_lock(&tick_broadcast_lock); |
f8381cba | 199 | |
b352bc1c TG |
200 | cpumask_and(tmpmask, cpu_online_mask, tick_broadcast_mask); |
201 | tick_do_broadcast(tmpmask); | |
f8381cba | 202 | |
b5f91da0 | 203 | raw_spin_unlock(&tick_broadcast_lock); |
f8381cba TG |
204 | } |
205 | ||
206 | /* | |
207 | * Event handler for periodic broadcast ticks | |
208 | */ | |
209 | static void tick_handle_periodic_broadcast(struct clock_event_device *dev) | |
210 | { | |
d4496b39 TG |
211 | ktime_t next; |
212 | ||
f8381cba TG |
213 | tick_do_periodic_broadcast(); |
214 | ||
215 | /* | |
216 | * The device is in periodic mode. No reprogramming necessary: | |
217 | */ | |
218 | if (dev->mode == CLOCK_EVT_MODE_PERIODIC) | |
219 | return; | |
220 | ||
221 | /* | |
222 | * Setup the next period for devices, which do not have | |
d4496b39 | 223 | * periodic mode. We read dev->next_event first and add to it |
698f9315 | 224 | * when the event already expired. clockevents_program_event() |
d4496b39 TG |
225 | * sets dev->next_event only when the event is really |
226 | * programmed to the device. | |
f8381cba | 227 | */ |
d4496b39 TG |
228 | for (next = dev->next_event; ;) { |
229 | next = ktime_add(next, tick_period); | |
f8381cba | 230 | |
d1748302 | 231 | if (!clockevents_program_event(dev, next, false)) |
f8381cba TG |
232 | return; |
233 | tick_do_periodic_broadcast(); | |
234 | } | |
235 | } | |
236 | ||
237 | /* | |
238 | * Powerstate information: The system enters/leaves a state, where | |
239 | * affected devices might stop | |
240 | */ | |
f833bab8 | 241 | static void tick_do_broadcast_on_off(unsigned long *reason) |
f8381cba TG |
242 | { |
243 | struct clock_event_device *bc, *dev; | |
244 | struct tick_device *td; | |
f833bab8 | 245 | unsigned long flags; |
9c17bcda | 246 | int cpu, bc_stopped; |
f8381cba | 247 | |
b5f91da0 | 248 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
f8381cba TG |
249 | |
250 | cpu = smp_processor_id(); | |
251 | td = &per_cpu(tick_cpu_device, cpu); | |
252 | dev = td->evtdev; | |
253 | bc = tick_broadcast_device.evtdev; | |
254 | ||
255 | /* | |
1595f452 | 256 | * Is the device not affected by the powerstate ? |
f8381cba | 257 | */ |
1595f452 | 258 | if (!dev || !(dev->features & CLOCK_EVT_FEAT_C3STOP)) |
f8381cba TG |
259 | goto out; |
260 | ||
3dfbc884 TG |
261 | if (!tick_device_is_functional(dev)) |
262 | goto out; | |
1595f452 | 263 | |
b352bc1c | 264 | bc_stopped = cpumask_empty(tick_broadcast_mask); |
9c17bcda | 265 | |
1595f452 TG |
266 | switch (*reason) { |
267 | case CLOCK_EVT_NOTIFY_BROADCAST_ON: | |
268 | case CLOCK_EVT_NOTIFY_BROADCAST_FORCE: | |
b352bc1c | 269 | if (!cpumask_test_and_set_cpu(cpu, tick_broadcast_mask)) { |
07454bff TG |
270 | if (tick_broadcast_device.mode == |
271 | TICKDEV_MODE_PERIODIC) | |
2344abbc | 272 | clockevents_shutdown(dev); |
f8381cba | 273 | } |
3dfbc884 | 274 | if (*reason == CLOCK_EVT_NOTIFY_BROADCAST_FORCE) |
aa276e1c | 275 | tick_broadcast_force = 1; |
1595f452 TG |
276 | break; |
277 | case CLOCK_EVT_NOTIFY_BROADCAST_OFF: | |
aa276e1c | 278 | if (!tick_broadcast_force && |
b352bc1c | 279 | cpumask_test_and_clear_cpu(cpu, tick_broadcast_mask)) { |
07454bff TG |
280 | if (tick_broadcast_device.mode == |
281 | TICKDEV_MODE_PERIODIC) | |
f8381cba TG |
282 | tick_setup_periodic(dev, 0); |
283 | } | |
1595f452 | 284 | break; |
f8381cba TG |
285 | } |
286 | ||
b352bc1c | 287 | if (cpumask_empty(tick_broadcast_mask)) { |
9c17bcda | 288 | if (!bc_stopped) |
2344abbc | 289 | clockevents_shutdown(bc); |
9c17bcda | 290 | } else if (bc_stopped) { |
f8381cba TG |
291 | if (tick_broadcast_device.mode == TICKDEV_MODE_PERIODIC) |
292 | tick_broadcast_start_periodic(bc); | |
79bf2bb3 TG |
293 | else |
294 | tick_broadcast_setup_oneshot(bc); | |
f8381cba TG |
295 | } |
296 | out: | |
b5f91da0 | 297 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
f8381cba TG |
298 | } |
299 | ||
300 | /* | |
301 | * Powerstate information: The system enters/leaves a state, where | |
302 | * affected devices might stop. | |
303 | */ | |
304 | void tick_broadcast_on_off(unsigned long reason, int *oncpu) | |
305 | { | |
6b954823 | 306 | if (!cpumask_test_cpu(*oncpu, cpu_online_mask)) |
833df317 | 307 | printk(KERN_ERR "tick-broadcast: ignoring broadcast for " |
72fcde96 | 308 | "offline CPU #%d\n", *oncpu); |
bf020cb7 | 309 | else |
f833bab8 | 310 | tick_do_broadcast_on_off(&reason); |
f8381cba TG |
311 | } |
312 | ||
313 | /* | |
314 | * Set the periodic handler depending on broadcast on/off | |
315 | */ | |
316 | void tick_set_periodic_handler(struct clock_event_device *dev, int broadcast) | |
317 | { | |
318 | if (!broadcast) | |
319 | dev->event_handler = tick_handle_periodic; | |
320 | else | |
321 | dev->event_handler = tick_handle_periodic_broadcast; | |
322 | } | |
323 | ||
324 | /* | |
325 | * Remove a CPU from broadcasting | |
326 | */ | |
327 | void tick_shutdown_broadcast(unsigned int *cpup) | |
328 | { | |
329 | struct clock_event_device *bc; | |
330 | unsigned long flags; | |
331 | unsigned int cpu = *cpup; | |
332 | ||
b5f91da0 | 333 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
f8381cba TG |
334 | |
335 | bc = tick_broadcast_device.evtdev; | |
b352bc1c | 336 | cpumask_clear_cpu(cpu, tick_broadcast_mask); |
f8381cba TG |
337 | |
338 | if (tick_broadcast_device.mode == TICKDEV_MODE_PERIODIC) { | |
b352bc1c | 339 | if (bc && cpumask_empty(tick_broadcast_mask)) |
2344abbc | 340 | clockevents_shutdown(bc); |
f8381cba TG |
341 | } |
342 | ||
b5f91da0 | 343 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
f8381cba | 344 | } |
79bf2bb3 | 345 | |
6321dd60 TG |
346 | void tick_suspend_broadcast(void) |
347 | { | |
348 | struct clock_event_device *bc; | |
349 | unsigned long flags; | |
350 | ||
b5f91da0 | 351 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
6321dd60 TG |
352 | |
353 | bc = tick_broadcast_device.evtdev; | |
18de5bc4 | 354 | if (bc) |
2344abbc | 355 | clockevents_shutdown(bc); |
6321dd60 | 356 | |
b5f91da0 | 357 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
6321dd60 TG |
358 | } |
359 | ||
360 | int tick_resume_broadcast(void) | |
361 | { | |
362 | struct clock_event_device *bc; | |
363 | unsigned long flags; | |
364 | int broadcast = 0; | |
365 | ||
b5f91da0 | 366 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
6321dd60 TG |
367 | |
368 | bc = tick_broadcast_device.evtdev; | |
6321dd60 | 369 | |
cd05a1f8 | 370 | if (bc) { |
18de5bc4 TG |
371 | clockevents_set_mode(bc, CLOCK_EVT_MODE_RESUME); |
372 | ||
cd05a1f8 TG |
373 | switch (tick_broadcast_device.mode) { |
374 | case TICKDEV_MODE_PERIODIC: | |
b352bc1c | 375 | if (!cpumask_empty(tick_broadcast_mask)) |
cd05a1f8 | 376 | tick_broadcast_start_periodic(bc); |
6b954823 | 377 | broadcast = cpumask_test_cpu(smp_processor_id(), |
b352bc1c | 378 | tick_broadcast_mask); |
cd05a1f8 TG |
379 | break; |
380 | case TICKDEV_MODE_ONESHOT: | |
b352bc1c | 381 | if (!cpumask_empty(tick_broadcast_mask)) |
a6371f80 | 382 | broadcast = tick_resume_broadcast_oneshot(bc); |
cd05a1f8 TG |
383 | break; |
384 | } | |
6321dd60 | 385 | } |
b5f91da0 | 386 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
6321dd60 TG |
387 | |
388 | return broadcast; | |
389 | } | |
390 | ||
391 | ||
79bf2bb3 TG |
392 | #ifdef CONFIG_TICK_ONESHOT |
393 | ||
b352bc1c | 394 | static cpumask_var_t tick_broadcast_oneshot_mask; |
26517f3e | 395 | static cpumask_var_t tick_broadcast_pending_mask; |
79bf2bb3 | 396 | |
289f480a | 397 | /* |
6b954823 | 398 | * Exposed for debugging: see timer_list.c |
289f480a | 399 | */ |
6b954823 | 400 | struct cpumask *tick_get_broadcast_oneshot_mask(void) |
289f480a | 401 | { |
b352bc1c | 402 | return tick_broadcast_oneshot_mask; |
289f480a IM |
403 | } |
404 | ||
d2348fb6 DL |
405 | /* |
406 | * Set broadcast interrupt affinity | |
407 | */ | |
408 | static void tick_broadcast_set_affinity(struct clock_event_device *bc, | |
409 | const struct cpumask *cpumask) | |
410 | { | |
411 | if (!(bc->features & CLOCK_EVT_FEAT_DYNIRQ)) | |
412 | return; | |
413 | ||
414 | if (cpumask_equal(bc->cpumask, cpumask)) | |
415 | return; | |
416 | ||
417 | bc->cpumask = cpumask; | |
418 | irq_set_affinity(bc->irq, bc->cpumask); | |
419 | } | |
420 | ||
421 | static int tick_broadcast_set_event(struct clock_event_device *bc, int cpu, | |
f9ae39d0 | 422 | ktime_t expires, int force) |
79bf2bb3 | 423 | { |
d2348fb6 DL |
424 | int ret; |
425 | ||
b9a6a235 TG |
426 | if (bc->mode != CLOCK_EVT_MODE_ONESHOT) |
427 | clockevents_set_mode(bc, CLOCK_EVT_MODE_ONESHOT); | |
428 | ||
d2348fb6 DL |
429 | ret = clockevents_program_event(bc, expires, force); |
430 | if (!ret) | |
431 | tick_broadcast_set_affinity(bc, cpumask_of(cpu)); | |
432 | return ret; | |
79bf2bb3 TG |
433 | } |
434 | ||
cd05a1f8 TG |
435 | int tick_resume_broadcast_oneshot(struct clock_event_device *bc) |
436 | { | |
437 | clockevents_set_mode(bc, CLOCK_EVT_MODE_ONESHOT); | |
b7e113dc | 438 | return 0; |
cd05a1f8 TG |
439 | } |
440 | ||
fb02fbc1 TG |
441 | /* |
442 | * Called from irq_enter() when idle was interrupted to reenable the | |
443 | * per cpu device. | |
444 | */ | |
445 | void tick_check_oneshot_broadcast(int cpu) | |
446 | { | |
b352bc1c | 447 | if (cpumask_test_cpu(cpu, tick_broadcast_oneshot_mask)) { |
fb02fbc1 TG |
448 | struct tick_device *td = &per_cpu(tick_cpu_device, cpu); |
449 | ||
450 | clockevents_set_mode(td->evtdev, CLOCK_EVT_MODE_ONESHOT); | |
451 | } | |
452 | } | |
453 | ||
79bf2bb3 TG |
454 | /* |
455 | * Handle oneshot mode broadcasting | |
456 | */ | |
457 | static void tick_handle_oneshot_broadcast(struct clock_event_device *dev) | |
458 | { | |
459 | struct tick_device *td; | |
cdc6f27d | 460 | ktime_t now, next_event; |
d2348fb6 | 461 | int cpu, next_cpu = 0; |
79bf2bb3 | 462 | |
b5f91da0 | 463 | raw_spin_lock(&tick_broadcast_lock); |
79bf2bb3 TG |
464 | again: |
465 | dev->next_event.tv64 = KTIME_MAX; | |
cdc6f27d | 466 | next_event.tv64 = KTIME_MAX; |
b352bc1c | 467 | cpumask_clear(tmpmask); |
79bf2bb3 TG |
468 | now = ktime_get(); |
469 | /* Find all expired events */ | |
b352bc1c | 470 | for_each_cpu(cpu, tick_broadcast_oneshot_mask) { |
79bf2bb3 | 471 | td = &per_cpu(tick_cpu_device, cpu); |
d2348fb6 | 472 | if (td->evtdev->next_event.tv64 <= now.tv64) { |
b352bc1c | 473 | cpumask_set_cpu(cpu, tmpmask); |
26517f3e TG |
474 | /* |
475 | * Mark the remote cpu in the pending mask, so | |
476 | * it can avoid reprogramming the cpu local | |
477 | * timer in tick_broadcast_oneshot_control(). | |
478 | */ | |
479 | cpumask_set_cpu(cpu, tick_broadcast_pending_mask); | |
d2348fb6 | 480 | } else if (td->evtdev->next_event.tv64 < next_event.tv64) { |
cdc6f27d | 481 | next_event.tv64 = td->evtdev->next_event.tv64; |
d2348fb6 DL |
482 | next_cpu = cpu; |
483 | } | |
79bf2bb3 TG |
484 | } |
485 | ||
486 | /* | |
cdc6f27d TG |
487 | * Wakeup the cpus which have an expired event. |
488 | */ | |
b352bc1c | 489 | tick_do_broadcast(tmpmask); |
cdc6f27d TG |
490 | |
491 | /* | |
492 | * Two reasons for reprogram: | |
493 | * | |
494 | * - The global event did not expire any CPU local | |
495 | * events. This happens in dyntick mode, as the maximum PIT | |
496 | * delta is quite small. | |
497 | * | |
498 | * - There are pending events on sleeping CPUs which were not | |
499 | * in the event mask | |
79bf2bb3 | 500 | */ |
cdc6f27d | 501 | if (next_event.tv64 != KTIME_MAX) { |
79bf2bb3 | 502 | /* |
cdc6f27d TG |
503 | * Rearm the broadcast device. If event expired, |
504 | * repeat the above | |
79bf2bb3 | 505 | */ |
d2348fb6 | 506 | if (tick_broadcast_set_event(dev, next_cpu, next_event, 0)) |
79bf2bb3 TG |
507 | goto again; |
508 | } | |
b5f91da0 | 509 | raw_spin_unlock(&tick_broadcast_lock); |
79bf2bb3 TG |
510 | } |
511 | ||
512 | /* | |
513 | * Powerstate information: The system enters/leaves a state, where | |
514 | * affected devices might stop | |
515 | */ | |
516 | void tick_broadcast_oneshot_control(unsigned long reason) | |
517 | { | |
518 | struct clock_event_device *bc, *dev; | |
519 | struct tick_device *td; | |
520 | unsigned long flags; | |
521 | int cpu; | |
522 | ||
79bf2bb3 TG |
523 | /* |
524 | * Periodic mode does not care about the enter/exit of power | |
525 | * states | |
526 | */ | |
527 | if (tick_broadcast_device.mode == TICKDEV_MODE_PERIODIC) | |
7372b0b1 | 528 | return; |
79bf2bb3 | 529 | |
7372b0b1 AK |
530 | /* |
531 | * We are called with preemtion disabled from the depth of the | |
532 | * idle code, so we can't be moved away. | |
533 | */ | |
79bf2bb3 TG |
534 | cpu = smp_processor_id(); |
535 | td = &per_cpu(tick_cpu_device, cpu); | |
536 | dev = td->evtdev; | |
537 | ||
538 | if (!(dev->features & CLOCK_EVT_FEAT_C3STOP)) | |
7372b0b1 AK |
539 | return; |
540 | ||
541 | bc = tick_broadcast_device.evtdev; | |
79bf2bb3 | 542 | |
7372b0b1 | 543 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
79bf2bb3 | 544 | if (reason == CLOCK_EVT_NOTIFY_BROADCAST_ENTER) { |
26517f3e | 545 | WARN_ON_ONCE(cpumask_test_cpu(cpu, tick_broadcast_pending_mask)); |
b352bc1c | 546 | if (!cpumask_test_and_set_cpu(cpu, tick_broadcast_oneshot_mask)) { |
79bf2bb3 TG |
547 | clockevents_set_mode(dev, CLOCK_EVT_MODE_SHUTDOWN); |
548 | if (dev->next_event.tv64 < bc->next_event.tv64) | |
d2348fb6 | 549 | tick_broadcast_set_event(bc, cpu, dev->next_event, 1); |
79bf2bb3 TG |
550 | } |
551 | } else { | |
b352bc1c | 552 | if (cpumask_test_and_clear_cpu(cpu, tick_broadcast_oneshot_mask)) { |
79bf2bb3 | 553 | clockevents_set_mode(dev, CLOCK_EVT_MODE_ONESHOT); |
26517f3e TG |
554 | if (dev->next_event.tv64 == KTIME_MAX) |
555 | goto out; | |
556 | /* | |
557 | * The cpu which was handling the broadcast | |
558 | * timer marked this cpu in the broadcast | |
559 | * pending mask and fired the broadcast | |
560 | * IPI. So we are going to handle the expired | |
561 | * event anyway via the broadcast IPI | |
562 | * handler. No need to reprogram the timer | |
563 | * with an already expired event. | |
564 | */ | |
565 | if (cpumask_test_and_clear_cpu(cpu, | |
566 | tick_broadcast_pending_mask)) | |
567 | goto out; | |
568 | ||
569 | tick_program_event(dev->next_event, 1); | |
79bf2bb3 TG |
570 | } |
571 | } | |
26517f3e | 572 | out: |
b5f91da0 | 573 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
79bf2bb3 TG |
574 | } |
575 | ||
5590a536 TG |
576 | /* |
577 | * Reset the one shot broadcast for a cpu | |
578 | * | |
579 | * Called with tick_broadcast_lock held | |
580 | */ | |
581 | static void tick_broadcast_clear_oneshot(int cpu) | |
582 | { | |
b352bc1c | 583 | cpumask_clear_cpu(cpu, tick_broadcast_oneshot_mask); |
5590a536 TG |
584 | } |
585 | ||
6b954823 RR |
586 | static void tick_broadcast_init_next_event(struct cpumask *mask, |
587 | ktime_t expires) | |
7300711e TG |
588 | { |
589 | struct tick_device *td; | |
590 | int cpu; | |
591 | ||
5db0e1e9 | 592 | for_each_cpu(cpu, mask) { |
7300711e TG |
593 | td = &per_cpu(tick_cpu_device, cpu); |
594 | if (td->evtdev) | |
595 | td->evtdev->next_event = expires; | |
596 | } | |
597 | } | |
598 | ||
79bf2bb3 | 599 | /** |
8dce39c2 | 600 | * tick_broadcast_setup_oneshot - setup the broadcast device |
79bf2bb3 TG |
601 | */ |
602 | void tick_broadcast_setup_oneshot(struct clock_event_device *bc) | |
603 | { | |
07f4beb0 TG |
604 | int cpu = smp_processor_id(); |
605 | ||
9c17bcda TG |
606 | /* Set it up only once ! */ |
607 | if (bc->event_handler != tick_handle_oneshot_broadcast) { | |
7300711e | 608 | int was_periodic = bc->mode == CLOCK_EVT_MODE_PERIODIC; |
7300711e | 609 | |
9c17bcda | 610 | bc->event_handler = tick_handle_oneshot_broadcast; |
7300711e TG |
611 | |
612 | /* Take the do_timer update */ | |
613 | tick_do_timer_cpu = cpu; | |
614 | ||
615 | /* | |
616 | * We must be careful here. There might be other CPUs | |
617 | * waiting for periodic broadcast. We need to set the | |
618 | * oneshot_mask bits for those and program the | |
619 | * broadcast device to fire. | |
620 | */ | |
b352bc1c TG |
621 | cpumask_copy(tmpmask, tick_broadcast_mask); |
622 | cpumask_clear_cpu(cpu, tmpmask); | |
623 | cpumask_or(tick_broadcast_oneshot_mask, | |
624 | tick_broadcast_oneshot_mask, tmpmask); | |
6b954823 | 625 | |
b352bc1c | 626 | if (was_periodic && !cpumask_empty(tmpmask)) { |
b435092f | 627 | clockevents_set_mode(bc, CLOCK_EVT_MODE_ONESHOT); |
b352bc1c | 628 | tick_broadcast_init_next_event(tmpmask, |
6b954823 | 629 | tick_next_period); |
d2348fb6 | 630 | tick_broadcast_set_event(bc, cpu, tick_next_period, 1); |
7300711e TG |
631 | } else |
632 | bc->next_event.tv64 = KTIME_MAX; | |
07f4beb0 TG |
633 | } else { |
634 | /* | |
635 | * The first cpu which switches to oneshot mode sets | |
636 | * the bit for all other cpus which are in the general | |
637 | * (periodic) broadcast mask. So the bit is set and | |
638 | * would prevent the first broadcast enter after this | |
639 | * to program the bc device. | |
640 | */ | |
641 | tick_broadcast_clear_oneshot(cpu); | |
9c17bcda | 642 | } |
79bf2bb3 TG |
643 | } |
644 | ||
645 | /* | |
646 | * Select oneshot operating mode for the broadcast device | |
647 | */ | |
648 | void tick_broadcast_switch_to_oneshot(void) | |
649 | { | |
650 | struct clock_event_device *bc; | |
651 | unsigned long flags; | |
652 | ||
b5f91da0 | 653 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
fa4da365 SS |
654 | |
655 | tick_broadcast_device.mode = TICKDEV_MODE_ONESHOT; | |
79bf2bb3 TG |
656 | bc = tick_broadcast_device.evtdev; |
657 | if (bc) | |
658 | tick_broadcast_setup_oneshot(bc); | |
77b0d60c | 659 | |
b5f91da0 | 660 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
79bf2bb3 TG |
661 | } |
662 | ||
663 | ||
664 | /* | |
665 | * Remove a dead CPU from broadcasting | |
666 | */ | |
667 | void tick_shutdown_broadcast_oneshot(unsigned int *cpup) | |
668 | { | |
79bf2bb3 TG |
669 | unsigned long flags; |
670 | unsigned int cpu = *cpup; | |
671 | ||
b5f91da0 | 672 | raw_spin_lock_irqsave(&tick_broadcast_lock, flags); |
79bf2bb3 | 673 | |
31d9b393 TG |
674 | /* |
675 | * Clear the broadcast mask flag for the dead cpu, but do not | |
676 | * stop the broadcast device! | |
677 | */ | |
b352bc1c | 678 | cpumask_clear_cpu(cpu, tick_broadcast_oneshot_mask); |
79bf2bb3 | 679 | |
b5f91da0 | 680 | raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags); |
79bf2bb3 TG |
681 | } |
682 | ||
27ce4cb4 TG |
683 | /* |
684 | * Check, whether the broadcast device is in one shot mode | |
685 | */ | |
686 | int tick_broadcast_oneshot_active(void) | |
687 | { | |
688 | return tick_broadcast_device.mode == TICKDEV_MODE_ONESHOT; | |
689 | } | |
690 | ||
3a142a06 TG |
691 | /* |
692 | * Check whether the broadcast device supports oneshot. | |
693 | */ | |
694 | bool tick_broadcast_oneshot_available(void) | |
695 | { | |
696 | struct clock_event_device *bc = tick_broadcast_device.evtdev; | |
697 | ||
698 | return bc ? bc->features & CLOCK_EVT_FEAT_ONESHOT : false; | |
699 | } | |
700 | ||
79bf2bb3 | 701 | #endif |
b352bc1c TG |
702 | |
703 | void __init tick_broadcast_init(void) | |
704 | { | |
705 | alloc_cpumask_var(&tick_broadcast_mask, GFP_NOWAIT); | |
706 | alloc_cpumask_var(&tmpmask, GFP_NOWAIT); | |
707 | #ifdef CONFIG_TICK_ONESHOT | |
708 | alloc_cpumask_var(&tick_broadcast_oneshot_mask, GFP_NOWAIT); | |
26517f3e | 709 | alloc_cpumask_var(&tick_broadcast_pending_mask, GFP_NOWAIT); |
b352bc1c TG |
710 | #endif |
711 | } |