Add support for relaxing the 32bit ldc/stc instructions.
[deliverable/binutils-gdb.git] / ld / testsuite / ld-h8300 / relax-5-coff.d
CommitLineData
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1# name: H8300 Relaxation Test 5
2# source: relax-5.s
3# ld: --relax -m h8300s
4# objdump: -d --no-show-raw-insn
5
6.*: file format .*-h8300
7
8Disassembly of section .text:
9
1000000100 <_start>:
11 100: 01 40 6b 00 00 00 ldc @0x0:16,ccr
12 106: 01 40 6b 00 7f ff ldc @0x7fff:16,ccr
13 10c: 01 40 6b 20 00 00 80 00 ldc @0x8000:32,ccr
14 114: 01 40 6b 20 00 00 ff 00 ldc @0xff00:32,ccr
15 11c: 01 40 6b 20 00 ff ff 00 ldc @0xffff00:32,ccr
16 124: 01 40 6b 20 ff ff 7f ff ldc @0xffff7fff:32,ccr
17 12c: 01 40 6b 00 80 00 ldc @0x8000:16,ccr
18 132: 01 40 6b 00 fe ff ldc @0xfeff:16,ccr
19 138: 01 40 6b 00 ff 00 ldc @0xff00:16,ccr
20 13e: 01 40 6b 00 ff ff ldc @0xffff:16,ccr
21 144: 01 40 6b 80 00 00 stc ccr,@0x0:16
22 14a: 01 40 6b 80 7f ff stc ccr,@0x7fff:16
23 150: 01 40 6b a0 00 00 80 00 stc ccr,@0x8000:32
24 158: 01 40 6b a0 00 00 ff 00 stc ccr,@0xff00:32
25 160: 01 40 6b a0 00 ff ff 00 stc ccr,@0xffff00:32
26 168: 01 40 6b a0 ff ff 7f ff stc ccr,@0xffff7fff:32
27 170: 01 40 6b 80 80 00 stc ccr,@0x8000:16
28 176: 01 40 6b 80 fe ff stc ccr,@0xfeff:16
29 17c: 01 40 6b 80 ff 00 stc ccr,@0xff00:16
30 182: 01 40 6b 80 ff ff stc ccr,@0xffff:16
31 188: 01 41 6b 00 00 00 ldc @0x0:16,exr
32 18e: 01 41 6b 00 7f ff ldc @0x7fff:16,exr
33 194: 01 41 6b 20 00 00 80 00 ldc @0x8000:32,exr
34 19c: 01 41 6b 20 00 00 ff 00 ldc @0xff00:32,exr
35 1a4: 01 41 6b 20 00 ff ff 00 ldc @0xffff00:32,exr
36 1ac: 01 41 6b 20 ff ff 7f ff ldc @0xffff7fff:32,exr
37 1b4: 01 41 6b 00 80 00 ldc @0x8000:16,exr
38 1ba: 01 41 6b 00 fe ff ldc @0xfeff:16,exr
39 1c0: 01 41 6b 00 ff 00 ldc @0xff00:16,exr
40 1c6: 01 41 6b 00 ff ff ldc @0xffff:16,exr
41 1cc: 01 41 6b 80 00 00 stc exr,@0x0:16
42 1d2: 01 41 6b 80 7f ff stc exr,@0x7fff:16
43 1d8: 01 41 6b a0 00 00 80 00 stc exr,@0x8000:32
44 1e0: 01 41 6b a0 00 00 ff 00 stc exr,@0xff00:32
45 1e8: 01 41 6b a0 00 ff ff 00 stc exr,@0xffff00:32
46 1f0: 01 41 6b a0 ff ff 7f ff stc exr,@0xffff7fff:32
47 1f8: 01 41 6b 80 80 00 stc exr,@0x8000:16
48 1fe: 01 41 6b 80 fe ff stc exr,@0xfeff:16
49 204: 01 41 6b 80 ff 00 stc exr,@0xff00:16
50 20a: 01 41 6b 80 ff ff stc exr,@0xffff:16
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