Commit | Line | Data |
---|---|---|
0fd7d342 | 1 | #source: ovl2.s |
53d25da6 | 2 | #ld: -N -T ovl2.lnk -T ovl.lnk --emit-relocs |
0fd7d342 AM |
3 | #objdump: -D -r |
4 | ||
5 | .*elf32-spu | |
6 | ||
7 | Disassembly of section \.text: | |
8 | ||
9 | 00000100 <_start>: | |
47f6dab9 AM |
10 | .* brsl \$0,.* <00000000\.ovl_call\.f1_a1>.* |
11 | .*SPU_REL16 f1_a1 | |
36cf3ec2 | 12 | .* brsl \$0,.* <00000000\.ovl_call\.setjmp>.* |
47f6dab9 AM |
13 | .*SPU_REL16 setjmp |
14 | .* br 100 <_start> # 100 | |
15 | .*SPU_REL16 _start | |
0fd7d342 AM |
16 | |
17 | 0000010c <setjmp>: | |
47f6dab9 | 18 | .* bi \$0 |
0fd7d342 AM |
19 | |
20 | 00000110 <longjmp>: | |
47f6dab9 | 21 | .* bi \$0 |
bbb0fc04 AM |
22 | |
23 | .*00 00 03 40.* | |
16aef3de AM |
24 | .*SPU_ADDR32 \.ov_a1\+0x14 |
25 | \.\.\. | |
bbb0fc04 AM |
26 | #... |
27 | 00000320 <00000000\.ovl_call.f1_a1>: | |
47f6dab9 AM |
28 | .* ila \$78,1 |
29 | .* lnop | |
16aef3de | 30 | .* ila \$79,1040 # 410 |
cd4a7468 | 31 | .* bra? .* <__ovly_load>.* |
47f6dab9 | 32 | |
bbb0fc04 | 33 | 00000330 <00000000\.ovl_call.setjmp>: |
47f6dab9 AM |
34 | .* ila \$78,0 |
35 | .* lnop | |
36 | .* ila \$79,268 # 10c | |
cd4a7468 | 37 | .* bra? .* <__ovly_load>.* |
0fd7d342 | 38 | |
bbb0fc04 | 39 | 00000340 <00000000\.ovl_call\.13:5>: |
16aef3de AM |
40 | .* ila \$78,1 |
41 | .* lnop | |
42 | .* ila \$79,1044 # 414 | |
cd4a7468 | 43 | .* bra? .* <__ovly_load>.* |
16aef3de | 44 | |
bbb0fc04 | 45 | 00000350 <_SPUEAR_f1_a2>: |
47f6dab9 AM |
46 | .* ila \$78,2 |
47 | .* lnop | |
16aef3de | 48 | .* ila \$79,1040 # 410 |
cd4a7468 | 49 | .* bra? .* <__ovly_load>.* |
47f6dab9 | 50 | |
bbb0fc04 AM |
51 | #00000318 <00000000\.ovl_call.f1_a1>: |
52 | #.* bra?sl \$75,.* <__ovly_load>.* | |
53 | #.*00 04 04 00.* | |
54 | # | |
55 | #00000320 <00000000\.ovl_call.setjmp>: | |
56 | #.* bra?sl \$75,.* <__ovly_load>.* | |
57 | #.*00 00 01 0c.* | |
58 | # | |
59 | #00000328 <_SPUEAR_f1_a2>: | |
60 | #.* bra?sl \$75,.* <__ovly_load>.* | |
61 | #.*00 08 04 00.* | |
62 | ||
0fd7d342 AM |
63 | Disassembly of section \.ov_a1: |
64 | ||
16aef3de AM |
65 | 00000400 <00000001\.ovl_call\.14:6>: |
66 | .* ila \$78,2 | |
67 | .* lnop | |
68 | .* ila \$79,1044 # 414 | |
cd4a7468 | 69 | .* bra? .* <__ovly_load>.* |
16aef3de AM |
70 | |
71 | 00000410 <f1_a1>: | |
72 | .* bi \$0 | |
73 | .*00 00 04 14.* | |
74 | .*SPU_ADDR32 \.ov_a1\+0x14 | |
75 | .*00 00 04 20.* | |
76 | .*SPU_ADDR32 \.ov_a1\+0x20 | |
77 | .*00 00 04 00.* | |
78 | .*SPU_ADDR32 \.ov_a2\+0x14 | |
79 | ||
0fd7d342 AM |
80 | Disassembly of section \.ov_a2: |
81 | ||
16aef3de AM |
82 | 00000400 <00000002\.ovl_call\.13:5>: |
83 | .* ila \$78,1 | |
84 | .* lnop | |
85 | .* ila \$79,1056 # 420 | |
cd4a7468 | 86 | .* bra? .* <__ovly_load>.* |
16aef3de AM |
87 | |
88 | 00000410 <f1_a2>: | |
89 | .* br .* <longjmp>.* | |
90 | .*SPU_REL16 longjmp | |
91 | .*00 00 04 00.* | |
92 | .*SPU_ADDR32 \.ov_a1\+0x20 | |
93 | .*00 00 04 1c.* | |
94 | .*SPU_ADDR32 \.ov_a2\+0x1c | |
95 | .*00 00 00 00.* | |
96 | ||
0fd7d342 AM |
97 | Disassembly of section \.data: |
98 | ||
16aef3de AM |
99 | 00000420 <_ovly_table-0x10>: |
100 | .*00 00 00 00 .* | |
101 | .*00 00 00 01 .* | |
47f6dab9 | 102 | \.\.\. |
16aef3de AM |
103 | 00000430 <_ovly_table>: |
104 | .*00 00 04 00 .* | |
105 | .*00 00 00 20 .* | |
106 | #.*00 00 03 10 .* | |
452de53c | 107 | .*00 00 01 00 .* |
16aef3de AM |
108 | .*00 00 00 01 .* |
109 | .*00 00 04 00 .* | |
110 | .*00 00 00 20 .* | |
111 | #.*00 00 03 20 .* | |
452de53c | 112 | .*00 00 01 20 .* |
16aef3de AM |
113 | .*00 00 00 01 .* |
114 | ||
115 | 00000450 <_ovly_buf_table>: | |
116 | .*00 00 00 00 .* | |
0fd7d342 | 117 | |
0fd7d342 AM |
118 | Disassembly of section \.toe: |
119 | ||
16aef3de | 120 | 00000460 <_EAR_>: |
0fd7d342 | 121 | \.\.\. |
16aef3de AM |
122 | |
123 | Disassembly of section .nonalloc: | |
124 | ||
125 | 00000000 <.nonalloc>: | |
126 | .*00 00 04 14.* | |
127 | .*SPU_ADDR32 \.ov_a1\+0x14 | |
128 | .*00 00 04 20.* | |
129 | .*SPU_ADDR32 \.ov_a1\+0x20 | |
130 | .*00 00 04 14.* | |
131 | .*SPU_ADDR32 \.ov_a2\+0x14 | |
132 | .*00 00 04 1c.* | |
133 | .*SPU_ADDR32 \.ov_a2\+0x1c | |
134 | ||
0fd7d342 AM |
135 | Disassembly of section \.note\.spu_name: |
136 | ||
137 | .* <\.note\.spu_name>: | |
138 | .*: 00 00 00 08 .* | |
139 | .*: 00 00 00 0c .* | |
140 | .*: 00 00 00 01 .* | |
141 | .*: 53 50 55 4e .* | |
142 | .*: 41 4d 45 00 .* | |
143 | .*: 74 6d 70 64 .* | |
144 | .*: 69 72 2f 64 .* | |
145 | .*: 75 6d 70 00 .* |