Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Dynamic DMA mapping support. | |
3 | * | |
563aaf06 | 4 | * This implementation is a fallback for platforms that do not support |
1da177e4 LT |
5 | * I/O TLBs (aka DMA address translation hardware). |
6 | * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com> | |
7 | * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com> | |
8 | * Copyright (C) 2000, 2003 Hewlett-Packard Co | |
9 | * David Mosberger-Tang <davidm@hpl.hp.com> | |
10 | * | |
11 | * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API. | |
12 | * 00/12/13 davidm Rename to swiotlb.c and add mark_clean() to avoid | |
13 | * unnecessary i-cache flushing. | |
569c8bf5 JL |
14 | * 04/07/.. ak Better overflow handling. Assorted fixes. |
15 | * 05/09/10 linville Add support for syncing ranges, support syncing for | |
16 | * DMA_BIDIRECTIONAL mappings, miscellaneous cleanup. | |
fb05a379 | 17 | * 08/12/11 beckyb Add highmem support |
1da177e4 LT |
18 | */ |
19 | ||
20 | #include <linux/cache.h> | |
17e5ad6c | 21 | #include <linux/dma-mapping.h> |
1da177e4 | 22 | #include <linux/mm.h> |
8bc3bcc9 | 23 | #include <linux/export.h> |
1da177e4 LT |
24 | #include <linux/spinlock.h> |
25 | #include <linux/string.h> | |
0016fdee | 26 | #include <linux/swiotlb.h> |
fb05a379 | 27 | #include <linux/pfn.h> |
1da177e4 LT |
28 | #include <linux/types.h> |
29 | #include <linux/ctype.h> | |
ef9b1893 | 30 | #include <linux/highmem.h> |
5a0e3ad6 | 31 | #include <linux/gfp.h> |
1da177e4 LT |
32 | |
33 | #include <asm/io.h> | |
1da177e4 | 34 | #include <asm/dma.h> |
17e5ad6c | 35 | #include <asm/scatterlist.h> |
1da177e4 LT |
36 | |
37 | #include <linux/init.h> | |
38 | #include <linux/bootmem.h> | |
a8522509 | 39 | #include <linux/iommu-helper.h> |
1da177e4 LT |
40 | |
41 | #define OFFSET(val,align) ((unsigned long) \ | |
42 | ( (val) & ( (align) - 1))) | |
43 | ||
0b9afede AW |
44 | #define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT)) |
45 | ||
46 | /* | |
47 | * Minimum IO TLB size to bother booting with. Systems with mainly | |
48 | * 64bit capable cards will only lightly use the swiotlb. If we can't | |
49 | * allocate a contiguous 1MB, we're probably in trouble anyway. | |
50 | */ | |
51 | #define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT) | |
52 | ||
1da177e4 LT |
53 | int swiotlb_force; |
54 | ||
55 | /* | |
bfc5501f KRW |
56 | * Used to do a quick range check in swiotlb_tbl_unmap_single and |
57 | * swiotlb_tbl_sync_single_*, to see if the memory was in fact allocated by this | |
1da177e4 LT |
58 | * API. |
59 | */ | |
60 | static char *io_tlb_start, *io_tlb_end; | |
61 | ||
62 | /* | |
b595076a | 63 | * The number of IO TLB blocks (in groups of 64) between io_tlb_start and |
1da177e4 LT |
64 | * io_tlb_end. This is command line adjustable via setup_io_tlb_npages. |
65 | */ | |
66 | static unsigned long io_tlb_nslabs; | |
67 | ||
68 | /* | |
69 | * When the IOMMU overflows we return a fallback buffer. This sets the size. | |
70 | */ | |
71 | static unsigned long io_tlb_overflow = 32*1024; | |
72 | ||
03620b2d | 73 | static void *io_tlb_overflow_buffer; |
1da177e4 LT |
74 | |
75 | /* | |
76 | * This is a free list describing the number of free entries available from | |
77 | * each index | |
78 | */ | |
79 | static unsigned int *io_tlb_list; | |
80 | static unsigned int io_tlb_index; | |
81 | ||
82 | /* | |
83 | * We need to save away the original address corresponding to a mapped entry | |
84 | * for the sync operations. | |
85 | */ | |
bc40ac66 | 86 | static phys_addr_t *io_tlb_orig_addr; |
1da177e4 LT |
87 | |
88 | /* | |
89 | * Protect the above data structures in the map and unmap calls | |
90 | */ | |
91 | static DEFINE_SPINLOCK(io_tlb_lock); | |
92 | ||
5740afdb FT |
93 | static int late_alloc; |
94 | ||
1da177e4 LT |
95 | static int __init |
96 | setup_io_tlb_npages(char *str) | |
97 | { | |
98 | if (isdigit(*str)) { | |
e8579e72 | 99 | io_tlb_nslabs = simple_strtoul(str, &str, 0); |
1da177e4 LT |
100 | /* avoid tail segment of size < IO_TLB_SEGSIZE */ |
101 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
102 | } | |
103 | if (*str == ',') | |
104 | ++str; | |
b18485e7 | 105 | if (!strcmp(str, "force")) |
1da177e4 | 106 | swiotlb_force = 1; |
b18485e7 | 107 | |
1da177e4 LT |
108 | return 1; |
109 | } | |
110 | __setup("swiotlb=", setup_io_tlb_npages); | |
111 | /* make io_tlb_overflow tunable too? */ | |
112 | ||
f21ffe9f | 113 | unsigned long swiotlb_nr_tbl(void) |
5f98ecdb FT |
114 | { |
115 | return io_tlb_nslabs; | |
116 | } | |
f21ffe9f | 117 | EXPORT_SYMBOL_GPL(swiotlb_nr_tbl); |
02ca646e | 118 | /* Note that this doesn't work with highmem page */ |
70a7d3cc JF |
119 | static dma_addr_t swiotlb_virt_to_bus(struct device *hwdev, |
120 | volatile void *address) | |
e08e1f7a | 121 | { |
862d196b | 122 | return phys_to_dma(hwdev, virt_to_phys(address)); |
e08e1f7a IC |
123 | } |
124 | ||
ad32e8cb | 125 | void swiotlb_print_info(void) |
2e5b2b86 | 126 | { |
ad32e8cb | 127 | unsigned long bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
2e5b2b86 | 128 | phys_addr_t pstart, pend; |
2e5b2b86 IC |
129 | |
130 | pstart = virt_to_phys(io_tlb_start); | |
131 | pend = virt_to_phys(io_tlb_end); | |
132 | ||
3af684c7 BH |
133 | printk(KERN_INFO "software IO TLB [mem %#010llx-%#010llx] (%luMB) mapped at [%p-%p]\n", |
134 | (unsigned long long)pstart, (unsigned long long)pend - 1, | |
135 | bytes >> 20, io_tlb_start, io_tlb_end - 1); | |
2e5b2b86 IC |
136 | } |
137 | ||
abbceff7 | 138 | void __init swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose) |
1da177e4 | 139 | { |
563aaf06 | 140 | unsigned long i, bytes; |
1da177e4 | 141 | |
abbceff7 | 142 | bytes = nslabs << IO_TLB_SHIFT; |
1da177e4 | 143 | |
abbceff7 FT |
144 | io_tlb_nslabs = nslabs; |
145 | io_tlb_start = tlb; | |
563aaf06 | 146 | io_tlb_end = io_tlb_start + bytes; |
1da177e4 LT |
147 | |
148 | /* | |
149 | * Allocate and initialize the free list array. This array is used | |
150 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
151 | * between io_tlb_start and io_tlb_end. | |
152 | */ | |
e79f86b2 | 153 | io_tlb_list = alloc_bootmem_pages(PAGE_ALIGN(io_tlb_nslabs * sizeof(int))); |
25667d67 | 154 | for (i = 0; i < io_tlb_nslabs; i++) |
1da177e4 LT |
155 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); |
156 | io_tlb_index = 0; | |
e79f86b2 | 157 | io_tlb_orig_addr = alloc_bootmem_pages(PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t))); |
1da177e4 LT |
158 | |
159 | /* | |
160 | * Get the overflow emergency buffer | |
161 | */ | |
e79f86b2 | 162 | io_tlb_overflow_buffer = alloc_bootmem_low_pages(PAGE_ALIGN(io_tlb_overflow)); |
563aaf06 JB |
163 | if (!io_tlb_overflow_buffer) |
164 | panic("Cannot allocate SWIOTLB overflow buffer!\n"); | |
ad32e8cb FT |
165 | if (verbose) |
166 | swiotlb_print_info(); | |
1da177e4 LT |
167 | } |
168 | ||
abbceff7 FT |
169 | /* |
170 | * Statically reserve bounce buffer space and initialize bounce buffer data | |
171 | * structures for the software IO TLB used to implement the DMA API. | |
172 | */ | |
173 | void __init | |
174 | swiotlb_init_with_default_size(size_t default_size, int verbose) | |
175 | { | |
176 | unsigned long bytes; | |
177 | ||
178 | if (!io_tlb_nslabs) { | |
179 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
180 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
181 | } | |
182 | ||
183 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; | |
184 | ||
185 | /* | |
186 | * Get IO TLB memory from the low pages | |
187 | */ | |
e79f86b2 | 188 | io_tlb_start = alloc_bootmem_low_pages(PAGE_ALIGN(bytes)); |
abbceff7 FT |
189 | if (!io_tlb_start) |
190 | panic("Cannot allocate SWIOTLB buffer"); | |
191 | ||
192 | swiotlb_init_with_tbl(io_tlb_start, io_tlb_nslabs, verbose); | |
193 | } | |
194 | ||
563aaf06 | 195 | void __init |
ad32e8cb | 196 | swiotlb_init(int verbose) |
1da177e4 | 197 | { |
ad32e8cb | 198 | swiotlb_init_with_default_size(64 * (1<<20), verbose); /* default to 64MB */ |
1da177e4 LT |
199 | } |
200 | ||
0b9afede AW |
201 | /* |
202 | * Systems with larger DMA zones (those that don't support ISA) can | |
203 | * initialize the swiotlb later using the slab allocator if needed. | |
204 | * This should be just like above, but with some error catching. | |
205 | */ | |
206 | int | |
563aaf06 | 207 | swiotlb_late_init_with_default_size(size_t default_size) |
0b9afede | 208 | { |
563aaf06 | 209 | unsigned long i, bytes, req_nslabs = io_tlb_nslabs; |
0b9afede AW |
210 | unsigned int order; |
211 | ||
212 | if (!io_tlb_nslabs) { | |
213 | io_tlb_nslabs = (default_size >> IO_TLB_SHIFT); | |
214 | io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE); | |
215 | } | |
216 | ||
217 | /* | |
218 | * Get IO TLB memory from the low pages | |
219 | */ | |
563aaf06 | 220 | order = get_order(io_tlb_nslabs << IO_TLB_SHIFT); |
0b9afede | 221 | io_tlb_nslabs = SLABS_PER_PAGE << order; |
563aaf06 | 222 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede AW |
223 | |
224 | while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) { | |
bb52196b FT |
225 | io_tlb_start = (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, |
226 | order); | |
0b9afede AW |
227 | if (io_tlb_start) |
228 | break; | |
229 | order--; | |
230 | } | |
231 | ||
232 | if (!io_tlb_start) | |
233 | goto cleanup1; | |
234 | ||
563aaf06 | 235 | if (order != get_order(bytes)) { |
0b9afede AW |
236 | printk(KERN_WARNING "Warning: only able to allocate %ld MB " |
237 | "for software IO TLB\n", (PAGE_SIZE << order) >> 20); | |
238 | io_tlb_nslabs = SLABS_PER_PAGE << order; | |
563aaf06 | 239 | bytes = io_tlb_nslabs << IO_TLB_SHIFT; |
0b9afede | 240 | } |
563aaf06 JB |
241 | io_tlb_end = io_tlb_start + bytes; |
242 | memset(io_tlb_start, 0, bytes); | |
0b9afede AW |
243 | |
244 | /* | |
245 | * Allocate and initialize the free list array. This array is used | |
246 | * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE | |
247 | * between io_tlb_start and io_tlb_end. | |
248 | */ | |
249 | io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL, | |
250 | get_order(io_tlb_nslabs * sizeof(int))); | |
251 | if (!io_tlb_list) | |
252 | goto cleanup2; | |
253 | ||
254 | for (i = 0; i < io_tlb_nslabs; i++) | |
255 | io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE); | |
256 | io_tlb_index = 0; | |
257 | ||
bc40ac66 BB |
258 | io_tlb_orig_addr = (phys_addr_t *) |
259 | __get_free_pages(GFP_KERNEL, | |
260 | get_order(io_tlb_nslabs * | |
261 | sizeof(phys_addr_t))); | |
0b9afede AW |
262 | if (!io_tlb_orig_addr) |
263 | goto cleanup3; | |
264 | ||
bc40ac66 | 265 | memset(io_tlb_orig_addr, 0, io_tlb_nslabs * sizeof(phys_addr_t)); |
0b9afede AW |
266 | |
267 | /* | |
268 | * Get the overflow emergency buffer | |
269 | */ | |
270 | io_tlb_overflow_buffer = (void *)__get_free_pages(GFP_DMA, | |
271 | get_order(io_tlb_overflow)); | |
272 | if (!io_tlb_overflow_buffer) | |
273 | goto cleanup4; | |
274 | ||
ad32e8cb | 275 | swiotlb_print_info(); |
0b9afede | 276 | |
5740afdb FT |
277 | late_alloc = 1; |
278 | ||
0b9afede AW |
279 | return 0; |
280 | ||
281 | cleanup4: | |
bc40ac66 BB |
282 | free_pages((unsigned long)io_tlb_orig_addr, |
283 | get_order(io_tlb_nslabs * sizeof(phys_addr_t))); | |
0b9afede AW |
284 | io_tlb_orig_addr = NULL; |
285 | cleanup3: | |
25667d67 TL |
286 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * |
287 | sizeof(int))); | |
0b9afede | 288 | io_tlb_list = NULL; |
0b9afede | 289 | cleanup2: |
563aaf06 | 290 | io_tlb_end = NULL; |
0b9afede AW |
291 | free_pages((unsigned long)io_tlb_start, order); |
292 | io_tlb_start = NULL; | |
293 | cleanup1: | |
294 | io_tlb_nslabs = req_nslabs; | |
295 | return -ENOMEM; | |
296 | } | |
297 | ||
5740afdb FT |
298 | void __init swiotlb_free(void) |
299 | { | |
300 | if (!io_tlb_overflow_buffer) | |
301 | return; | |
302 | ||
303 | if (late_alloc) { | |
304 | free_pages((unsigned long)io_tlb_overflow_buffer, | |
305 | get_order(io_tlb_overflow)); | |
306 | free_pages((unsigned long)io_tlb_orig_addr, | |
307 | get_order(io_tlb_nslabs * sizeof(phys_addr_t))); | |
308 | free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs * | |
309 | sizeof(int))); | |
310 | free_pages((unsigned long)io_tlb_start, | |
311 | get_order(io_tlb_nslabs << IO_TLB_SHIFT)); | |
312 | } else { | |
313 | free_bootmem_late(__pa(io_tlb_overflow_buffer), | |
e79f86b2 | 314 | PAGE_ALIGN(io_tlb_overflow)); |
5740afdb | 315 | free_bootmem_late(__pa(io_tlb_orig_addr), |
e79f86b2 | 316 | PAGE_ALIGN(io_tlb_nslabs * sizeof(phys_addr_t))); |
5740afdb | 317 | free_bootmem_late(__pa(io_tlb_list), |
e79f86b2 | 318 | PAGE_ALIGN(io_tlb_nslabs * sizeof(int))); |
5740afdb | 319 | free_bootmem_late(__pa(io_tlb_start), |
e79f86b2 | 320 | PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); |
5740afdb | 321 | } |
f21ffe9f | 322 | io_tlb_nslabs = 0; |
5740afdb FT |
323 | } |
324 | ||
02ca646e | 325 | static int is_swiotlb_buffer(phys_addr_t paddr) |
640aebfe | 326 | { |
02ca646e FT |
327 | return paddr >= virt_to_phys(io_tlb_start) && |
328 | paddr < virt_to_phys(io_tlb_end); | |
640aebfe FT |
329 | } |
330 | ||
fb05a379 BB |
331 | /* |
332 | * Bounce: copy the swiotlb buffer back to the original dma location | |
333 | */ | |
d7ef1533 KRW |
334 | void swiotlb_bounce(phys_addr_t phys, char *dma_addr, size_t size, |
335 | enum dma_data_direction dir) | |
fb05a379 BB |
336 | { |
337 | unsigned long pfn = PFN_DOWN(phys); | |
338 | ||
339 | if (PageHighMem(pfn_to_page(pfn))) { | |
340 | /* The buffer does not have a mapping. Map it in and copy */ | |
341 | unsigned int offset = phys & ~PAGE_MASK; | |
342 | char *buffer; | |
343 | unsigned int sz = 0; | |
344 | unsigned long flags; | |
345 | ||
346 | while (size) { | |
67131ad0 | 347 | sz = min_t(size_t, PAGE_SIZE - offset, size); |
fb05a379 BB |
348 | |
349 | local_irq_save(flags); | |
c3eede8e | 350 | buffer = kmap_atomic(pfn_to_page(pfn)); |
fb05a379 BB |
351 | if (dir == DMA_TO_DEVICE) |
352 | memcpy(dma_addr, buffer + offset, sz); | |
ef9b1893 | 353 | else |
fb05a379 | 354 | memcpy(buffer + offset, dma_addr, sz); |
c3eede8e | 355 | kunmap_atomic(buffer); |
ef9b1893 | 356 | local_irq_restore(flags); |
fb05a379 BB |
357 | |
358 | size -= sz; | |
359 | pfn++; | |
360 | dma_addr += sz; | |
361 | offset = 0; | |
ef9b1893 JF |
362 | } |
363 | } else { | |
ef9b1893 | 364 | if (dir == DMA_TO_DEVICE) |
fb05a379 | 365 | memcpy(dma_addr, phys_to_virt(phys), size); |
ef9b1893 | 366 | else |
fb05a379 | 367 | memcpy(phys_to_virt(phys), dma_addr, size); |
ef9b1893 | 368 | } |
1b548f66 | 369 | } |
d7ef1533 | 370 | EXPORT_SYMBOL_GPL(swiotlb_bounce); |
1b548f66 | 371 | |
eb605a57 | 372 | void *swiotlb_tbl_map_single(struct device *hwdev, dma_addr_t tbl_dma_addr, |
22d48269 KRW |
373 | phys_addr_t phys, size_t size, |
374 | enum dma_data_direction dir) | |
1da177e4 LT |
375 | { |
376 | unsigned long flags; | |
377 | char *dma_addr; | |
378 | unsigned int nslots, stride, index, wrap; | |
379 | int i; | |
681cc5cd FT |
380 | unsigned long mask; |
381 | unsigned long offset_slots; | |
382 | unsigned long max_slots; | |
383 | ||
384 | mask = dma_get_seg_boundary(hwdev); | |
681cc5cd | 385 | |
eb605a57 FT |
386 | tbl_dma_addr &= mask; |
387 | ||
388 | offset_slots = ALIGN(tbl_dma_addr, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
a5ddde4a IC |
389 | |
390 | /* | |
391 | * Carefully handle integer overflow which can occur when mask == ~0UL. | |
392 | */ | |
b15a3891 JB |
393 | max_slots = mask + 1 |
394 | ? ALIGN(mask + 1, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT | |
395 | : 1UL << (BITS_PER_LONG - IO_TLB_SHIFT); | |
1da177e4 LT |
396 | |
397 | /* | |
398 | * For mappings greater than a page, we limit the stride (and | |
399 | * hence alignment) to a page size. | |
400 | */ | |
401 | nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
402 | if (size > PAGE_SIZE) | |
403 | stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT)); | |
404 | else | |
405 | stride = 1; | |
406 | ||
34814545 | 407 | BUG_ON(!nslots); |
1da177e4 LT |
408 | |
409 | /* | |
410 | * Find suitable number of IO TLB entries size that will fit this | |
411 | * request and allocate a buffer from that IO TLB pool. | |
412 | */ | |
413 | spin_lock_irqsave(&io_tlb_lock, flags); | |
a7133a15 AM |
414 | index = ALIGN(io_tlb_index, stride); |
415 | if (index >= io_tlb_nslabs) | |
416 | index = 0; | |
417 | wrap = index; | |
418 | ||
419 | do { | |
a8522509 FT |
420 | while (iommu_is_span_boundary(index, nslots, offset_slots, |
421 | max_slots)) { | |
b15a3891 JB |
422 | index += stride; |
423 | if (index >= io_tlb_nslabs) | |
424 | index = 0; | |
a7133a15 AM |
425 | if (index == wrap) |
426 | goto not_found; | |
427 | } | |
428 | ||
429 | /* | |
430 | * If we find a slot that indicates we have 'nslots' number of | |
431 | * contiguous buffers, we allocate the buffers from that slot | |
432 | * and mark the entries as '0' indicating unavailable. | |
433 | */ | |
434 | if (io_tlb_list[index] >= nslots) { | |
435 | int count = 0; | |
436 | ||
437 | for (i = index; i < (int) (index + nslots); i++) | |
438 | io_tlb_list[i] = 0; | |
439 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE - 1) && io_tlb_list[i]; i--) | |
440 | io_tlb_list[i] = ++count; | |
441 | dma_addr = io_tlb_start + (index << IO_TLB_SHIFT); | |
1da177e4 | 442 | |
a7133a15 AM |
443 | /* |
444 | * Update the indices to avoid searching in the next | |
445 | * round. | |
446 | */ | |
447 | io_tlb_index = ((index + nslots) < io_tlb_nslabs | |
448 | ? (index + nslots) : 0); | |
449 | ||
450 | goto found; | |
451 | } | |
452 | index += stride; | |
453 | if (index >= io_tlb_nslabs) | |
454 | index = 0; | |
455 | } while (index != wrap); | |
456 | ||
457 | not_found: | |
458 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
459 | return NULL; | |
460 | found: | |
1da177e4 LT |
461 | spin_unlock_irqrestore(&io_tlb_lock, flags); |
462 | ||
463 | /* | |
464 | * Save away the mapping from the original address to the DMA address. | |
465 | * This is needed when we sync the memory. Then we sync the buffer if | |
466 | * needed. | |
467 | */ | |
bc40ac66 BB |
468 | for (i = 0; i < nslots; i++) |
469 | io_tlb_orig_addr[index+i] = phys + (i << IO_TLB_SHIFT); | |
1da177e4 | 470 | if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL) |
fb05a379 | 471 | swiotlb_bounce(phys, dma_addr, size, DMA_TO_DEVICE); |
1da177e4 LT |
472 | |
473 | return dma_addr; | |
474 | } | |
d7ef1533 | 475 | EXPORT_SYMBOL_GPL(swiotlb_tbl_map_single); |
1da177e4 | 476 | |
eb605a57 FT |
477 | /* |
478 | * Allocates bounce buffer and returns its kernel virtual address. | |
479 | */ | |
480 | ||
481 | static void * | |
22d48269 KRW |
482 | map_single(struct device *hwdev, phys_addr_t phys, size_t size, |
483 | enum dma_data_direction dir) | |
eb605a57 FT |
484 | { |
485 | dma_addr_t start_dma_addr = swiotlb_virt_to_bus(hwdev, io_tlb_start); | |
486 | ||
487 | return swiotlb_tbl_map_single(hwdev, start_dma_addr, phys, size, dir); | |
488 | } | |
489 | ||
1da177e4 LT |
490 | /* |
491 | * dma_addr is the kernel virtual address of the bounce buffer to unmap. | |
492 | */ | |
d7ef1533 | 493 | void |
bfc5501f | 494 | swiotlb_tbl_unmap_single(struct device *hwdev, char *dma_addr, size_t size, |
22d48269 | 495 | enum dma_data_direction dir) |
1da177e4 LT |
496 | { |
497 | unsigned long flags; | |
498 | int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT; | |
499 | int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT; | |
bc40ac66 | 500 | phys_addr_t phys = io_tlb_orig_addr[index]; |
1da177e4 LT |
501 | |
502 | /* | |
503 | * First, sync the memory before unmapping the entry | |
504 | */ | |
bc40ac66 | 505 | if (phys && ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL))) |
fb05a379 | 506 | swiotlb_bounce(phys, dma_addr, size, DMA_FROM_DEVICE); |
1da177e4 LT |
507 | |
508 | /* | |
509 | * Return the buffer to the free list by setting the corresponding | |
af901ca1 | 510 | * entries to indicate the number of contiguous entries available. |
1da177e4 LT |
511 | * While returning the entries to the free list, we merge the entries |
512 | * with slots below and above the pool being returned. | |
513 | */ | |
514 | spin_lock_irqsave(&io_tlb_lock, flags); | |
515 | { | |
516 | count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ? | |
517 | io_tlb_list[index + nslots] : 0); | |
518 | /* | |
519 | * Step 1: return the slots to the free list, merging the | |
520 | * slots with superceeding slots | |
521 | */ | |
522 | for (i = index + nslots - 1; i >= index; i--) | |
523 | io_tlb_list[i] = ++count; | |
524 | /* | |
525 | * Step 2: merge the returned slots with the preceding slots, | |
526 | * if available (non zero) | |
527 | */ | |
528 | for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--) | |
529 | io_tlb_list[i] = ++count; | |
530 | } | |
531 | spin_unlock_irqrestore(&io_tlb_lock, flags); | |
532 | } | |
d7ef1533 | 533 | EXPORT_SYMBOL_GPL(swiotlb_tbl_unmap_single); |
1da177e4 | 534 | |
d7ef1533 | 535 | void |
bfc5501f | 536 | swiotlb_tbl_sync_single(struct device *hwdev, char *dma_addr, size_t size, |
d7ef1533 KRW |
537 | enum dma_data_direction dir, |
538 | enum dma_sync_target target) | |
1da177e4 | 539 | { |
bc40ac66 BB |
540 | int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT; |
541 | phys_addr_t phys = io_tlb_orig_addr[index]; | |
542 | ||
543 | phys += ((unsigned long)dma_addr & ((1 << IO_TLB_SHIFT) - 1)); | |
df336d1c | 544 | |
de69e0f0 JL |
545 | switch (target) { |
546 | case SYNC_FOR_CPU: | |
547 | if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
fb05a379 | 548 | swiotlb_bounce(phys, dma_addr, size, DMA_FROM_DEVICE); |
34814545 ES |
549 | else |
550 | BUG_ON(dir != DMA_TO_DEVICE); | |
de69e0f0 JL |
551 | break; |
552 | case SYNC_FOR_DEVICE: | |
553 | if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)) | |
fb05a379 | 554 | swiotlb_bounce(phys, dma_addr, size, DMA_TO_DEVICE); |
34814545 ES |
555 | else |
556 | BUG_ON(dir != DMA_FROM_DEVICE); | |
de69e0f0 JL |
557 | break; |
558 | default: | |
1da177e4 | 559 | BUG(); |
de69e0f0 | 560 | } |
1da177e4 | 561 | } |
d7ef1533 | 562 | EXPORT_SYMBOL_GPL(swiotlb_tbl_sync_single); |
1da177e4 LT |
563 | |
564 | void * | |
565 | swiotlb_alloc_coherent(struct device *hwdev, size_t size, | |
06a54497 | 566 | dma_addr_t *dma_handle, gfp_t flags) |
1da177e4 | 567 | { |
563aaf06 | 568 | dma_addr_t dev_addr; |
1da177e4 LT |
569 | void *ret; |
570 | int order = get_order(size); | |
284901a9 | 571 | u64 dma_mask = DMA_BIT_MASK(32); |
1e74f300 FT |
572 | |
573 | if (hwdev && hwdev->coherent_dma_mask) | |
574 | dma_mask = hwdev->coherent_dma_mask; | |
1da177e4 | 575 | |
25667d67 | 576 | ret = (void *)__get_free_pages(flags, order); |
ac2b3e67 | 577 | if (ret && swiotlb_virt_to_bus(hwdev, ret) + size - 1 > dma_mask) { |
1da177e4 LT |
578 | /* |
579 | * The allocated memory isn't reachable by the device. | |
1da177e4 LT |
580 | */ |
581 | free_pages((unsigned long) ret, order); | |
582 | ret = NULL; | |
583 | } | |
584 | if (!ret) { | |
585 | /* | |
bfc5501f KRW |
586 | * We are either out of memory or the device can't DMA to |
587 | * GFP_DMA memory; fall back on map_single(), which | |
ceb5ac32 | 588 | * will grab memory from the lowest available address range. |
1da177e4 | 589 | */ |
bc40ac66 | 590 | ret = map_single(hwdev, 0, size, DMA_FROM_DEVICE); |
9dfda12b | 591 | if (!ret) |
1da177e4 | 592 | return NULL; |
1da177e4 LT |
593 | } |
594 | ||
595 | memset(ret, 0, size); | |
70a7d3cc | 596 | dev_addr = swiotlb_virt_to_bus(hwdev, ret); |
1da177e4 LT |
597 | |
598 | /* Confirm address can be DMA'd by device */ | |
ac2b3e67 | 599 | if (dev_addr + size - 1 > dma_mask) { |
563aaf06 | 600 | printk("hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016Lx\n", |
1e74f300 | 601 | (unsigned long long)dma_mask, |
563aaf06 | 602 | (unsigned long long)dev_addr); |
a2b89b59 FT |
603 | |
604 | /* DMA_TO_DEVICE to avoid memcpy in unmap_single */ | |
bfc5501f | 605 | swiotlb_tbl_unmap_single(hwdev, ret, size, DMA_TO_DEVICE); |
a2b89b59 | 606 | return NULL; |
1da177e4 LT |
607 | } |
608 | *dma_handle = dev_addr; | |
609 | return ret; | |
610 | } | |
874d6a95 | 611 | EXPORT_SYMBOL(swiotlb_alloc_coherent); |
1da177e4 LT |
612 | |
613 | void | |
614 | swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr, | |
02ca646e | 615 | dma_addr_t dev_addr) |
1da177e4 | 616 | { |
862d196b | 617 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
02ca646e | 618 | |
aa24886e | 619 | WARN_ON(irqs_disabled()); |
02ca646e FT |
620 | if (!is_swiotlb_buffer(paddr)) |
621 | free_pages((unsigned long)vaddr, get_order(size)); | |
1da177e4 | 622 | else |
bfc5501f KRW |
623 | /* DMA_TO_DEVICE to avoid memcpy in swiotlb_tbl_unmap_single */ |
624 | swiotlb_tbl_unmap_single(hwdev, vaddr, size, DMA_TO_DEVICE); | |
1da177e4 | 625 | } |
874d6a95 | 626 | EXPORT_SYMBOL(swiotlb_free_coherent); |
1da177e4 LT |
627 | |
628 | static void | |
22d48269 KRW |
629 | swiotlb_full(struct device *dev, size_t size, enum dma_data_direction dir, |
630 | int do_panic) | |
1da177e4 LT |
631 | { |
632 | /* | |
633 | * Ran out of IOMMU space for this operation. This is very bad. | |
634 | * Unfortunately the drivers cannot handle this operation properly. | |
17e5ad6c | 635 | * unless they check for dma_mapping_error (most don't) |
1da177e4 LT |
636 | * When the mapping is small enough return a static buffer to limit |
637 | * the damage, or panic when the transfer is too big. | |
638 | */ | |
563aaf06 | 639 | printk(KERN_ERR "DMA: Out of SW-IOMMU space for %zu bytes at " |
94b32486 | 640 | "device %s\n", size, dev ? dev_name(dev) : "?"); |
1da177e4 | 641 | |
c7084b35 CD |
642 | if (size <= io_tlb_overflow || !do_panic) |
643 | return; | |
644 | ||
645 | if (dir == DMA_BIDIRECTIONAL) | |
646 | panic("DMA: Random memory could be DMA accessed\n"); | |
647 | if (dir == DMA_FROM_DEVICE) | |
648 | panic("DMA: Random memory could be DMA written\n"); | |
649 | if (dir == DMA_TO_DEVICE) | |
650 | panic("DMA: Random memory could be DMA read\n"); | |
1da177e4 LT |
651 | } |
652 | ||
653 | /* | |
654 | * Map a single buffer of the indicated size for DMA in streaming mode. The | |
17e5ad6c | 655 | * physical address to use is returned. |
1da177e4 LT |
656 | * |
657 | * Once the device is given the dma address, the device owns this memory until | |
ceb5ac32 | 658 | * either swiotlb_unmap_page or swiotlb_dma_sync_single is performed. |
1da177e4 | 659 | */ |
f98eee8e FT |
660 | dma_addr_t swiotlb_map_page(struct device *dev, struct page *page, |
661 | unsigned long offset, size_t size, | |
662 | enum dma_data_direction dir, | |
663 | struct dma_attrs *attrs) | |
1da177e4 | 664 | { |
f98eee8e | 665 | phys_addr_t phys = page_to_phys(page) + offset; |
862d196b | 666 | dma_addr_t dev_addr = phys_to_dma(dev, phys); |
1da177e4 LT |
667 | void *map; |
668 | ||
34814545 | 669 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 670 | /* |
ceb5ac32 | 671 | * If the address happens to be in the device's DMA window, |
1da177e4 LT |
672 | * we can safely return the device addr and not worry about bounce |
673 | * buffering it. | |
674 | */ | |
b9394647 | 675 | if (dma_capable(dev, dev_addr, size) && !swiotlb_force) |
1da177e4 LT |
676 | return dev_addr; |
677 | ||
678 | /* | |
679 | * Oh well, have to allocate and map a bounce buffer. | |
680 | */ | |
f98eee8e | 681 | map = map_single(dev, phys, size, dir); |
1da177e4 | 682 | if (!map) { |
f98eee8e | 683 | swiotlb_full(dev, size, dir, 1); |
1da177e4 LT |
684 | map = io_tlb_overflow_buffer; |
685 | } | |
686 | ||
f98eee8e | 687 | dev_addr = swiotlb_virt_to_bus(dev, map); |
1da177e4 LT |
688 | |
689 | /* | |
690 | * Ensure that the address returned is DMA'ble | |
691 | */ | |
fba99fa3 FT |
692 | if (!dma_capable(dev, dev_addr, size)) { |
693 | swiotlb_tbl_unmap_single(dev, map, size, dir); | |
694 | dev_addr = swiotlb_virt_to_bus(dev, io_tlb_overflow_buffer); | |
695 | } | |
1da177e4 LT |
696 | |
697 | return dev_addr; | |
698 | } | |
f98eee8e | 699 | EXPORT_SYMBOL_GPL(swiotlb_map_page); |
1da177e4 | 700 | |
1da177e4 LT |
701 | /* |
702 | * Unmap a single streaming mode DMA translation. The dma_addr and size must | |
ceb5ac32 | 703 | * match what was provided for in a previous swiotlb_map_page call. All |
1da177e4 LT |
704 | * other usages are undefined. |
705 | * | |
706 | * After this call, reads by the cpu to the buffer are guaranteed to see | |
707 | * whatever the device wrote there. | |
708 | */ | |
7fcebbd2 | 709 | static void unmap_single(struct device *hwdev, dma_addr_t dev_addr, |
22d48269 | 710 | size_t size, enum dma_data_direction dir) |
1da177e4 | 711 | { |
862d196b | 712 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
1da177e4 | 713 | |
34814545 | 714 | BUG_ON(dir == DMA_NONE); |
7fcebbd2 | 715 | |
02ca646e | 716 | if (is_swiotlb_buffer(paddr)) { |
bfc5501f | 717 | swiotlb_tbl_unmap_single(hwdev, phys_to_virt(paddr), size, dir); |
7fcebbd2 BB |
718 | return; |
719 | } | |
720 | ||
721 | if (dir != DMA_FROM_DEVICE) | |
722 | return; | |
723 | ||
02ca646e FT |
724 | /* |
725 | * phys_to_virt doesn't work with hihgmem page but we could | |
726 | * call dma_mark_clean() with hihgmem page here. However, we | |
727 | * are fine since dma_mark_clean() is null on POWERPC. We can | |
728 | * make dma_mark_clean() take a physical address if necessary. | |
729 | */ | |
730 | dma_mark_clean(phys_to_virt(paddr), size); | |
7fcebbd2 BB |
731 | } |
732 | ||
733 | void swiotlb_unmap_page(struct device *hwdev, dma_addr_t dev_addr, | |
734 | size_t size, enum dma_data_direction dir, | |
735 | struct dma_attrs *attrs) | |
736 | { | |
737 | unmap_single(hwdev, dev_addr, size, dir); | |
1da177e4 | 738 | } |
f98eee8e | 739 | EXPORT_SYMBOL_GPL(swiotlb_unmap_page); |
874d6a95 | 740 | |
1da177e4 LT |
741 | /* |
742 | * Make physical memory consistent for a single streaming mode DMA translation | |
743 | * after a transfer. | |
744 | * | |
ceb5ac32 | 745 | * If you perform a swiotlb_map_page() but wish to interrogate the buffer |
17e5ad6c TL |
746 | * using the cpu, yet do not wish to teardown the dma mapping, you must |
747 | * call this function before doing so. At the next point you give the dma | |
1da177e4 LT |
748 | * address back to the card, you must first perform a |
749 | * swiotlb_dma_sync_for_device, and then the device again owns the buffer | |
750 | */ | |
be6b0267 | 751 | static void |
8270f3f1 | 752 | swiotlb_sync_single(struct device *hwdev, dma_addr_t dev_addr, |
d7ef1533 KRW |
753 | size_t size, enum dma_data_direction dir, |
754 | enum dma_sync_target target) | |
1da177e4 | 755 | { |
862d196b | 756 | phys_addr_t paddr = dma_to_phys(hwdev, dev_addr); |
1da177e4 | 757 | |
34814545 | 758 | BUG_ON(dir == DMA_NONE); |
380d6878 | 759 | |
02ca646e | 760 | if (is_swiotlb_buffer(paddr)) { |
bfc5501f KRW |
761 | swiotlb_tbl_sync_single(hwdev, phys_to_virt(paddr), size, dir, |
762 | target); | |
380d6878 BB |
763 | return; |
764 | } | |
765 | ||
766 | if (dir != DMA_FROM_DEVICE) | |
767 | return; | |
768 | ||
02ca646e | 769 | dma_mark_clean(phys_to_virt(paddr), size); |
1da177e4 LT |
770 | } |
771 | ||
8270f3f1 JL |
772 | void |
773 | swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 774 | size_t size, enum dma_data_direction dir) |
8270f3f1 | 775 | { |
de69e0f0 | 776 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_CPU); |
8270f3f1 | 777 | } |
874d6a95 | 778 | EXPORT_SYMBOL(swiotlb_sync_single_for_cpu); |
8270f3f1 | 779 | |
1da177e4 LT |
780 | void |
781 | swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr, | |
160c1d8e | 782 | size_t size, enum dma_data_direction dir) |
1da177e4 | 783 | { |
de69e0f0 | 784 | swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_DEVICE); |
1da177e4 | 785 | } |
874d6a95 | 786 | EXPORT_SYMBOL(swiotlb_sync_single_for_device); |
1da177e4 LT |
787 | |
788 | /* | |
789 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
ceb5ac32 | 790 | * This is the scatter-gather version of the above swiotlb_map_page |
1da177e4 LT |
791 | * interface. Here the scatter gather list elements are each tagged with the |
792 | * appropriate dma address and length. They are obtained via | |
793 | * sg_dma_{address,length}(SG). | |
794 | * | |
795 | * NOTE: An implementation may be able to use a smaller number of | |
796 | * DMA address/length pairs than there are SG table elements. | |
797 | * (for example via virtual mapping capabilities) | |
798 | * The routine returns the number of addr/length pairs actually | |
799 | * used, at most nents. | |
800 | * | |
ceb5ac32 | 801 | * Device ownership issues as mentioned above for swiotlb_map_page are the |
1da177e4 LT |
802 | * same here. |
803 | */ | |
804 | int | |
309df0c5 | 805 | swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems, |
160c1d8e | 806 | enum dma_data_direction dir, struct dma_attrs *attrs) |
1da177e4 | 807 | { |
dbfd49fe | 808 | struct scatterlist *sg; |
1da177e4 LT |
809 | int i; |
810 | ||
34814545 | 811 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 812 | |
dbfd49fe | 813 | for_each_sg(sgl, sg, nelems, i) { |
961d7d0e | 814 | phys_addr_t paddr = sg_phys(sg); |
862d196b | 815 | dma_addr_t dev_addr = phys_to_dma(hwdev, paddr); |
bc40ac66 | 816 | |
cf56e3f2 | 817 | if (swiotlb_force || |
b9394647 | 818 | !dma_capable(hwdev, dev_addr, sg->length)) { |
bc40ac66 BB |
819 | void *map = map_single(hwdev, sg_phys(sg), |
820 | sg->length, dir); | |
7e870233 | 821 | if (!map) { |
1da177e4 LT |
822 | /* Don't panic here, we expect map_sg users |
823 | to do proper error handling. */ | |
824 | swiotlb_full(hwdev, sg->length, dir, 0); | |
309df0c5 AK |
825 | swiotlb_unmap_sg_attrs(hwdev, sgl, i, dir, |
826 | attrs); | |
dbfd49fe | 827 | sgl[0].dma_length = 0; |
1da177e4 LT |
828 | return 0; |
829 | } | |
70a7d3cc | 830 | sg->dma_address = swiotlb_virt_to_bus(hwdev, map); |
1da177e4 LT |
831 | } else |
832 | sg->dma_address = dev_addr; | |
833 | sg->dma_length = sg->length; | |
834 | } | |
835 | return nelems; | |
836 | } | |
309df0c5 AK |
837 | EXPORT_SYMBOL(swiotlb_map_sg_attrs); |
838 | ||
839 | int | |
840 | swiotlb_map_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, | |
22d48269 | 841 | enum dma_data_direction dir) |
309df0c5 AK |
842 | { |
843 | return swiotlb_map_sg_attrs(hwdev, sgl, nelems, dir, NULL); | |
844 | } | |
874d6a95 | 845 | EXPORT_SYMBOL(swiotlb_map_sg); |
1da177e4 LT |
846 | |
847 | /* | |
848 | * Unmap a set of streaming mode DMA translations. Again, cpu read rules | |
ceb5ac32 | 849 | * concerning calls here are the same as for swiotlb_unmap_page() above. |
1da177e4 LT |
850 | */ |
851 | void | |
309df0c5 | 852 | swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl, |
160c1d8e | 853 | int nelems, enum dma_data_direction dir, struct dma_attrs *attrs) |
1da177e4 | 854 | { |
dbfd49fe | 855 | struct scatterlist *sg; |
1da177e4 LT |
856 | int i; |
857 | ||
34814545 | 858 | BUG_ON(dir == DMA_NONE); |
1da177e4 | 859 | |
7fcebbd2 BB |
860 | for_each_sg(sgl, sg, nelems, i) |
861 | unmap_single(hwdev, sg->dma_address, sg->dma_length, dir); | |
862 | ||
1da177e4 | 863 | } |
309df0c5 AK |
864 | EXPORT_SYMBOL(swiotlb_unmap_sg_attrs); |
865 | ||
866 | void | |
867 | swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sgl, int nelems, | |
22d48269 | 868 | enum dma_data_direction dir) |
309df0c5 AK |
869 | { |
870 | return swiotlb_unmap_sg_attrs(hwdev, sgl, nelems, dir, NULL); | |
871 | } | |
874d6a95 | 872 | EXPORT_SYMBOL(swiotlb_unmap_sg); |
1da177e4 LT |
873 | |
874 | /* | |
875 | * Make physical memory consistent for a set of streaming mode DMA translations | |
876 | * after a transfer. | |
877 | * | |
878 | * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules | |
879 | * and usage. | |
880 | */ | |
be6b0267 | 881 | static void |
dbfd49fe | 882 | swiotlb_sync_sg(struct device *hwdev, struct scatterlist *sgl, |
d7ef1533 KRW |
883 | int nelems, enum dma_data_direction dir, |
884 | enum dma_sync_target target) | |
1da177e4 | 885 | { |
dbfd49fe | 886 | struct scatterlist *sg; |
1da177e4 LT |
887 | int i; |
888 | ||
380d6878 BB |
889 | for_each_sg(sgl, sg, nelems, i) |
890 | swiotlb_sync_single(hwdev, sg->dma_address, | |
de69e0f0 | 891 | sg->dma_length, dir, target); |
1da177e4 LT |
892 | } |
893 | ||
8270f3f1 JL |
894 | void |
895 | swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 896 | int nelems, enum dma_data_direction dir) |
8270f3f1 | 897 | { |
de69e0f0 | 898 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_CPU); |
8270f3f1 | 899 | } |
874d6a95 | 900 | EXPORT_SYMBOL(swiotlb_sync_sg_for_cpu); |
8270f3f1 | 901 | |
1da177e4 LT |
902 | void |
903 | swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg, | |
160c1d8e | 904 | int nelems, enum dma_data_direction dir) |
1da177e4 | 905 | { |
de69e0f0 | 906 | swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_DEVICE); |
1da177e4 | 907 | } |
874d6a95 | 908 | EXPORT_SYMBOL(swiotlb_sync_sg_for_device); |
1da177e4 LT |
909 | |
910 | int | |
8d8bb39b | 911 | swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr) |
1da177e4 | 912 | { |
70a7d3cc | 913 | return (dma_addr == swiotlb_virt_to_bus(hwdev, io_tlb_overflow_buffer)); |
1da177e4 | 914 | } |
874d6a95 | 915 | EXPORT_SYMBOL(swiotlb_dma_mapping_error); |
1da177e4 LT |
916 | |
917 | /* | |
17e5ad6c | 918 | * Return whether the given device DMA address mask can be supported |
1da177e4 | 919 | * properly. For example, if your device can only drive the low 24-bits |
17e5ad6c | 920 | * during bus mastering, then you would pass 0x00ffffff as the mask to |
1da177e4 LT |
921 | * this function. |
922 | */ | |
923 | int | |
563aaf06 | 924 | swiotlb_dma_supported(struct device *hwdev, u64 mask) |
1da177e4 | 925 | { |
70a7d3cc | 926 | return swiotlb_virt_to_bus(hwdev, io_tlb_end - 1) <= mask; |
1da177e4 | 927 | } |
1da177e4 | 928 | EXPORT_SYMBOL(swiotlb_dma_supported); |