Commit | Line | Data |
---|---|---|
14b456f2 AV |
1 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
2 | Michael Collison <michael.collison@arm.com> | |
3 | ||
4 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
5 | (enum mve_instructions): Likewise. | |
6 | (enum mve_undefined): Add new reasons. | |
7 | (is_mve_encoding_conflict): Handle new instructions. | |
8 | (is_mve_undefined): Likewise. | |
9 | (is_mve_unpredictable): Likewise. | |
10 | (print_mve_undefined): Likewise. | |
11 | (print_mve_size): Likewise. | |
12 | ||
f49bb598 AV |
13 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
14 | Michael Collison <michael.collison@arm.com> | |
15 | ||
16 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
17 | (enum mve_instructions): Likewise. | |
18 | (is_mve_encoding_conflict): Handle new instructions. | |
19 | (is_mve_undefined): Likewise. | |
20 | (is_mve_unpredictable): Likewise. | |
21 | (print_mve_size): Likewise. | |
22 | ||
56858bea AV |
23 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
24 | Michael Collison <michael.collison@arm.com> | |
25 | ||
26 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
27 | (enum mve_instructions): Likewise. | |
28 | (is_mve_encoding_conflict): Likewise. | |
29 | (is_mve_unpredictable): Likewise. | |
30 | (print_mve_size): Likewise. | |
31 | ||
e523f101 AV |
32 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
33 | Michael Collison <michael.collison@arm.com> | |
34 | ||
35 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
36 | (enum mve_instructions): Likewise. | |
37 | (is_mve_encoding_conflict): Handle new instructions. | |
38 | (is_mve_undefined): Likewise. | |
39 | (is_mve_unpredictable): Likewise. | |
40 | (print_mve_size): Likewise. | |
41 | ||
66dcaa5d AV |
42 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
43 | Michael Collison <michael.collison@arm.com> | |
44 | ||
45 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
46 | (enum mve_instructions): Likewise. | |
47 | (is_mve_encoding_conflict): Handle new instructions. | |
48 | (is_mve_undefined): Likewise. | |
49 | (is_mve_unpredictable): Likewise. | |
50 | (print_mve_size): Likewise. | |
51 | (print_insn_mve): Likewise. | |
52 | ||
d052b9b7 AV |
53 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
54 | Michael Collison <michael.collison@arm.com> | |
55 | ||
56 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
57 | (print_insn_thumb32): Handle new instructions. | |
58 | ||
ed63aa17 AV |
59 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
60 | Michael Collison <michael.collison@arm.com> | |
61 | ||
62 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
63 | (enum mve_undefined): Add new reasons. | |
64 | (is_mve_encoding_conflict): Handle new instructions. | |
65 | (is_mve_undefined): Likewise. | |
66 | (is_mve_unpredictable): Likewise. | |
67 | (print_mve_undefined): Likewise. | |
68 | (print_mve_size): Likewise. | |
69 | (print_mve_shift_n): Likewise. | |
70 | (print_insn_mve): Likewise. | |
71 | ||
897b9bbc AV |
72 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
73 | Michael Collison <michael.collison@arm.com> | |
74 | ||
75 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
76 | (is_mve_encoding_conflict): Handle new instructions. | |
77 | (is_mve_unpredictable): Likewise. | |
78 | (print_mve_rotate): Likewise. | |
79 | (print_mve_size): Likewise. | |
80 | (print_insn_mve): Likewise. | |
81 | ||
1c8f2df8 AV |
82 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
83 | Michael Collison <michael.collison@arm.com> | |
84 | ||
85 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
86 | (is_mve_encoding_conflict): Handle new instructions. | |
87 | (is_mve_unpredictable): Likewise. | |
88 | (print_mve_size): Likewise. | |
89 | (print_insn_mve): Likewise. | |
90 | ||
d3b63143 AV |
91 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
92 | Michael Collison <michael.collison@arm.com> | |
93 | ||
94 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
95 | (enum mve_undefined): Add new reasons. | |
96 | (is_mve_encoding_conflict): Handle new instructions. | |
97 | (is_mve_undefined): Likewise. | |
98 | (is_mve_unpredictable): Likewise. | |
99 | (print_mve_undefined): Likewise. | |
100 | (print_mve_size): Likewise. | |
101 | (print_insn_mve): Likewise. | |
102 | ||
14925797 AV |
103 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
104 | Michael Collison <michael.collison@arm.com> | |
105 | ||
106 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
107 | (is_mve_encoding_conflict): Handle new instructions. | |
108 | (is_mve_undefined): Likewise. | |
109 | (is_mve_unpredictable): Likewise. | |
110 | (print_mve_size): Likewise. | |
111 | (print_insn_mve): Likewise. | |
112 | ||
c507f10b AV |
113 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
114 | Michael Collison <michael.collison@arm.com> | |
115 | ||
116 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
117 | (enum mve_unpredictable): Add new reasons. | |
118 | (enum mve_undefined): Likewise. | |
119 | (is_mve_okay_in_it): Handle new isntructions. | |
120 | (is_mve_encoding_conflict): Likewise. | |
121 | (is_mve_undefined): Likewise. | |
122 | (is_mve_unpredictable): Likewise. | |
123 | (print_mve_vmov_index): Likewise. | |
124 | (print_simd_imm8): Likewise. | |
125 | (print_mve_undefined): Likewise. | |
126 | (print_mve_unpredictable): Likewise. | |
127 | (print_mve_size): Likewise. | |
128 | (print_insn_mve): Likewise. | |
129 | ||
bf0b396d AV |
130 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
131 | Michael Collison <michael.collison@arm.com> | |
132 | ||
133 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
134 | (enum mve_unpredictable): Add new reasons. | |
135 | (enum mve_undefined): Likewise. | |
136 | (is_mve_encoding_conflict): Handle new instructions. | |
137 | (is_mve_undefined): Likewise. | |
138 | (is_mve_unpredictable): Likewise. | |
139 | (print_mve_undefined): Likewise. | |
140 | (print_mve_unpredictable): Likewise. | |
141 | (print_mve_rounding_mode): Likewise. | |
142 | (print_mve_vcvt_size): Likewise. | |
143 | (print_mve_size): Likewise. | |
144 | (print_insn_mve): Likewise. | |
145 | ||
ef1576a1 AV |
146 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
147 | Michael Collison <michael.collison@arm.com> | |
148 | ||
149 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
150 | (enum mve_unpredictable): Add new reasons. | |
151 | (enum mve_undefined): Likewise. | |
152 | (is_mve_undefined): Handle new instructions. | |
153 | (is_mve_unpredictable): Likewise. | |
154 | (print_mve_undefined): Likewise. | |
155 | (print_mve_unpredictable): Likewise. | |
156 | (print_mve_size): Likewise. | |
157 | (print_insn_mve): Likewise. | |
158 | ||
aef6d006 AV |
159 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
160 | Michael Collison <michael.collison@arm.com> | |
161 | ||
162 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
163 | (enum mve_undefined): Add new reasons. | |
164 | (insns): Add new instructions. | |
165 | (is_mve_encoding_conflict): | |
166 | (print_mve_vld_str_addr): New print function. | |
167 | (is_mve_undefined): Handle new instructions. | |
168 | (is_mve_unpredictable): Likewise. | |
169 | (print_mve_undefined): Likewise. | |
170 | (print_mve_size): Likewise. | |
171 | (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions. | |
172 | (print_insn_mve): Handle new operands. | |
173 | ||
04d54ace AV |
174 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
175 | Michael Collison <michael.collison@arm.com> | |
176 | ||
177 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
178 | (enum mve_unpredictable): Add new reasons. | |
179 | (is_mve_encoding_conflict): Handle new instructions. | |
180 | (is_mve_unpredictable): Likewise. | |
181 | (mve_opcodes): Add new instructions. | |
182 | (print_mve_unpredictable): Handle new reasons. | |
183 | (print_mve_register_blocks): New print function. | |
184 | (print_mve_size): Handle new instructions. | |
185 | (print_insn_mve): Likewise. | |
186 | ||
9743db03 AV |
187 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
188 | Michael Collison <michael.collison@arm.com> | |
189 | ||
190 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
191 | (enum mve_unpredictable): Add new reasons. | |
192 | (enum mve_undefined): Likewise. | |
193 | (is_mve_encoding_conflict): Handle new instructions. | |
194 | (is_mve_undefined): Likewise. | |
195 | (is_mve_unpredictable): Likewise. | |
196 | (coprocessor_opcodes): Move NEON VDUP from here... | |
197 | (neon_opcodes): ... to here. | |
198 | (mve_opcodes): Add new instructions. | |
199 | (print_mve_undefined): Handle new reasons. | |
200 | (print_mve_unpredictable): Likewise. | |
201 | (print_mve_size): Handle new instructions. | |
202 | (print_insn_neon): Handle vdup. | |
203 | (print_insn_mve): Handle new operands. | |
204 | ||
143275ea AV |
205 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
206 | Michael Collison <michael.collison@arm.com> | |
207 | ||
208 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
209 | (enum mve_unpredictable): Add new values. | |
210 | (mve_opcodes): Add new instructions. | |
211 | (vec_condnames): New array with vector conditions. | |
212 | (mve_predicatenames): New array with predicate suffixes. | |
213 | (mve_vec_sizename): New array with vector sizes. | |
214 | (enum vpt_pred_state): New enum with vector predication states. | |
215 | (struct vpt_block): New struct type for vpt blocks. | |
216 | (vpt_block_state): Global struct to keep track of state. | |
217 | (mve_extract_pred_mask): New helper function. | |
218 | (num_instructions_vpt_block): Likewise. | |
219 | (mark_outside_vpt_block): Likewise. | |
220 | (mark_inside_vpt_block): Likewise. | |
221 | (invert_next_predicate_state): Likewise. | |
222 | (update_next_predicate_state): Likewise. | |
223 | (update_vpt_block_state): Likewise. | |
224 | (is_vpt_instruction): Likewise. | |
225 | (is_mve_encoding_conflict): Add entries for new instructions. | |
226 | (is_mve_unpredictable): Likewise. | |
227 | (print_mve_unpredictable): Handle new cases. | |
228 | (print_instruction_predicate): Likewise. | |
229 | (print_mve_size): New function. | |
230 | (print_vec_condition): New function. | |
231 | (print_insn_mve): Handle vpt blocks and new print operands. | |
232 | ||
f08d8ce3 AV |
233 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
234 | ||
235 | * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors | |
236 | 8, 14 and 15 for Armv8.1-M Mainline. | |
237 | ||
73cd51e5 AV |
238 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
239 | Michael Collison <michael.collison@arm.com> | |
240 | ||
241 | * arm-dis.c (enum mve_instructions): New enum. | |
242 | (enum mve_unpredictable): Likewise. | |
243 | (enum mve_undefined): Likewise. | |
244 | (struct mopcode32): New struct. | |
245 | (is_mve_okay_in_it): New function. | |
246 | (is_mve_architecture): Likewise. | |
247 | (arm_decode_field): Likewise. | |
248 | (arm_decode_field_multiple): Likewise. | |
249 | (is_mve_encoding_conflict): Likewise. | |
250 | (is_mve_undefined): Likewise. | |
251 | (is_mve_unpredictable): Likewise. | |
252 | (print_mve_undefined): Likewise. | |
253 | (print_mve_unpredictable): Likewise. | |
254 | (print_insn_coprocessor_1): Use arm_decode_field_multiple. | |
255 | (print_insn_mve): New function. | |
256 | (print_insn_thumb32): Handle MVE architecture. | |
257 | (select_arm_features): Force thumb for Armv8.1-m Mainline. | |
258 | ||
3076e594 NC |
259 | 2019-05-10 Nick Clifton <nickc@redhat.com> |
260 | ||
261 | PR 24538 | |
262 | * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the | |
263 | end of the table prematurely. | |
264 | ||
387e7624 FS |
265 | 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com> |
266 | ||
267 | * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB | |
268 | macros for R6. | |
269 | ||
0067be51 AM |
270 | 2019-05-11 Alan Modra <amodra@gmail.com> |
271 | ||
272 | * ppc-dis.c (print_insn_powerpc) Don't skip optional operands | |
273 | when -Mraw is in effect. | |
274 | ||
42e6288f MM |
275 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
276 | ||
277 | * aarch64-dis-2.c: Regenerate. | |
278 | * aarch64-tbl.h (OP_SVE_BBU): New variant set. | |
279 | (OP_SVE_BBB): New variant set. | |
280 | (OP_SVE_DDDD): New variant set. | |
281 | (OP_SVE_HHH): New variant set. | |
282 | (OP_SVE_HHHU): New variant set. | |
283 | (OP_SVE_SSS): New variant set. | |
284 | (OP_SVE_SSSU): New variant set. | |
285 | (OP_SVE_SHH): New variant set. | |
286 | (OP_SVE_SBBU): New variant set. | |
287 | (OP_SVE_DSS): New variant set. | |
288 | (OP_SVE_DHHU): New variant set. | |
289 | (OP_SVE_VMV_HSD_BHS): New variant set. | |
290 | (OP_SVE_VVU_HSD_BHS): New variant set. | |
291 | (OP_SVE_VVVU_SD_BH): New variant set. | |
292 | (OP_SVE_VVVU_BHSD): New variant set. | |
293 | (OP_SVE_VVV_QHD_DBS): New variant set. | |
294 | (OP_SVE_VVV_HSD_BHS): New variant set. | |
295 | (OP_SVE_VVV_HSD_BHS2): New variant set. | |
296 | (OP_SVE_VVV_BHS_HSD): New variant set. | |
297 | (OP_SVE_VV_BHS_HSD): New variant set. | |
298 | (OP_SVE_VVV_SD): New variant set. | |
299 | (OP_SVE_VVU_BHS_HSD): New variant set. | |
300 | (OP_SVE_VZVV_SD): New variant set. | |
301 | (OP_SVE_VZVV_BH): New variant set. | |
302 | (OP_SVE_VZV_SD): New variant set. | |
303 | (aarch64_opcode_table): Add sve2 instructions. | |
304 | ||
28ed815a MM |
305 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
306 | ||
307 | * aarch64-asm-2.c: Regenerated. | |
308 | * aarch64-dis-2.c: Regenerated. | |
309 | * aarch64-opc-2.c: Regenerated. | |
310 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
311 | for SVE_SHLIMM_UNPRED_22. | |
312 | (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. | |
313 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 | |
314 | operand. | |
315 | ||
fd1dc4a0 MM |
316 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
317 | ||
318 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
319 | sve_size_tsz_bhs iclass encode. | |
320 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
321 | sve_size_tsz_bhs iclass decode. | |
322 | ||
31e36ab3 MM |
323 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
324 | ||
325 | * aarch64-asm-2.c: Regenerated. | |
326 | * aarch64-dis-2.c: Regenerated. | |
327 | * aarch64-opc-2.c: Regenerated. | |
328 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
329 | for SVE_Zm4_11_INDEX. | |
330 | (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. | |
331 | (fields): Handle SVE_i2h field. | |
332 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. | |
333 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand. | |
334 | ||
1be5f94f MM |
335 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
336 | ||
337 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
338 | sve_shift_tsz_bhsd iclass encode. | |
339 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
340 | sve_shift_tsz_bhsd iclass decode. | |
341 | ||
3c17238b MM |
342 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
343 | ||
344 | * aarch64-asm-2.c: Regenerated. | |
345 | * aarch64-dis-2.c: Regenerated. | |
346 | * aarch64-opc-2.c: Regenerated. | |
347 | * aarch64-asm.c (aarch64_ins_sve_shrimm): | |
348 | (aarch64_encode_variant_using_iclass): Handle | |
349 | sve_shift_tsz_hsd iclass encode. | |
350 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
351 | sve_shift_tsz_hsd iclass decode. | |
352 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
353 | for SVE_SHRIMM_UNPRED_22. | |
354 | (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. | |
355 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 | |
356 | operand. | |
357 | ||
cd50a87a MM |
358 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
359 | ||
360 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
361 | sve_size_013 iclass encode. | |
362 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
363 | sve_size_013 iclass decode. | |
364 | ||
3c705960 MM |
365 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
366 | ||
367 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
368 | sve_size_bh iclass encode. | |
369 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
370 | sve_size_bh iclass decode. | |
371 | ||
0a57e14f MM |
372 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
373 | ||
374 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
375 | sve_size_sd2 iclass encode. | |
376 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
377 | sve_size_sd2 iclass decode. | |
378 | * aarch64-opc.c (fields): Handle SVE_sz2 field. | |
379 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field. | |
380 | ||
c469c864 MM |
381 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
382 | ||
383 | * aarch64-asm-2.c: Regenerated. | |
384 | * aarch64-dis-2.c: Regenerated. | |
385 | * aarch64-opc-2.c: Regenerated. | |
386 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
387 | for SVE_ADDR_ZX. | |
388 | (aarch64_print_operand): Add printing for SVE_ADDR_ZX. | |
389 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand. | |
390 | ||
116adc27 MM |
391 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
392 | ||
393 | * aarch64-asm-2.c: Regenerated. | |
394 | * aarch64-dis-2.c: Regenerated. | |
395 | * aarch64-opc-2.c: Regenerated. | |
396 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
397 | for SVE_Zm3_11_INDEX. | |
398 | (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. | |
399 | (fields): Handle SVE_i3l and SVE_i3h2 fields. | |
400 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 | |
401 | fields. | |
402 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand. | |
403 | ||
3bd82c86 MM |
404 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
405 | ||
406 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
407 | sve_size_hsd2 iclass encode. | |
408 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
409 | sve_size_hsd2 iclass decode. | |
410 | * aarch64-opc.c (fields): Handle SVE_size field. | |
411 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field. | |
412 | ||
adccc507 MM |
413 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
414 | ||
415 | * aarch64-asm-2.c: Regenerated. | |
416 | * aarch64-dis-2.c: Regenerated. | |
417 | * aarch64-opc-2.c: Regenerated. | |
418 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
419 | for SVE_IMM_ROT3. | |
420 | (aarch64_print_operand): Add printing for SVE_IMM_ROT3. | |
421 | (fields): Handle SVE_rot3 field. | |
422 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. | |
423 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand. | |
424 | ||
5cd99750 MM |
425 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
426 | ||
427 | * aarch64-opc.c (verify_constraints): Check for movprfx for sve2 | |
428 | instructions. | |
429 | ||
7ce2460a MM |
430 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
431 | ||
432 | * aarch64-tbl.h | |
433 | (aarch64_feature_sve2, aarch64_feature_sve2aes, | |
434 | aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, | |
435 | aarch64_feature_sve2bitperm): New feature sets. | |
436 | (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros | |
437 | for feature set addresses. | |
438 | (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, | |
439 | SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros. | |
440 | ||
41cee089 FS |
441 | 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com> |
442 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
443 | ||
444 | * mips-dis.c (mips_calculate_combination_ases): Add ISA | |
445 | argument and set ASE_EVA_R6 appropriately. | |
446 | (set_default_mips_dis_options): Pass ISA to above. | |
447 | (parse_mips_dis_option): Likewise. | |
448 | * mips-opc.c (EVAR6): New macro. | |
449 | (mips_builtin_opcodes): Add llwpe, scwpe. | |
450 | ||
b83b4b13 SD |
451 | 2019-05-01 Sudakshina Das <sudi.das@arm.com> |
452 | ||
453 | * aarch64-asm-2.c: Regenerated. | |
454 | * aarch64-dis-2.c: Regenerated. | |
455 | * aarch64-opc-2.c: Regenerated. | |
456 | * aarch64-opc.c (operand_general_constraint_met_p): Add case for | |
457 | AARCH64_OPND_TME_UIMM16. | |
458 | (aarch64_print_operand): Likewise. | |
459 | * aarch64-tbl.h (QL_IMM_NIL): New. | |
460 | (TME): New. | |
461 | (_TME_INSN): New. | |
462 | (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel. | |
463 | ||
4a90ce95 JD |
464 | 2019-04-29 John Darrington <john@darrington.wattle.id.au> |
465 | ||
466 | * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. | |
467 | ||
a45328b9 AB |
468 | 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com> |
469 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
470 | ||
471 | * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp. | |
472 | ||
d10be0cb JD |
473 | 2019-04-24 John Darrington <john@darrington.wattle.id.au> |
474 | ||
475 | * s12z-opc.h: Add extern "C" bracketing to help | |
476 | users who wish to use this interface in c++ code. | |
477 | ||
a679f24e JD |
478 | 2019-04-24 John Darrington <john@darrington.wattle.id.au> |
479 | ||
480 | * s12z-opc.c (bm_decode): Handle bit map operations with the | |
481 | "reserved0" mode. | |
482 | ||
32c36c3c AV |
483 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
484 | ||
485 | * arm-dis.c (coprocessor_opcodes): Document new %J and %K format | |
486 | specifier. Add entries for VLDR and VSTR of system registers. | |
487 | (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in | |
488 | coprocessor instructions on Armv8.1-M Mainline targets. Add handling | |
489 | of %J and %K format specifier. | |
490 | ||
efd6b359 AV |
491 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
492 | ||
493 | * arm-dis.c (coprocessor_opcodes): Document new %C format control code. | |
494 | Add new entries for VSCCLRM instruction. | |
495 | (print_insn_coprocessor): Handle new %C format control code. | |
496 | ||
6b0dd094 AV |
497 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
498 | ||
499 | * arm-dis.c (enum isa): New enum. | |
500 | (struct sopcode32): New structure. | |
501 | (coprocessor_opcodes): change type of entries to struct sopcode32 and | |
502 | set isa field of all current entries to ANY. | |
503 | (print_insn_coprocessor): Change type of insn to struct sopcode32. | |
504 | Only match an entry if its isa field allows the current mode. | |
505 | ||
4b5a202f AV |
506 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
507 | ||
508 | * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for | |
509 | CLRM. | |
510 | (print_insn_thumb32): Add logic to print %n CLRM register list. | |
511 | ||
60f993ce AV |
512 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
513 | ||
514 | * arm-dis.c (print_insn_thumb32): Updated to accept new %P | |
515 | and %Q patterns. | |
516 | ||
f6b2b12d AV |
517 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
518 | ||
519 | * arm-dis.c (thumb32_opcodes): New instruction bfcsel. | |
520 | (print_insn_thumb32): Edit the switch case for %Z. | |
521 | ||
1889da70 AV |
522 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
523 | ||
524 | * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern. | |
525 | ||
65d1bc05 AV |
526 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
527 | ||
528 | * arm-dis.c (thumb32_opcodes): New instruction bfl. | |
529 | ||
1caf72a5 AV |
530 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
531 | ||
532 | * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern. | |
533 | ||
f1c7f421 AV |
534 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
535 | ||
536 | * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an | |
537 | Arm register with r13 and r15 unpredictable. | |
538 | (thumb32_opcodes): New instructions for bfx and bflx. | |
539 | ||
4389b29a AV |
540 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
541 | ||
542 | * arm-dis.c (thumb32_opcodes): New instructions for bf. | |
543 | ||
e5d6e09e AV |
544 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
545 | ||
546 | * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern. | |
547 | ||
e12437dc AV |
548 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
549 | ||
550 | * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern. | |
551 | ||
031254f2 AV |
552 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
553 | ||
554 | * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline. | |
555 | ||
e5a557ac JD |
556 | 2019-04-12 John Darrington <john@darrington.wattle.id.au> |
557 | ||
558 | s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with | |
559 | "optr". ("operator" is a reserved word in c++). | |
560 | ||
bd7ceb8d SD |
561 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
562 | ||
563 | * aarch64-opc.c (aarch64_print_operand): Add case for | |
564 | AARCH64_OPND_Rt_SP. | |
565 | (verify_constraints): Likewise. | |
566 | * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. | |
567 | (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions | |
568 | to accept Rt|SP as first operand. | |
569 | (AARCH64_OPERANDS): Add new Rt_SP. | |
570 | * aarch64-asm-2.c: Regenerated. | |
571 | * aarch64-dis-2.c: Regenerated. | |
572 | * aarch64-opc-2.c: Regenerated. | |
573 | ||
e54010f1 SD |
574 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
575 | ||
576 | * aarch64-asm-2.c: Regenerated. | |
577 | * aarch64-dis-2.c: Likewise. | |
578 | * aarch64-opc-2.c: Likewise. | |
579 | * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm. | |
580 | ||
7e96e219 RS |
581 | 2019-04-09 Robert Suchanek <robert.suchanek@mips.com> |
582 | ||
583 | * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. | |
584 | ||
6f2791d5 L |
585 | 2019-04-08 H.J. Lu <hongjiu.lu@intel.com> |
586 | ||
587 | * i386-opc.tbl: Consolidate AVX512 BF16 entries. | |
588 | * i386-init.h: Regenerated. | |
589 | ||
e392bad3 AM |
590 | 2019-04-07 Alan Modra <amodra@gmail.com> |
591 | ||
592 | * ppc-dis.c (print_insn_powerpc): Use a tiny state machine | |
593 | op_separator to control printing of spaces, comma and parens | |
594 | rather than need_comma, need_paren and spaces vars. | |
595 | ||
dffaa15c AM |
596 | 2019-04-07 Alan Modra <amodra@gmail.com> |
597 | ||
598 | PR 24421 | |
599 | * arm-dis.c (print_insn_coprocessor): Correct bracket placement. | |
600 | (print_insn_neon, print_insn_arm): Likewise. | |
601 | ||
d6aab7a1 XG |
602 | 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> |
603 | ||
604 | * i386-dis-evex.h (evex_table): Updated to support BF16 | |
605 | instructions. | |
606 | * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 | |
607 | and EVEX_W_0F3872_P_3. | |
608 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. | |
609 | (cpu_flags): Add bitfield for CpuAVX512_BF16. | |
610 | * i386-opc.h (enum): Add CpuAVX512_BF16. | |
611 | (i386_cpu_flags): Add bitfield for cpuavx512_bf16. | |
612 | * i386-opc.tbl: Add AVX512 BF16 instructions. | |
613 | * i386-init.h: Regenerated. | |
614 | * i386-tbl.h: Likewise. | |
615 | ||
66e85460 AM |
616 | 2019-04-05 Alan Modra <amodra@gmail.com> |
617 | ||
618 | * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK. | |
619 | (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics | |
620 | to favour printing of "-" branch hint when using the "y" bit. | |
621 | Allow BH field on bc{ctr,lr,tar}{,l}{-,+}. | |
622 | ||
c2b1c275 AM |
623 | 2019-04-05 Alan Modra <amodra@gmail.com> |
624 | ||
625 | * ppc-dis.c (print_insn_powerpc): Delay printing spaces after | |
626 | opcode until first operand is output. | |
627 | ||
aae9718e PB |
628 | 2019-04-04 Peter Bergner <bergner@linux.ibm.com> |
629 | ||
630 | PR gas/24349 | |
631 | * ppc-opc.c (valid_bo_pre_v2): Add comments. | |
632 | (valid_bo_post_v2): Add support for 'at' branch hints. | |
633 | (insert_bo): Only error on branch on ctr. | |
634 | (get_bo_hint_mask): New function. | |
635 | (insert_boe): Add new 'branch_taken' formal argument. Add support | |
636 | for inserting 'at' branch hints. | |
637 | (extract_boe): Add new 'branch_taken' formal argument. Add support | |
638 | for extracting 'at' branch hints. | |
639 | (insert_bom, extract_bom, insert_bop, extract_bop): New functions. | |
640 | (BOE): Delete operand. | |
641 | (BOM, BOP): New operands. | |
642 | (RM): Update value. | |
643 | (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. | |
644 | (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-, | |
645 | bcctrl-, bctar-, bctarl->: Replace BOE with BOM. | |
646 | (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+, | |
647 | bcctrl+, bctar+, bctarl+>: Replace BOE with BOP. | |
648 | <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, | |
649 | bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, | |
650 | bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, | |
651 | bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, | |
652 | bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, | |
653 | bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, | |
654 | bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, | |
655 | bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, | |
656 | beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, | |
657 | bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, | |
658 | buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, | |
659 | bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, | |
660 | bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, | |
661 | bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, | |
662 | bttarl+>: New extended mnemonics. | |
663 | ||
96a86c01 AM |
664 | 2019-03-28 Alan Modra <amodra@gmail.com> |
665 | ||
666 | PR 24390 | |
667 | * ppc-opc.c (BTF): Define. | |
668 | (powerpc_opcodes): Use for mtfsb*. | |
669 | * ppc-dis.c (print_insn_powerpc): Print fields with both | |
670 | PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. | |
671 | ||
796d6298 TC |
672 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
673 | ||
674 | * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols. | |
675 | (mapping_symbol_for_insn): Implement new algorithm. | |
676 | (print_insn): Remove duplicate code. | |
677 | ||
60df3720 TC |
678 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
679 | ||
680 | * aarch64-dis.c (print_insn_aarch64): | |
681 | Implement override. | |
682 | ||
51457761 TC |
683 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
684 | ||
685 | * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search | |
686 | order. | |
687 | ||
53b2f36b TC |
688 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
689 | ||
690 | * aarch64-dis.c (last_stop_offset): New. | |
691 | (print_insn_aarch64): Use stop_offset. | |
692 | ||
89199bb5 L |
693 | 2019-03-19 H.J. Lu <hongjiu.lu@intel.com> |
694 | ||
695 | PR gas/24359 | |
696 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to | |
697 | CPU_ANY_AVX2_FLAGS. | |
698 | * i386-init.h: Regenerated. | |
699 | ||
97ed31ae L |
700 | 2019-03-18 H.J. Lu <hongjiu.lu@intel.com> |
701 | ||
702 | PR gas/24348 | |
703 | * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, | |
704 | vmovdqu16, vmovdqu32 and vmovdqu64. | |
705 | * i386-tbl.h: Regenerated. | |
706 | ||
0919bfe9 AK |
707 | 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> |
708 | ||
709 | * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand | |
710 | from vstrszb, vstrszh, and vstrszf. | |
711 | ||
712 | 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> | |
713 | ||
714 | * s390-opc.txt: Add instruction descriptions. | |
715 | ||
21820ebe JW |
716 | 2019-02-08 Jim Wilson <jimw@sifive.com> |
717 | ||
718 | * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form. | |
719 | <bne>: Likewise. | |
720 | ||
f7dd2fb2 TC |
721 | 2019-02-07 Tamar Christina <tamar.christina@arm.com> |
722 | ||
723 | * arm-dis.c (arm_opcodes): Redefine hlt to armv1. | |
724 | ||
6456d318 TC |
725 | 2019-02-07 Tamar Christina <tamar.christina@arm.com> |
726 | ||
727 | PR binutils/23212 | |
728 | * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. | |
729 | * aarch64-opc.c (verify_elem_sd): New. | |
730 | (fields): Add FLD_sz entr. | |
731 | * aarch64-tbl.h (_SIMD_INSN): New. | |
732 | (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and | |
733 | fmulx scalar and vector by element isns. | |
734 | ||
4a83b610 NC |
735 | 2019-02-07 Nick Clifton <nickc@redhat.com> |
736 | ||
737 | * po/sv.po: Updated Swedish translation. | |
738 | ||
fc60b8c8 AK |
739 | 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> |
740 | ||
741 | * s390-mkopc.c (main): Accept arch13 as cpu string. | |
742 | * s390-opc.c: Add new instruction formats and instruction opcode | |
743 | masks. | |
744 | * s390-opc.txt: Add new arch13 instructions. | |
745 | ||
e10620d3 TC |
746 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
747 | ||
748 | * aarch64-tbl.h (QL_LDST_AT): Update macro. | |
749 | (aarch64_opcode): Change encoding for stg, stzg | |
750 | st2g and st2zg. | |
751 | * aarch64-asm-2.c: Regenerated. | |
752 | * aarch64-dis-2.c: Regenerated. | |
753 | * aarch64-opc-2.c: Regenerated. | |
754 | ||
20a4ca55 SD |
755 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
756 | ||
757 | * aarch64-asm-2.c: Regenerated. | |
758 | * aarch64-dis-2.c: Likewise. | |
759 | * aarch64-opc-2.c: Likewise. | |
760 | * aarch64-tbl.h (aarch64_opcode): Add new stzgm. | |
761 | ||
550fd7bf SD |
762 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
763 | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | |
764 | ||
765 | * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. | |
766 | * aarch64-asm.h (ins_addr_simple_2): Likeiwse. | |
767 | * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. | |
768 | * aarch64-dis.h (ext_addr_simple_2): Likewise. | |
769 | * aarch64-opc.c (operand_general_constraint_met_p): Remove | |
770 | case for ldstgv_indexed. | |
771 | (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. | |
772 | * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. | |
773 | (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. | |
774 | * aarch64-asm-2.c: Regenerated. | |
775 | * aarch64-dis-2.c: Regenerated. | |
776 | * aarch64-opc-2.c: Regenerated. | |
777 | ||
d9938630 NC |
778 | 2019-01-23 Nick Clifton <nickc@redhat.com> |
779 | ||
780 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
781 | ||
375cd423 NC |
782 | 2019-01-21 Nick Clifton <nickc@redhat.com> |
783 | ||
784 | * po/de.po: Updated German translation. | |
785 | * po/uk.po: Updated Ukranian translation. | |
786 | ||
57299f48 CX |
787 | 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com> |
788 | * mips-dis.c (mips_arch_choices): Fix typo in | |
789 | gs464, gs464e and gs264e descriptors. | |
790 | ||
f48dfe41 NC |
791 | 2019-01-19 Nick Clifton <nickc@redhat.com> |
792 | ||
793 | * configure: Regenerate. | |
794 | * po/opcodes.pot: Regenerate. | |
795 | ||
f974f26c NC |
796 | 2018-06-24 Nick Clifton <nickc@redhat.com> |
797 | ||
798 | 2.32 branch created. | |
799 | ||
39f286cd JD |
800 | 2019-01-09 John Darrington <john@darrington.wattle.id.au> |
801 | ||
448b8ca8 JD |
802 | * s12z-dis.c (print_insn_s12z): Do not dereference an operand |
803 | if it is null. | |
804 | -dis.c (opr_emit_disassembly): Do not omit an index if it is | |
39f286cd JD |
805 | zero. |
806 | ||
3107326d AP |
807 | 2019-01-09 Andrew Paprocki <andrew@ishiboo.com> |
808 | ||
809 | * configure: Regenerate. | |
810 | ||
7e9ca91e AM |
811 | 2019-01-07 Alan Modra <amodra@gmail.com> |
812 | ||
813 | * configure: Regenerate. | |
814 | * po/POTFILES.in: Regenerate. | |
815 | ||
ef1ad42b JD |
816 | 2019-01-03 John Darrington <john@darrington.wattle.id.au> |
817 | ||
818 | * s12z-opc.c: New file. | |
819 | * s12z-opc.h: New file. | |
820 | * s12z-dis.c: Removed all code not directly related to display | |
821 | of instructions. Used the interface provided by the new files | |
822 | instead. | |
823 | * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. | |
7e9ca91e | 824 | * Makefile.in: Regenerate. |
ef1ad42b | 825 | * configure.ac (bfd_s12z_arch): Correct the dependencies. |
7e9ca91e | 826 | * configure: Regenerate. |
ef1ad42b | 827 | |
82704155 AM |
828 | 2019-01-01 Alan Modra <amodra@gmail.com> |
829 | ||
830 | Update year range in copyright notice of all files. | |
831 | ||
d5c04e1b | 832 | For older changes see ChangeLog-2018 |
3499769a | 833 | \f |
d5c04e1b | 834 | Copyright (C) 2019 Free Software Foundation, Inc. |
3499769a AM |
835 | |
836 | Copying and distribution of this file, with or without modification, | |
837 | are permitted in any medium without royalty provided the copyright | |
838 | notice and this notice are preserved. | |
839 | ||
840 | Local Variables: | |
841 | mode: change-log | |
842 | left-margin: 8 | |
843 | fill-column: 74 | |
844 | version-control: never | |
845 | End: |